CN1074557A - 半导体装置 - Google Patents
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- 239000002184 metal Substances 0.000 claims description 58
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
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Abstract
本发明涉及一半导体装置，包括电连接半导体装
置的金属导线至外壳引线的焊接块，以及一覆盖该焊
接块和金属导线的钝化层。该焊接块或金属导线具
有钝角或圆形拐角。钝化层中的裂纹的产生得到显
著抑制，从而提高了半导体装置的可靠性。
Description
本发明涉及半导体装置，更具体地说，涉及具有焊接块和金属导线的半导体装置。
一般来说，在半导体装置的最终金属层的图形成形之后，晶片的整个上表面均淀积一钝化层。这是一层防止晶片在后续的组装和封装过程中遭受机械和化学损坏的绝缘保护层。广泛使用的一种钝化层包括磷硅玻璃（PSG）层，该层对钠离子和其它快扩散金属杂质具有良好的吸收性能，和一层具有良好机械性能的PECVD氮化硅膜。在成形之后，将此钝化层腐蚀出窗口，以暴露出一组形成在钝化层之下的特殊的金属化图形。这些金属图形一般位于电路的周边，称之为焊接块。这些焊接块的典型尺寸为约100×100微米，相隔50-100微米。导线连接或焊接到焊接块的金属表面，然后接入芯片的管壳。用这种方法在芯片和管壳引线之间形成连接。
在常规的半导体装置中，形成金属图形以使金属导线为矩形，焊接块为正方形。图1A和1B示出常规焊接块的图形，这些焊接块经金属线及金属导线的图形与电路电连接。该常规的焊接块和金属导线之间有矩形拐角B1、B2和B3。如上所述，在半导体装置的焊接块和金属导线形成后，将一钝化层敷于其上。接着是热处理步骤。在这种情况下，很有可能在覆盖着焊接块和金属导线的钝化层中产生裂纹（见图1A中的A），因而降低了半导体装置的可靠性。根据本发明者的经验，钝化层中的裂纹与钝化层及该层之下的金属焊接块和/或金属导线之间的物理特性的差异密切相关。
为了防止上述钝化层中裂纹的产生，本发明者进行的研究得到本发明的结果。
本发明的目的是提供一种防止覆盖于半导体装置的焊接块和/或金属导线的钝化层在相继的热处理步骤中产生裂纹的焊接块或金属导线。
为了达到上述目的，本发明的半导体装置的特征在于：将半导体装置的焊接块和/或部分金属导线加工成圆形的或钝角形的拐角。
简单地说，根据本发明，提供了一种半导体装置，该装置包括一使半导体装置的金属导线与其封装引线电连接的焊接块和覆盖于焊接块和金属导线的钝化层，在金属导线和焊接块之间的接点C1和C2处形成一钝角形或圆形的拐角，从而抑制了后续的热处理步骤中在钝化层上产生裂纹。用作金属导线或焊接块的材料可以有铝、钼、钨、金、铜，以及它们的合金等。本发明中所用的钝化层可以是二氧化硅层，PSG层、掺杂有硼或磷原子的二氧化硅层、氮化硅层等。这些层可以单独使用，也可以组合成两层或更多层的组合层。比起使用单层结构作为钝化层，使用组合层能够减少裂纹产生的百分比。
通过形成具有圆形或钝角形的拐角C1、C2和C3的焊接块和/或金属导线，确实减少了形成于其上的钝化层中产生裂纹的百分比。其原因似乎是由于焊接块和/或金属导线与钝化层间的应力被分布开来了。同样，为了减少上述裂纹产生的可能性，将金属导线图形的突出部分也做成钝角或圆形，从而抑制形成于其上的层中的应力集中。
通过参照附图对最佳实施例的详细描述将使本发明的目的及其它优点更清楚明了。
图1A和1B分别为常规焊接块的图形和一常规金属导线的图形，此焊接块通过一金属导线与半导体电路电连接，以及一形成在钝化层中的裂纹。
图2A和2B分别示出本发明的焊接块图形和金属导线的图形，此焊接块通过一金属导线与半导体电路电连接。
图3A为示出一半导体晶片的顶视图的SEM图，该晶片具有通过金属导线与半导体电路电连接的现有技术的焊接块和本发明的焊接块。
图3B为图3A中的一个焊接块的图形（最下面一行从左数第5个），这是本发明的实施例。
图3C为图3A中的一个现有技术焊接块的图形（最下面一行从左数第8个）及在热处理之后形成于钝化层中的裂纹。
图2A和2B示出本发明实施例的焊接块的图形和一金属导线，焊接块经一金属导线与半导体电路电连接。本发明的焊接块和金属导线的图形具有钝角形的拐角C1、C2和C3。除了图示的钝角形拐角，具有圆形拐角的焊接块和金属导线也能抑制钝化层中裂纹的产生。形成具有钝角或圆形拐角的焊接块或金属导线来分散焊接块和/或金属导线与钝化层之间的应力，从而抑制了钝化层中裂纹的产生。
在半导体晶片上形成图1A（现有技术）和图2A（本发明实施例）所示的100×100微米的焊接块之后，再在半导体晶片的整个表面上形成一钝化层。该金属导线与焊接块电连接，其线宽为20微米。作为焊接块和金属导线的金属化层是沉积的Al-Si合金层。在试验中作为钝化层的分别有PSG层，其厚度为3000
、5000
和8000
，由氮化硅层（厚3000
）和PSG层（厚3000
、5000
、8000
）构成的组合层和另一由氮化硅层（厚6000
）和PSG层（厚5000
和8000
）构成的组合层。在各种情况下，PSG层均最接近金属层。在对这些没有开窗口的样品于450℃进行了4个30分钟的退火处理后，估测了焊接块上的钝化层的裂纹产生百分比。其结果示于表1。
由表1可以看出，钝化层中的裂纹产生百分比通过形成具有钝角形拐角的焊接块并形成金属导线以使其与焊接块之间的接点处形成钝角而得到显著降低。我们还能看到，使用PSG层和氮化硅层形成的组合层，其裂纹产生百分比小于只用PSG层的情况。
图3A为具有现有技术焊接块及本发明一实施例的焊接块两者的半导体晶片顶视图的SEM图，焊接块通过金属导线与半导体电路电连接。图3的结构是按下列步骤得到的。
在一半导体晶片上形成半导体装置之后，开出将有源区与金属化层电连接的接触孔，该金属化层在下一步工序中形成。然后，沉积金属化层，并使其形成图形以在整个半导体晶片的表面上形成金属导线和焊接块。此处，在同一芯片上形成图形是指形成常规的正方形焊接块和矩形金属导线以及根据本发明形成一钝角形拐角。接着一般是淀积铝或铝合金作为金属化层，但也可以用钼、钨、金、铜等或其合金构成。然后在这一形成物上通过沉积一层8000
厚的PSG层形成一钝化层。也能单独或组合地用二氧化硅层、掺硼和/或磷的二氧化硅层、氮化硅层等代替PGS层。在450℃下进行三次30分钟的退火处理，对其获得图3A的SEM图。
有选择地示出了上述结构的两个焊接块。图3B为本发明一实施例的焊接块的图形（底行左数第5个）。图3C示出现有技术焊接块的图形（底行左数第8个），其在热处理之后产生了裂纹。如图3A和3C中可见的，当金属导线和焊接块之间的接点形成直角形拐角时，在钝化层中形成了裂纹A。而当金属导线与焊接块的接合处具有钝角形拐角时，如图3A和3B所示，没出现裂纹。同时，图3B中的直角形拐角B1处也没有裂纹。这似乎是由于点B1左下方的表面面积小的缘故。
根据本发明精确计算的估计，上述实施例中现有技术情况下裂纹产生频率为94%，而本发明为22%。按具有裂纹的钝化层所覆盖的焊接块的数目除以所有焊接块的数目而得的数计算裂纹产生百分比。
根据本发明，半导体装置包括一焊接块和/或具有钝角形或图形拐角的金属导线。这一部分分散了焊接块和/或金属导线与覆盖于其上的钝化层之间的应力。因此，能简单地抑制覆盖于焊接块和/或金属导线之上的钝化层中的裂纹产生百分比，从而提高了半导体装置的可靠性。
已具体地示出本发明并参照其最佳实施例作了描述，本领域的普通技术人员能理解到可以在形式和细节上作出多种改变，但均不偏离本发明的精神和范围。
Claims (10)
1、半导体装置，包括：
一焊接块，用于将半导体装置的金属导线电连接到所述半导体装置的管壳引线；以及
一覆盖住所述焊接块和所述金属导线的钝化层；其特征在于：
所述金属导线在其与焊接块间的接点处形成一钝角或圆角拐角，以抑制在后续的热处理步骤中在所述钝化层中产生裂纹。
2、根据权利要求1的半导体装置，其特征在于：
所述金属导线或所述焊接块由选自铝、钼、钨、金、铜及其合金构成的一组材料中任一种构成的。
3、根据权利要求1的半导体装置，其特征在于：
所述钝化层是由二氧化硅层、PSG层、掺硼或磷原子的二氧化硅层以及氮化硅层构成的一组中选出的单一材料层或由两层或更多层构成的组合层。
4、半导体装置，其特征在于：由在与内部金属导线的接点处具有圆形或钝角形拐角的焊接块构成。
5、根据权利要求4的半导体装置，其特征在于：
进一步包括在所述金属导线和所述焊接块的接合处具有一钝角或圆角形拐角的金属导线。
6、半导体装置，其特征在于：包括一具有圆形或钝角形拐角的金属导线。
7、根据权利要求6的半导体装置，其特征在于：
进一步包括将所述金属导线连接至所述半导体装置的管壳引线的焊接块。
8、根据权利要求7的半导体装置，其特征在于：
所述金属导线在其与所述焊接块的接合处形成有钝角或圆形拐角。
9、半导体装置，其特征在于：包括一按钝角或圆形凸出形状成形的金属层。
10、半导体装置，其特征在于：包括一具有钝角或圆形拐角的金属层;以及
形成于其上且由PSG层和氮化硅层构成的组合层。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR910019752 | 1991-11-07 | ||
| KR19752/91 | 1991-11-07 |
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| Publication Number | Publication Date |
|---|---|
| CN1074557A true CN1074557A (zh) | 1993-07-21 |
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ID=19322415
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN92112747A Pending CN1074557A (zh) | 1991-11-07 | 1992-11-06 | 半导体装置 |
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| Country | Link |
|---|---|
| EP (1) | EP0541405A1 (zh) |
| JP (1) | JPH05218021A (zh) |
| CN (1) | CN1074557A (zh) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979317A (zh) * | 2014-04-14 | 2015-10-14 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
| CN109791923A (zh) * | 2016-08-16 | 2019-05-21 | 英特尔公司 | 用于减小应力的圆化的金属迹线拐角 |
| CN112234028A (zh) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | 降低钝化层应力的方法及钝化层应力缓冲结构 |
| CN115084087A (zh) * | 2021-03-10 | 2022-09-20 | 中芯国际集成电路制造(上海)有限公司 | 晶圆焊垫结构及其形成方法 |
| CN115084087B (zh) * | 2021-03-10 | 2025-02-18 | 中芯国际集成电路制造(上海)有限公司 | 晶圆焊垫结构及其形成方法 |
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| US6503820B1 (en) * | 1999-10-04 | 2003-01-07 | Koninklijke Philips Electronics N.V. | Die pad crack absorption system and method for integrated circuit chip fabrication |
| JP4979154B2 (ja) * | 2000-06-07 | 2012-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP5110897B2 (ja) * | 2007-02-07 | 2012-12-26 | ローム株式会社 | 半導体装置 |
| JP5460141B2 (ja) | 2009-06-26 | 2014-04-02 | ラピスセミコンダクタ株式会社 | 半導体装置 |
| JP6040456B2 (ja) * | 2010-01-15 | 2016-12-07 | ローム株式会社 | 半導体装置およびその製造方法 |
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| CN211788920U (zh) * | 2017-07-24 | 2020-10-27 | 株式会社村田制作所 | 半导体装置 |
| JP6473790B2 (ja) * | 2017-09-21 | 2019-02-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6677832B2 (ja) * | 2019-01-28 | 2020-04-08 | ルネサスエレクトロニクス株式会社 | 半導体チップ |
| JP7165694B2 (ja) * | 2020-03-13 | 2022-11-04 | ルネサスエレクトロニクス株式会社 | 半導体チップ |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60217652A (ja) * | 1984-04-13 | 1985-10-31 | Hitachi Ltd | 半導体装置 |
| JPS60242643A (ja) * | 1985-03-22 | 1985-12-02 | Hitachi Ltd | 電子部品の配線 |
| JPS6384122A (ja) * | 1986-09-29 | 1988-04-14 | Matsushita Electronics Corp | 半導体装置 |
| JPH0379059A (ja) * | 1989-08-22 | 1991-04-04 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
-
1992
- 1992-11-06 CN CN92112747A patent/CN1074557A/zh active Pending
- 1992-11-06 JP JP4322354A patent/JPH05218021A/ja active Pending
- 1992-11-09 EP EP92310245A patent/EP0541405A1/en not_active Withdrawn
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979317A (zh) * | 2014-04-14 | 2015-10-14 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
| US10283458B2 (en) | 2014-04-14 | 2019-05-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US10923437B2 (en) | 2014-04-14 | 2021-02-16 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US11482498B2 (en) | 2014-04-14 | 2022-10-25 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US11810869B2 (en) | 2014-04-14 | 2023-11-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN109791923A (zh) * | 2016-08-16 | 2019-05-21 | 英特尔公司 | 用于减小应力的圆化的金属迹线拐角 |
| US11784150B2 (en) | 2016-08-16 | 2023-10-10 | Intel Corporation | Rounded metal trace corner for stress reduction |
| CN112234028A (zh) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | 降低钝化层应力的方法及钝化层应力缓冲结构 |
| CN115084087A (zh) * | 2021-03-10 | 2022-09-20 | 中芯国际集成电路制造(上海)有限公司 | 晶圆焊垫结构及其形成方法 |
| CN115084087B (zh) * | 2021-03-10 | 2025-02-18 | 中芯国际集成电路制造(上海)有限公司 | 晶圆焊垫结构及其形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218021A (ja) | 1993-08-27 |
| EP0541405A1 (en) | 1993-05-12 |
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