CN1957455A - 在铜金属化集成电路之上具有保护性防护层可焊金属接头的接触点的结构和方法 - Google Patents
在铜金属化集成电路之上具有保护性防护层可焊金属接头的接触点的结构和方法 Download PDFInfo
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- CN1957455A CN1957455A CNA2005800165361A CN200580016536A CN1957455A CN 1957455 A CN1957455 A CN 1957455A CN A2005800165361 A CNA2005800165361 A CN A2005800165361A CN 200580016536 A CN200580016536 A CN 200580016536A CN 1957455 A CN1957455 A CN 1957455A
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Abstract
一种用于集成电路(IC)接触点的金属结构,所述集成电路具有铜互连涂敷金属(311)。该涂敷金属的一部分(301)被暴露以向IC提供接触点。导电阻挡层(330)被置于铜涂敷金属的暴露部分上。厚度优选为约0.4至1.4微米之间的可焊金属接头(350)被置于到阻挡层上。保护性的防护层(320)包围着接头,而且其厚度(320b)使得接头的暴露表面(322)位于防护层的暴露表面(320a)处或之下。可选地,所述防护层的宽度为约0.1至0.3微米之间的一部分(321)可重叠在接头的周界上。
Description
技术领域
【0001】本发明一般涉及电子系统和半导体器件领域,更具体地是涉及铜金属化集成电路的焊盘结构和制造方法。
背景技术
【0002】在集成电路(IC)技术中,将纯铝或掺杂铝作为涂敷金属的选择用于互连和焊盘已经超过四十年。铝的主要优点是易于沉积和图案化。而且,由金、铜或铝制成的连接到铝焊盘的焊丝的技术已经发展到一种高水平的自动化、微型化和可靠度。
【0003】在IC持续的微型化趋势中,活动或有源电路元件之间的互连的RC时间常数日益决定着可获得的IC速度功率产品。因此现在,互连铝的相对高的电阻率与诸如铜之类的金属的较低电阻率相比要逊色。而且,铝对电迁移的显著的敏感性也正成为严重的障碍。所以,基于铜具有较高的导电率和较低的电迁移敏感性,因而现在强烈地促使在半导体工业中利用铜作为优选的互连金属。然而,由于铝互连技术已经很成熟,因而转用铜是一个相当大的技术挑战。
【0004】铜必须被屏蔽才不会扩散到IC的硅基材料中,这样才能保护电路,不会在载体的有效期破坏处于硅晶格中的铜原子的特性。对于由铜制成的焊盘,在制造工艺流程中必须防止形成氧化铜(I)薄膜,因为这些膜严重地抑制了焊丝的可靠接合,尤其对于传统的金丝球焊。与覆盖在金属铝上的氧化铝膜相比,覆盖在金属铜上的氧化铜膜不易被焊接工艺中施加的热压和超声能联合破坏。而另一难题在于,裸露的铜焊盘易被腐蚀。
【0005】为了克服这些问题,半导体工业采取这样一种结构,即,用一个铝层盖在干净的铜焊盘的顶上,这样就重新构成了通过传统的金丝球焊来接合铝焊盘的传统情形。然而,上述方法存在若干缺点。首先,铝帽的造价高于所期望的,因为这个工艺要求额外的步骤来沉积金属、图案化、蚀刻和清理。第二,所述帽的厚度必须足以允许进行可靠的丝焊(或称引线接合),并足以防止铜扩散穿过帽金属从而可能对IC晶体管造成不良影响。
【0006】第三,用于所述帽的铝是软的,因此会在电测试中被多探针触点的标记严重破坏。而这种破坏在尺寸不断减小的焊盘中会变成重要因素,以致随后的球焊接合不再可靠。最后,由于该铝层高于周围的防护层平面,从而增加了金属划伤和涂抹的危险。在很多高输入/输出电路的紧密的焊盘间距处,任何铝涂抹代表着不能接受的相邻焊点间短路的风险。
发明内容
【0007】因此,需要一种冶金焊盘结构,其适用于具有铜互连涂敷金属的IC,其结合了一种制造所述焊盘结构的低成本方法、对再扩散的完美控制、涂抹或划伤风险的消除、以及一种丝焊到这些焊盘的可靠方法。所述焊盘结构应该足够灵活,以应用于不同的IC产品族和广泛的设计和工艺变型中。优选地,在实现这些创新点的同时还可缩短生产周期、增加产量,而且不需要昂贵的额外制造设备。
【0008】本发明的一个实施例是一种用于集成电路(IC)的接触点的金属结构,所述集成电路具有铜互连涂敷金属。该涂敷金属的一部分被暴露以向IC提供接触点。导电阻挡层位于所述铜涂敷金属的暴露部分上。可焊金属接头,优选为约0.4至1.4微米厚的铝,被置于所述阻挡层上。保护性的防护层包围着所述接头,并且该防护层所具有的厚度使得所述接头的暴露表面位于所述防护层的暴露表面处或之下。可选地,所述防护层的一个约0.1至0.3微米宽的部分可重叠所述接头的周界上。
【0009】本发明的另一个实施例是一种制造用于集成电路接触点的金属结构的晶片级方法,所述集成电路具有铜互连涂敷金属。所述方法包括以化学机械方式抛光所述晶片,以暴露出所述铜涂敷金属的嵌入绝缘材料中的图案化接触点区域的步骤。然后,将阻挡金属层沉积到包括暴露的铜涂敷金属的晶片上。接着,将可焊金属层(优选为铝)沉积到阻挡层上,其厚度足以进行丝球焊。接着,将沉积的两个金属层进行图案化,以去除接触点区域外的层部分,但保留接触点区域上的层部分,从而在每个接触点上形成一个可焊金属接头。然后,在晶片上沉积一个保护性的防护层,包括所述图案化层部分的金属接头。所述防护层具有的厚度可使防护层的暴露表面位于可焊金属层的暴露表面处或之上。最后,在所述防护层上开出窗口,以暴露所述可焊金属接头。
【0010】本发明的实施例涉及丝焊IC组件、半导体器件封装、表面安装和芯片级的封装。本发明的一个技术优点在于提供了一种减少铝涂抹或划伤以及接触点间电短路风险的低成本方法。因此,可以显著提高高输入/输入器件的组装成品率。本发明的一个额外的技术优点在于,有利于在无电短路造成的产量损失的风险的情况下,缩小芯片接触点的间距。进一步的技术优点包括有机会将组件缩放到更小的尺寸,满足现在IC微型化的趋势。
【0011】当结合附图以及所附权利要求中给出的新颖性特征考虑时,根据下文对本发明优选实施例的描述,本发明的某些实施例所代表的技术优点将会变得更加明显。
附图说明
【0012】图1示出了根据已知技术的具有铜涂敷金属的集成电路(IC)的接触点的示意性截面图。可焊金属作为额外的层添加到晶片表面上且被抬高成高于晶片表面。
【0013】图2示出了在已知技术中铜金属化IC的两个丝焊接触点的示意性截面图。抬高的可焊金属层已被划伤和涂抹,引起了电短路。
【0014】图3是本发明的一个实施例的示意性截面图,示出了具有铜涂敷金属的IC的接触点,其中该接触点具有一个可焊金属接头。
【0015】图4是根据本发明的焊盘涂敷金属的示意性截面图,其中具有接合到可焊金属接头的焊球。
【0016】图5是根据本发明另一个实施例的器件制造工艺流程的方框图。
具体实施方式
【0017】通过比较本发明的一个实施例和传统的对集成电路(IC)芯片的接触点进行丝焊的方法(其使用铜作为互连金属),能够最好地理解本发明带来的技术优点。图1中示出了传统结构的一个实例。在总体上被标识为100的IC接触点的示意性截面图中,101是层间(intra-level)电介质,可由二氧化硅、低k电介质、或任何其它合适的传统上用于IC的绝缘体组成。102表示顶层IC铜涂敷金属(厚度通常为200至500纳米之间),其被阻挡层(通常为氮化钽,且厚度通常为10至30纳米之间)103a和103b包围,以防止其扩散到其它IC材料中。接触窗110处于实质上不渗水的防护层104中(防护层104通常为500至1000纳米之间的氮化硅、氮氧化硅、或二氧化硅,并且可以是单层或多层的),接触窗的宽度通常为40至70微米之间,其暴露出铜涂敷金属102,以便建立接触。阻挡层103b在窗口周界的周围重叠在防护层104上,以产生涂敷金属宽度111,因而该宽度大于窗口110(直径通常为约45至75微米之间)。同样的宽度111容纳可焊金属层120,该金属层为铝或铜铝合金。为了使丝焊可靠,层120的厚度121通常在700至1000纳米之间。
【0018】图案化铝层120相当高的高度121存在偶然划伤或涂抹铝的很大风险。在铝图案化之后的典型的组装工艺流程中,有许多晶片和芯片处理步骤。最重要的步骤包括背磨;将晶片从加工设备传送到组装设备;将晶片置于条带(tape)上以便锯割;锯割和清洗晶片;将每个芯片固定到引线框;进行丝焊(或称引线接合);以及将焊好的芯片包封到模塑料中。在这些工艺步骤的每一个工艺步骤中,以及在工艺步骤之间,可能会发生偶然的划伤或涂抹。
【0019】图2示意性地示出了一个实例,其是穿过两个邻近(距离230)的焊盘201和202的截面图。焊盘201的铝层210和焊盘202的铝层220已经被划伤,以致铝在240处被涂抹在一起。因此,焊盘250和251形成电短路。
【0020】图3示出了本发明的一个实施例,其图解说明了半导体晶片的一部分300的示意性截面图。层间绝缘材料310例如由低k介电材料、二氧化硅、或介电材料的叠层制成。图3进一步示出了IC互连涂敷金属的图案化顶层部分,该涂敷金属由铜或铜合金制成,嵌在绝缘体310中。特别示出了铜层中用于提供接触点的部分311以及用于锚定划线道的部分312。铜层的厚度范围优选为0.2至0.5微米。铜涂敷金属分别包含在阻挡层313a和113b中,以防止其扩散到绝缘体310或其它的集成电路材料中;阻挡层313a和313b优选由氮化钽制成,厚度为约10至30纳米。焊盘铜层311具有宽度301(通常处于30至60微米的范围内)。
【0021】如图3所示,铜层311的暴露表面(顶表面)311a和划线道涂敷金属的暴露表面(顶表面)312a与介电材料310的顶表面310a处于同一高度。之所以要一致的原因在于制造方法中包括了一个化学机械抛光步骤(参考下述内容)。
【0022】为了与铜建立低电阻的欧姆接触,一个或多个导电阻挡层330被沉积到铜上,如图3所示。对于单个层而言,氮化钽是较佳的选择。对于两个层而言,第一阻挡层最好选自钛、钽、钨、钼、铬以及它们的合金;该层被沉积在暴露的铜部分311上,以通过“吸除(gettering)”铜上的氧化物与铜建立良好的欧姆接触。第二阻挡层(通常为镍钒),被沉积以防止铜向外扩散。该阻挡层的厚度优选在0.02至0.03微米的范围内。在图3中,所示阻挡层330与铜涂敷金属311具有相同的宽度301。虽然这是优选结构,但仍可存在其他的器件设计方案,其中阻挡层宽度可以稍微略小或略大。
【0023】阻挡层330的顶上是一个可焊金属层350,其厚度适于进行丝球焊。厚度范围优选为从约0.4至1.4微米。由于这一厚度较大,因而层350通常被称为接头(plug)。可焊金属优选为铝或铝合金,例如铝铜合金。在图3中,这一接头的暴露表面被标识为350a。同样厚度的铝层351在图3中被示为在划线道金属312之上。
【0024】如上所述,由于表面310a和311a处于一个共同高度上,阻挡层330和可焊接头350的总厚度在几何上将堆叠高出这个共同高度;在图3中,在共同高度之上的这个总高度被标识为360。为了防止任何偶然的划伤或涂抹,应沉积一个保护性的防护层320(更详细的内容参见下文)。优选的防护层材料实际上是不渗水或锁水的,并且从机械意义而言是硬的;实例包括一层或多层氮化硅、氮氧化硅、碳化硅、或包括聚酰亚胺的绝缘材料的叠层。该防护层的厚度320b处于0.5至1.5微米范围内,优选为1.0微米。图3中,防护层320的暴露表面被标识为320a。
【0025】根据本发明,沉积的保护性防护层320具有厚度320b并包围着接头350,以致接头350的暴露表面350a位于防护层320的暴露表面320a处或之下。宽度322的窗口开在防护层320中,以便暴露出接头350的表面350a。优选地,宽度322比接头350的宽度301窄;因此,防护层320的一部分(在图3中标识为321)可以重叠在接头350的周界上。类似的描述也适用于相对于铝层351的防护层320。接头表面350a和层表面351a相对于防护层320a并未被抬高;因此,可分别保护接头350和层351,使其不会发生偶然划伤,从而提供了原状接头金属以便可靠地进行球焊。
【0026】图4的截面图示意性地示出了在芯片通过锯割工艺(410指示的划线道)从晶片中分离出来并接合了一个焊球之后的图3中的接触点。金属焊丝402(优选为金)的自由气球401(优选为金)被压焊到接头403(优选为铝或铝合金)的原状表面403a。在焊接过程中,金属间化合物404形成在球和接头的接触区域。
【0027】本发明的另一个实施例是一种制造用于集成电路接触点的金属结构的晶片级方法,所述集成电路具有铜互连涂敷金属。图5的示意性方框图中示出了该工艺流程。该方法从步骤501开始,在步骤502以化学机械方式抛光晶片,以暴露出嵌入在绝缘材料中的铜涂敷金属的图案化接触点区域。
【0028】在下一个步骤503中,阻挡金属层被沉积在晶片上(包括暴露的铜涂敷金属)。优选的阻挡金属选择包括钽或氮化钽和镍钒;优选的阻挡层厚度在大约20和30纳米之间。在步骤504中,将可焊金属层沉积在阻挡层上,其厚度足以进行丝球焊。优选的可焊金属选择包括铝和铝合金,优选的可焊金属层厚度在0.4到1.4微米之间。
【0029】在下一个步骤505中,沉积的两个金属层都被图案化,以便去除接触点区域外的层部分,但保留接触点区域上的层部分,从而在每个接触点上形成可焊金属接头。
【0030】在下一个步骤506中,将保护性的防护层沉积在晶片上,包括步骤505中形成的图案化层部分的金属接头。防护层优选包括一层或多层氮化硅、氮氧化硅、二氧化硅、碳化硅、或其它锁水化合物。防护层具有的厚度使得防护层的暴露表面位于可焊金属层的暴露表面处或之上。优选的防护层厚度为约0.6至1.5微米。
【0031】在步骤507中,窗口被开在防护层中,以暴露可焊金属接头。可将窗口的尺寸设计成,使宽度在约0.1和0.3微米之间的防护框留在焊盘区域的周界的周围,从而为接头提供额外的保护避免偶然划伤。该方法结束于步骤508。
【0032】虽然本发明是参考说明性实施例描述的,但不应将这种描述理解为限制性的。对于查阅了本说明书的本领域技术人员而言,这些说明性实施例的各种变型和组合以及本发明的其它实施例将是明显的。因此所附权利要求应涵盖任何这样的变型和实施例。
Claims (19)
1.一种具有铜互连涂敷金属的集成电路,所述涂敷金属的一部分被暴露以向所述集成电路提供接触点,所述集成电路包括:
一个或多个导电阻挡金属层,其置于所述铜涂敷金属的所述暴露部分上;
一个可焊金属层,其置于所述阻挡层上,且所述阻挡层具有适于丝焊的厚度以及一个暴露表面;和
一个保护性的防护层,其包围着所述接合层,以使所述接合层的暴露表面位于所述防护层的暴露表面处或之下。
2.一种用于具有铜互连涂敷金属的集成电路的金属结构,所述涂敷金属的一部分被暴露以向所述集成电路提供接触点,所述金属结构包括:
一个导电阻挡层,其置于所述铜涂敷金属的暴露部分上;
一个可焊金属接头,其置于所述阻挡层上;和
一个保护性的防护层,其包围着所述接头,以使所述接头的暴露表面位于所述防护层的暴露表面处或之下。
3.根据权利要求2所述的金属结构,其中所述防护层的厚度范围为约0.6至1.5微米。
4.根据权利要求2所述的金属结构,其中所述防护层在所述接头的周界上有约0.1至0.3微米之间的重叠。
5.根据权利要求2所述的金属结构,其中所述防护层包括一层或多层氮化硅、氮氧化硅、二氧化硅、碳化硅、或其它锁水化合物。
6.根据权利要求2所述的金属结构,其中所述可焊金属接头为铝或铝合金。
7.根据权利要求2所述的金属结构,其中所述接头的厚度在约0.4至1.4微米之间。
8.根据权利要求2所述的金属结构,进一步包括接合于所述接头的焊球。
9.根据权利要求2所述的金属结构,其中所述阻挡层包括氮化钽。
10.根据权利要求2所述的金属结构,其中所述阻挡层选自钛、钽、钨、钼、铬、钒以及它们的合金、叠层和化合物。
11.根据权利要求2所述的金属结构,其中所述阻挡层的厚度在约0.02至0.03微米之间。
12.根据权利要求2所述的金属结构,其中所述阻挡层被图案化到与所述涂敷金属的所述接触点部分相同的区域。
13.根据权利要求2所述的金属结构,其中所述可焊金属接头被图案化到与所述涂敷金属的所述接触点部分相同的区域。
14.根据权利要求2所述的金属结构,其中所述防护层的一部分重叠在所述接头的周界上。
15.一种制造金属结构的晶片级方法,所述金属结构用于具有铜互连涂敷金属的集成电路的接触点,所述方法包括以下步骤:
以化学机械方式抛光所述晶片,以暴露出嵌入绝缘材料中的所述铜涂敷金属的图案化接触点区域;
在包括所述暴露的铜涂敷金属的所述晶片上沉积一个阻挡金属层;
在所述阻挡层上沉积一个可焊金属层,其厚度足以进行丝球焊;
将沉积的两个所述金属层图案化,以去除所述接触点区域外的层部分,但保留所述接触点区域上的层部分,从而在每个所述接触点上形成一个可焊金属接头;
在包括所述图案化层部分的所述金属接头的所述晶片上沉积一个保护性的防护层,所述防护层具有的厚度使得所述防护层的暴露表面位于所述可焊金属层的暴露表面处或之上;
在所述防护层中开出窗口以暴露所述可焊金属接头。
16.根据权利要求15所述的方法,其中所述沉积可焊金属层的步骤包括厚度范围为约0.4至1.4微米的铝。
17.根据权利要求15所述的方法,其中所述防护层的厚度范围为约0.6至1.5微米。
18.根据权利要求15所述的方法,其中所述防护框的宽度为约0.1至0.3微米之间。
19.根据权利要求15所述的方法,其中所述防护层中的所述开口在每个接头的周界的周围留下一个防护框。
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US10/806,519 | 2004-03-23 | ||
US10/806,519 US20050215048A1 (en) | 2004-03-23 | 2004-03-23 | Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits |
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US20050206007A1 (en) * | 2004-03-18 | 2005-09-22 | Lei Li | Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits |
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US8043893B2 (en) | 2007-09-14 | 2011-10-25 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
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US9515034B2 (en) | 2014-01-03 | 2016-12-06 | Freescale Semiconductor, Inc. | Bond pad having a trench and method for forming |
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CN101419924B (zh) * | 2007-10-25 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
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US20050215048A1 (en) | 2005-09-29 |
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