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ATE350765T1 - Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung

Info

Publication number
ATE350765T1
ATE350765T1 AT02077552T AT02077552T ATE350765T1 AT E350765 T1 ATE350765 T1 AT E350765T1 AT 02077552 T AT02077552 T AT 02077552T AT 02077552 T AT02077552 T AT 02077552T AT E350765 T1 ATE350765 T1 AT E350765T1
Authority
AT
Austria
Prior art keywords
semiconductor device
producing
semiconductor
package leads
semiconductor material
Prior art date
Application number
AT02077552T
Other languages
English (en)
Inventor
Ronald Dekker
Henricus Godefridus Rafae Maas
Martinus Pieter Joh Versleijen
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE350765T1 publication Critical patent/ATE350765T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT02077552T 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung ATE350765T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94202182 1994-07-26

Publications (1)

Publication Number Publication Date
ATE350765T1 true ATE350765T1 (de) 2007-01-15

Family

ID=8217069

Family Applications (2)

Application Number Title Priority Date Filing Date
AT02077552T ATE350765T1 (de) 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung
AT95921959T ATE225985T1 (de) 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT95921959T ATE225985T1 (de) 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

Country Status (7)

Country Link
US (1) US5753537A (de)
EP (2) EP0721661B1 (de)
KR (1) KR100380701B1 (de)
AT (2) ATE350765T1 (de)
DE (2) DE69528515T2 (de)
TW (1) TW345728B (de)
WO (1) WO1996003772A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69615792T2 (de) * 1995-05-10 2002-05-23 Koninklijke Philips Electronics N.V., Eindhoven Miniatur-halbleiteranordnung für oberflächenmontage
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
KR100390897B1 (ko) * 1997-12-29 2003-08-19 주식회사 하이닉스반도체 칩 크기 패키지의 제조방법
DE19818036B4 (de) * 1998-04-22 2005-05-19 Siemens Ag Verfahren zur Herstellung eines elektrotechnischen Bauteils mit einer kunststoffpassivierten Oberfläche, derartiges Bauteil und Anwendung dieses Bauteils
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EP1251557A3 (de) 2003-04-09
EP1251557B1 (de) 2007-01-03
DE69535361D1 (de) 2007-02-15
ATE225985T1 (de) 2002-10-15
KR960705353A (ko) 1996-10-09
US5753537A (en) 1998-05-19
DE69528515D1 (de) 2002-11-14
WO1996003772A2 (en) 1996-02-08
EP0721661B1 (de) 2002-10-09
TW345728B (en) 1998-11-21
DE69528515T2 (de) 2003-04-24
EP1251557A2 (de) 2002-10-23
KR100380701B1 (ko) 2003-07-22
WO1996003772A3 (en) 1996-04-18
DE69535361T2 (de) 2007-10-04
EP0721661A1 (de) 1996-07-17

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