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Cited By

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Wagle AVrudhula S(2022)Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and PerformanceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309978041:6(1855-1867)Online publication date: Jun-2022
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
Pan PLin CCong JKaptanoglu S(1998)A new retiming-based technology mapping algorithm for LUT-based FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275118(35-42)Online publication date: 1-Mar-1998
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FPGA '96: Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

February 1996

158 pages

ISBN:0897917731

DOI:10.1145/228370

Chairmen:
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada
,
Carl Ebeling
Univ. of Washington, Seattle

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Published: 15 February 1996

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FPGA96: 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 11 - 13, 1996

California, Monterey, USA

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Wagle AVrudhula S(2022)Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and PerformanceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309978041:6(1855-1867)Online publication date: Jun-2022
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
Pan PLin CCong JKaptanoglu S(1998)A new retiming-based technology mapping algorithm for LUT-based FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275118(35-42)Online publication date: 1-Mar-1998
Cong JWu CYoffa EDe Micheli GRabaey J(1997)FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuitsProceedings of the 34th annual Design Automation Conference10.1145/266021.266309(644-649)Online publication date: 13-Jun-1997
Pan PLiu CPennino TYoffa E(1996)Optimal clock period FPGA technology mapping for sequential circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240655(720-725)Online publication date: 1-Jun-1996

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