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Chortle-crf: Fast technology mapping for lookup table-based FPGAs

Authors:

Robert Francis,

Jonathan Rose,

Zvonko VranesicAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 227 - 233

https://doi.org/10.1145/127601.127670

Published: 01 June 1991 Publication History

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Cited By

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Fan LWu CIenne PZhang Z(2023)FPGA Technology Mapping with Adaptive Gate DecompositionProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573048(135-140)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573048
Amaru LPossani VTesta EMarranghello FCasares CLuo JVuillod PMishchenko ADe Micheli G(2021)LUT-Based Optimization For ASIC Design Flow2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586132(871-876)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586132
Hosseinzadeh HBeitollahi HMozayani N(2018)A Flexible and Efficient Reconfigurable Architecture based on Multi-Agent Systems2018 9th International Symposium on Telecommunications (IST)10.1109/ISTEL.2018.8661058(429-434)Online publication date: Dec-2018
https://doi.org/10.1109/ISTEL.2018.8661058
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A new algorithm for technology mapping of lookup table-based Field-Programmable Gate Arrays (FPGA's) is presented. It has the capability of producing compact designs (minimizing the number of cells (CLB's)), as well as the flexibility of trading ...

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Fan LWu CIenne PZhang Z(2023)FPGA Technology Mapping with Adaptive Gate DecompositionProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3543622.3573048(135-140)Online publication date: 12-Feb-2023
https://dl.acm.org/doi/10.1145/3543622.3573048
Amaru LPossani VTesta EMarranghello FCasares CLuo JVuillod PMishchenko ADe Micheli G(2021)LUT-Based Optimization For ASIC Design Flow2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586132(871-876)Online publication date: 5-Dec-2021
https://doi.org/10.1109/DAC18074.2021.9586132
Hosseinzadeh HBeitollahi HMozayani N(2018)A Flexible and Efficient Reconfigurable Architecture based on Multi-Agent Systems2018 9th International Symposium on Telecommunications (IST)10.1109/ISTEL.2018.8661058(429-434)Online publication date: Dec-2018
https://doi.org/10.1109/ISTEL.2018.8661058
Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Keutzer KRavindran K(2016)Technology MappingEncyclopedia of Algorithms10.1007/978-1-4939-2864-4_420(2200-2204)Online publication date: 22-Apr-2016
https://doi.org/10.1007/978-1-4939-2864-4_420
Khurshid BNaaz R(2015)Improving synthesis of fixed-point adders on FPGAs using primitive instantiations2015 Annual IEEE India Conference (INDICON)10.1109/INDICON.2015.7443470(1-5)Online publication date: Dec-2015
https://doi.org/10.1109/INDICON.2015.7443470
Khurshid BNazir LMir R(2015)Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs2015 2nd International Conference on Electronics and Communication Systems (ICECS)10.1109/ECS.2015.7124915(316-321)Online publication date: Feb-2015
https://doi.org/10.1109/ECS.2015.7124915
Sanchez ESterpone LUllah A(2014)Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927478(1-6)Online publication date: Sep-2014
https://doi.org/10.1109/FPL.2014.6927478
Keutzer KRavindran K(2014)Technology MappingEncyclopedia of Algorithms10.1007/978-3-642-27848-8_420-2(1-7)Online publication date: 20-Dec-2014
https://doi.org/10.1007/978-3-642-27848-8_420-2
Todman TFu HTsoi BMencer OLuk W(2009)Smart Enumeration: A Systematic Approach to Exhaustive SearchIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-95948-9_43(429-438)Online publication date: 2009
https://doi.org/10.1007/978-3-540-95948-9_43
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Recommendations

Improvements to technology mapping for LUT-based FPGAs

ROUTABILITY-DRIVEN TECHNOLOGY MAPPING FOR LookUp TABLE-BASED FPGAs

Routability-driven technology mapping for lookup table-based FPGA's