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Sequential synthesis for table look up programmable gate arrays

Authors:

Rajeev Murgai,

Robert K. Brayton,

Albert Sangiovanni-VincentelliAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 224 - 229

https://doi.org/10.1145/157485.164681

Published: 01 July 1993 Publication History

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R. Murgai, R. K. Brayton and A. Sangiovanni-Vincentelli,"Sequential Synthesis for Table Look Up Programmable Gate Arrays", Internal Report, Univ. of California, Berkeley.

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Cited By

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Cong JWu C(2006)An efficient algorithm for performance-optimal FPGA technology mapping with retimingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72031217:9(738-748)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.720312
Naseer ABalakrishnan MKumar A(2006)Direct mapping of RTL structures onto LUT-based FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70940117:7(624-631)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.709401
Feske KMulka SKoegst MElst G(2005)Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAsField-Programmable Logic and Applications10.1007/3-540-63465-7_228(235-244)Online publication date: 29-Jul-2005
https://doi.org/10.1007/3-540-63465-7_228
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Sequential synthesis for table look up programmable gate arrays

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Cong JWu C(2006)An efficient algorithm for performance-optimal FPGA technology mapping with retimingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72031217:9(738-748)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.720312
Naseer ABalakrishnan MKumar A(2006)Direct mapping of RTL structures onto LUT-based FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70940117:7(624-631)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.709401
Feske KMulka SKoegst MElst G(2005)Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAsField-Programmable Logic and Applications10.1007/3-540-63465-7_228(235-244)Online publication date: 29-Jul-2005
https://doi.org/10.1007/3-540-63465-7_228
Pan PLin CCong JKaptanoglu S(1998)A new retiming-based technology mapping algorithm for LUT-based FPGAsProceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays10.1145/275107.275118(35-42)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1145/275107.275118
Feske KRulke SKoegst M(1998)FPGA based prototyping using a target driven FSM partitioning strategy1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196)10.1109/ICECS.1998.813277(89-92)Online publication date: 1998
https://doi.org/10.1109/ICECS.1998.813277
Lemberski I(1998)Modified approach to automata state encoding for LUT FPGA implementationProceedings. 24th EUROMICRO Conference (Cat. No.98EX204)10.1109/EURMIC.1998.711798(196-199)Online publication date: 1998
https://doi.org/10.1109/EURMIC.1998.711798
Pan PLiu CPennino TYoffa E(1996)Optimal clock period FPGA technology mapping for sequential circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240655(720-725)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240655
Cong JDing Y(1996)Combinational logic synthesis for LUT based field programmable gate arraysACM Transactions on Design Automation of Electronic Systems10.1145/233539.2335401:2(145-204)Online publication date: 1-Apr-1996
https://dl.acm.org/doi/10.1145/233539.233540
Pan PLiu CRose JEbeling C(1996)Technology mapping of sequential circuits for LUT-based FPGAs for performanceProceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays10.1145/228370.228379(58-64)Online publication date: 15-Feb-1996
https://dl.acm.org/doi/10.1145/228370.228379
Chrzanowska-Jeske MGao TCoppola A(1996)Global-cell selection in a partitioning-based fitter for an application-specific EPLD device38th Midwest Symposium on Circuits and Systems. Proceedings10.1109/MWSCAS.1995.510203(773-776)Online publication date: 1996
https://doi.org/10.1109/MWSCAS.1995.510203
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