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Xmap: A technology mapper for table-lookup field-programmable gate arrays

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Kevin KarplusAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 240 - 243

https://doi.org/10.1145/127601.127672

Published: 01 June 1991 Publication History

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Cited By

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Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Cheang SLee KLeung K(2007)Applying Genetic Parallel Programming to Synthesize Combinational Logic CircuitsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2006.88404411:4(503-520)Online publication date: 1-Aug-2007
https://dl.acm.org/doi/10.1109/TEVC.2006.884044
Cong JMinkovich K(2007)Optimality Study of Logic Synthesis for LUT-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88792226:2(230-239)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.887922
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Index Terms

Xmap: A technology mapper for table-lookup field-programmable gate arrays
1. Hardware
2. Theory of computation
  1. Design and analysis of algorithms

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Cheang SLee KLeung K(2007)Applying Genetic Parallel Programming to Synthesize Combinational Logic CircuitsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2006.88404411:4(503-520)Online publication date: 1-Aug-2007
https://dl.acm.org/doi/10.1109/TEVC.2006.884044
Cong JMinkovich K(2007)Optimality Study of Logic Synthesis for LUT-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88792226:2(230-239)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.887922
Cong JMinkovich KWilton SDeHon A(2006)Optimality study of logic synthesis for LUT-based FPGAsProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117207(33-40)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117207
Hoare RKourtev IJones A(2006)Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2006.68(299-300)Online publication date: 24-Apr-2006
https://dl.acm.org/doi/10.1109/FCCM.2006.68
Wen-Zen Shen (2006)Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping32nd Design Automation Conference10.1109/DAC.1995.250065(65-69)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250065
Beetem J(2006)RebelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70393817:5(444-451)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703938
Lai YPan KPedram M(2006)OBDD-based function decompositionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.51157715:8(977-990)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.511577
Chen CTsay YHwang TWu ALin Y(2006)Combining technology mapping and placement for delay-minimization in FPGA designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40670914:9(1076-1084)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.406709
Hwang TOwens RIrwin MWang K(2006)Logic synthesis for field-programmable gate arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.31747113:10(1280-1287)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.317471
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