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A heuristic method for FPGA technology mapping based on the edge visibility

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Nam-Sung WooAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 248 - 251

https://doi.org/10.1145/127601.127675

Published: 01 June 1991 Publication History

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References

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Cited By

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Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Cheang SLee KLeung K(2007)Applying Genetic Parallel Programming to Synthesize Combinational Logic CircuitsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2006.88404411:4(503-520)Online publication date: 1-Aug-2007
https://dl.acm.org/doi/10.1109/TEVC.2006.884044
Cong JMinkovich K(2007)Optimality Study of Logic Synthesis for LUT-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88792226:2(230-239)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.887922
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A heuristic method for FPGA technology mapping based on the edge visibility

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FPGA technology mapping: a study of optimality
DAC '05: Proceedings of the 42nd annual Design Automation Conference

This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed ...
Complexity issues and algorithms for LUT-based FPGA technology mapping
Dual-output LUT merging during FPGA technology mapping
ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Modern commercial Field-Programmable Gate Array (FPGA) architectures support dual-output look-up tables (LUTs). If the number of total inputs in two small LUTs do not exceed the constraint, e.g., 5 in Xilinx UltraScale+ series, we can pack them into one ...

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Khurshid B(2017)LUT based realization of fixed-point multipliers targeting state-of-art FPGAsDesign Automation for Embedded Systems10.1007/s10617-017-9184-x21:2(89-115)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10617-017-9184-x
Cheang SLee KLeung K(2007)Applying Genetic Parallel Programming to Synthesize Combinational Logic CircuitsIEEE Transactions on Evolutionary Computation10.1109/TEVC.2006.88404411:4(503-520)Online publication date: 1-Aug-2007
https://dl.acm.org/doi/10.1109/TEVC.2006.884044
Cong JMinkovich K(2007)Optimality Study of Logic Synthesis for LUT-Based FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88792226:2(230-239)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.887922
Cong JMinkovich KWilton SDeHon A(2006)Optimality study of logic synthesis for LUT-based FPGAsProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117207(33-40)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117207
Chowdhary AHayes J(2006)Area-optimal technology mapping for field-programmable gate arrays based on lookup tablesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85089324:7(999-1013)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.850893
Wen-Zen Shen (2006)Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping32nd Design Automation Conference10.1109/DAC.1995.250065(65-69)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250065
Beetem J(2006)RebelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70393817:5(444-451)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703938
Chang SCheng KWoo NMarek-Sadowska M(2006)Postlayout logic restructuring using alternative wiresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.64061716:6(587-596)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.640617
Chang SMarek-Sadowdka MHwang T(2006)Technology mapping for TLU FPGAs based on decomposition of binary decision diagramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.54144215:10(1226-1236)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.541442
Chen CTsay YHwang TWu ALin Y(2006)Combining technology mapping and placement for delay-minimization in FPGA designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40670914:9(1076-1084)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.406709
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FPGA technology mapping: a study of optimality

Complexity issues and algorithms for LUT-based FPGA technology mapping

Dual-output LUT merging during FPGA technology mapping