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Techniques for scalable and effective routability evaluation

Authors:

Natarajan Viswanathan,

Charles J. Alpert,

Andrew D. Huber,

Gustavo E. Tellez,

Douglas Keller,

Sachin S. SapatnekarAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 2

Article No.: 17, Pages 1 - 37

https://doi.org/10.1145/2566663

Published: 28 March 2014 Publication History

Abstract

Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast design closure can only be achieved by accurately evaluating whether a design is routable or not early in the design cycle. Lately, it has become common to use a “light mode” version of a global router to quickly evaluate the routability of a given placement. This approach suffers from three weaknesses: (i) it does not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing; (ii) the congestion maps obtained by it tend to have isolated hotspots surrounded by noncongested spots, called “noisy hotspots”, which further affects the accuracy in routability evaluation; and (iii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer, and moreover, they may often fail to predict the routability accurately. This article presents solutions to these issues. First, we propose three approaches to model local routing resources. Second, we propose a smoothing technique to reduce the number of noisy hotspots and obtain a more accurate routability evaluation result. Finally, we develop a new metric which represents congestion maps with higher fidelity. We apply the proposed techniques to several industrial circuits and demonstrate that one can better predict and evaluate design routability and that congestion mitigation tools can perform much better to improve the design routability.

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Cited By

Daboul SHeld SNatura BRotter D(2023)Global Interconnect OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/358704428:5(1-24)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3587044
Amuru DZahra AVudumula HCherupally PGurram SAhmad AAbbas Z(2023)AI/ML algorithms and applications in VLSI design and technologyIntegration, the VLSI Journal10.1016/j.vlsi.2023.06.00293:COnline publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1016/j.vlsi.2023.06.002
Chen XDi ZWu WWu QShi JFeng Q(2022)Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning ModelIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.309342069:2(564-568)Online publication date: Feb-2022
https://doi.org/10.1109/TCSII.2021.3093420
Show More Cited By

Index Terms

Techniques for scalable and effective routability evaluation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Information & Contributors

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 19, Issue 2

March 2014

314 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2597648

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 March 2014

Accepted: 01 December 2013

Revised: 01 May 2013

Received: 01 December 2012

Published in TODAES Volume 19, Issue 2

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Cited By

Daboul SHeld SNatura BRotter D(2023)Global Interconnect OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/358704428:5(1-24)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3587044
Amuru DZahra AVudumula HCherupally PGurram SAhmad AAbbas Z(2023)AI/ML algorithms and applications in VLSI design and technologyIntegration, the VLSI Journal10.1016/j.vlsi.2023.06.00293:COnline publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1016/j.vlsi.2023.06.002
Chen XDi ZWu WWu QShi JFeng Q(2022)Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning ModelIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.309342069:2(564-568)Online publication date: Feb-2022
https://doi.org/10.1109/TCSII.2021.3093420
Daboul SHeld SNatura BRotter D(2019)Global Interconnect Optimization2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942155(1-8)Online publication date: Nov-2019
https://doi.org/10.1109/ICCAD45719.2019.8942155
Téllez GHu JWei Y(2016)RoutingElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-10(183-216)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-10
Qi ZCai YZhou Q(2014)Accurate prediction of detailed routing congestion using supervised data learning2014 IEEE 32nd International Conference on Computer Design (ICCD)10.1109/ICCD.2014.6974668(97-103)Online publication date: Oct-2014
https://doi.org/10.1109/ICCD.2014.6974668

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