[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
research-article

Low-power skewed-load tests based on functional broadside tests

Published: 28 March 2014 Publication History

Abstract

This article studies the generation of low-power skewed-load tests such that the signal transitions (and line values) they create during their fast functional clock cycles match those of functional broadside tests. Functional broadside tests create functional operation conditions during their fast functional clock cycles. As a result, the signal transitions that occur during these clock cycles can also occur during functional operation. The procedure described in this article matches these signal-transitions on a line-by-line basis when generating low-power skewed-load tests. The procedure accepts a functional broadside test set for transition faults. In one of its basic steps, the procedure modifies a functional broadside test into a skewed-load test. This allows it to retain many of the signal transitions (and line values) of the functional broadside test in the skewed-load test. Experimental results for benchmark circuits demonstrate the extent to which it is possible to match the signal-transitions of skewed-load tests with those of functional broadside tests while achieving the high transition fault coverage that is typical of skewed-load tests.

References

[1]
K. M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, and G. Hetherington. 2004. Minimizing power consumption in scan testing: Pattern generation and DFT techniques. In Proceedings of the International Test Conference. IEEE, 355--364.
[2]
A. Chandra and K. Chakrabarty. 2002. Reduction of SOC test data volume, scan power and testing time using alternating runlength codes. In Proceedings of the Design Automation Conference. ACM, 673--678.
[3]
V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy. 1998. Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 17, 2, 1325--1333.
[4]
V. R. Devanathan, C. P. Ravikumar, and V. Kamakoti. 2007. On power-profiling and pattern generation for power-safe scan tests. In Proceedings of the Design, Automation & Test in Europe Conference. IEEE, 1--6.
[5]
S. Kajihara, K. Ishida, and K. Miyase. 2002. Test vector modification for power reduction during scan testing. In Proceedings of the VLSI Test Symposium. IEEE, 160--165.
[6]
K. Lee, S. Hsu, and C. Ho. 2004. Test power reduction with multiple capture orders. In Proceedings of the Asian Test Symposium. IEEE, 26--31.
[7]
K.-J. Lee, T.-C. Huang, and J.-J. Chen. 2000. Peak-power reduction for multiple-scan circuits during test application. In Proceedings of the Asian Test Symposium. IEEE, 453--458.
[8]
J. Lee, S. Narayan, M. Kapralos, and M. Tehranipoor. 2008. Layout-aware, IR-drop tolerant transition fault pattern generation. In Proceedings of the Design, Automation and Test in Europe Conference. IEEE, 1172--1177.
[9]
J. Lee and M. Tehranipoor. 2008. LS-TDF: Low-switching transition delay fault pattern generation. In Proceedings of the VLSI Test Symposium. IEEE, 227--232.
[10]
W. Li, S. M. Reddy, and I. Pomeranz. 2004. On test generation for transition faults with minimized peak power dissipation. In Proceedings of the Design Automation Conference. IEEE, 504--509.
[11]
I. Pomeranz. 2011. Augmenting functional broadside tests for transition fault coverage with bounded switching activity. In Proceedings of the Pacific Rim International Symposium on Dependable Computing. IEEE, 38--44.
[12]
I. Pomeranz. 2013. Signal-transition patterns of functional broadside tests. IEEE Trans. Computers 62, 12, 2544--2549.
[13]
I. Pomeranz and S. M. Reddy. 2008. Functional broadside tests with minimum and maximum switching activity. ASP J. Low Power Electron. 4, 3, 429--437.
[14]
I. Pomeranz and S. M. Reddy. 2006. Generation of functional broadside tests for transition faults. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 25, 10, 2207--2218.
[15]
P. Rosinger, B. M. Al-Hashimi, and N. Nicolici. 2004. Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 23, 7, 1142--1153.
[16]
A. Sabne, R. Tiwari, A. Shrivastava, S. Ravi, and R. Parekhji. 2010. A generic low power scan chain wrapper for designs using scan compression. In Proceedings of the VLSI Test Symposium. IEEE, 135--140.
[17]
R. Sankaralingam, R. R. Oruganti, and N. A. Touba. 2000. Static compaction techniques to control scan vector power dissipation. In Proceedings of the VLSI Test Symposium. IEEE, 35--40.
[18]
J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind, P. Sreeprakash, and M. Hachinger. 2003. A case study of IR-drop in structured at-speed testing. In Proceedings of the International Test Conference. IEEE, 1098--1104.
[19]
J. Saxena, K. M. Butler, and L. Whetsel. 2001. An analysis of power reduction techniques in scan testing. In Proceedings of the International Test Conference. IEEE, 670--677.
[20]
C.-W. Tzeng and S.-Y. Huang. 2009. QC-Fill: Quick-and-Cool X-Filling for multicasting-based scan test. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 28, 11, 1756--1766.
[21]
X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja. 2008. A capture-safe test generation scheme for at-speed scan testing. In Proceedings of the European Test Symposium. IEEE, 55--60.
[22]
X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita. 2005. Low-capture-power test generation for scan-based testing. In Proceedings of the International Test Conference. IEEE, 1019--1028.
[23]
X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. A. Kochte, S. Kajihara, P. Girard, and M. Tehranipoor 2011. Power-aware test generation with guaranteed launch safety for at-speed scan testing. In Proceedings of the VLSI Test Symposium. IEEE, 166--171.
[24]
L. Whetsel, 2000. Adapting scan architectures for low power operation. In Proceedings of the International Test Conference. IEEE, 863--872.
[25]
M.-F. Wu, H.-C. Pan, T.-H. Wang, J.-L. Huang, K.-H. Tsai, and W.-T. Cheng. 2010. Improved weight assignment for logic switching activity during at-speed test pattern generation. In Proceedings of the Asia and South Pacific Design Automation Conference. IEEE, 493--498.
[26]
D. Xiang, S. Gu, J.-G. Sun, and Y.-L. Wu. 2003. A cost-effective scan architecture for scan testing with nonscan test power and test application cost. In Proceedings of the Design Automation Conference. IEEE, 744--747.

Cited By

View all
  • (2015)Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test SetIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231117023:3(593-597)Online publication date: Mar-2015

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 19, Issue 2
March 2014
314 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/2597648
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

Publication History

Published: 28 March 2014
Accepted: 01 August 2013
Revised: 01 February 2013
Received: 01 September 2012
Published in TODAES Volume 19, Issue 2

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Functional broadside tests
  2. low-power test generation
  3. skewed-load tests
  4. switching activity
  5. transition faults

Qualifiers

  • Research-article
  • Research
  • Refereed

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 03 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2015)Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test SetIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231117023:3(593-597)Online publication date: Mar-2015

View Options

Login options

Full Access

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media