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Density gradient minimization with coupling-constrained dummy fill for CMP control

Authors:

Yao-Wen ChangAuthors Info & Claims

ISPD '10: Proceedings of the 19th international symposium on Physical design

Pages 105 - 111

https://doi.org/10.1145/1735023.1735052

Published: 14 March 2010 Publication History

Abstract

In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase interconnect coupling capacitance and thus circuit delay, and might also lead to explosion of mask data due to the extra layout patterns. Traditional dummy-fill algorithms try to make each tile (window) density satisfy foundry's density upper and lower bounds under the coupling constraint. As technology advances, however, it is not sufficient to just keep the pattern density variation of each layer within density bounds. The density gradient, besides the density variation, plays a pivotal role in determining the post-CMP thickness of modern circuit designs. In this paper, we present the first gradient-driven dummy-fill algorithm to address the density gradient and other classical objectives (such as density variation, coupling constraints, dummy count) as well. Our dummy-fill algorithm has the two distinguished features: (1) Gaussian smoothing based gradient-driven multilevel dummy density analysis to minimize density gradient level by level, and (2) ILP-based fill synthesis to insert the fewest dummies within the coupling-violation-free feasible regions while satisfying the density constraints. Experimental results show that our algorithm can achieve promising results by inserting minimal dummies to reduce the density gradient and variation under the coupling constraints with a reasonable runtime overhead.

References

[1]

H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, "Novel Wire Density Driven Full-Chip Routing for CMP Variation Control," Proc. of IEEE/ACM International Conf. on Computer-Aided Design, pp. 831--838, Nov. 2007.

Digital Library

[2]

Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky, Practical Iterated Fill Synthesis for CMP Uniformity, Proc. of ACM/IEEE Design Automation Conference, pp. 671--674, Jun. 2000.

Digital Library

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Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky, "Closing the Smoothness and Uniformity Gap in Area Fill Synthesis," Proc. of ACM International Symposium on Physical Design, pp. 137--142, Apr. 2002.

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M. Cho, D. Z. Pan, H. Xiang, and R. Puri, "Wire Density Driven Global Routing for CMP Variation and Timing," Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 487--492, Nov. 2006.

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GTstyle, "The Next Generation Tool for Dummy Filling, available at http://www.xyalis.com/gtstyle.htm

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A. B. Kahng and K. Samadi, "CMP Fill Synthesis: A Survey of Recent Studies." IEEE Trans. on Computer-Aided Design, vol. 27, no. 1, pp. 3--19, Jan. 2008.

Digital Library

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K. S.-M. Li, Y.-W. Chang, C.-L. Lee, C. Su, and J. E. Chen, "Multilevel Full-Chip Routing with Testability and Yield Enhancement." IEEE Trans. on Computer-Aided Design, vol. 26, no. 9, pp. 1625--1636, Sep. 2007.

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T. H. Park, Characterization and Modeling of Pattern Dependencies in Copper Interconnects for Integrated Circuits, Ph.D. Dissertation, Dep. of EECS, MIT, May 2002.

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D. Reed, "Metal Fill Crosses the Threshold from Manufacturing to Design," Electonic Design, Jan. 7, 2007.

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D. Reed, "Dummy Fill Needs to Wise up," Chip Design, Jan. 15, 2007.

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P. L. Reu, R. L. Engelstad, and E. G. Lovell, "Mask Distortion Issues for Next-generation Lithography, Microelectronic Engineering, vol. 69, no. 2-4, pp. 420--428, Sep. 2003.

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B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R.Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. kapoor, "The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes," IEEE Trans. on Electron Devices, vol. 45, no. 3, pp. 665--679, Mar. 1998.

[14]

The VCMP team, Taiwan Semiconductor Manufacturing Company (TSMC), Ltd.

[15]

H. Xiang, L. Deng, R. Puri, K.-Y. Chao, and M. D. F. Wang, "Dummy Fill Density Analysis with Coupling Constraints," Proc. of ACM International Symposium on Physical Design, pp. 3--9, Mar. 2007.

Digital Library

Cited By

Paul SMukherjee TBanerjee PSur-Kolay S(2023)Concurrent Steiner Tree Selection for Global routing with EUVL Flare ReductionIntegration10.1016/j.vlsi.2023.04.00792(66-76)Online publication date: Sep-2023
https://doi.org/10.1016/j.vlsi.2023.04.007
Kong MKim DKweon MKang SSavidis ISasan AThapliyal HDeMara R(2022)GAN-Dummy Fill: Timing-aware Dummy Fill Method using GANProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530352(177-181)Online publication date: 6-Jun-2022
https://dl.acm.org/doi/10.1145/3526241.3530352
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
Show More Cited By

Index Terms

Density gradient minimization with coupling-constrained dummy fill for CMP control
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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Published In

cover image ACM Conferences

ISPD '10: Proceedings of the 19th international symposium on Physical design

March 2010

220 pages

ISBN:9781605589206

DOI:10.1145/1735023

General Chair:
Prashant Saxena
Synopsys
,
Program Chair:
Yao-Wen Chang
National Taiwan University

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 14 March 2010

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ISPD '10: International Symposium on Physical Design

March 14 - 17, 2010

California, San Francisco, USA

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ISPD '10 Paper Acceptance Rate 22 of 70 submissions, 31%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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International Symposium on Physical Design

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Cited By

Paul SMukherjee TBanerjee PSur-Kolay S(2023)Concurrent Steiner Tree Selection for Global routing with EUVL Flare ReductionIntegration10.1016/j.vlsi.2023.04.00792(66-76)Online publication date: Sep-2023
https://doi.org/10.1016/j.vlsi.2023.04.007
Kong MKim DKweon MKang SSavidis ISasan AThapliyal HDeMara R(2022)GAN-Dummy Fill: Timing-aware Dummy Fill Method using GANProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530352(177-181)Online publication date: 6-Jun-2022
https://dl.acm.org/doi/10.1145/3526241.3530352
Bai XZhu ZLi PChen JLan TLi XYu JZhu WChang Y(2022)Timing-Aware Fill Insertions With Design-Rule and Density ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313385441:10(3529-3542)Online publication date: Oct-2022
https://doi.org/10.1109/TCAD.2021.3133854
Paul SBanerjee PSur‐Kolay S(2021)A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segmentsIET Circuits, Devices & Systems10.1049/cds2.1202815:4(310-329)Online publication date: 29-Mar-2021
https://doi.org/10.1049/cds2.12028
Yu SKao CHuang CJiang I(2020)Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC47756.2020.9045668(133-138)Online publication date: Jan-2020
https://doi.org/10.1109/ASP-DAC47756.2020.9045668
Lin YYu BPan D(2017)High Performance Dummy Fill Insertion With Coupling and Uniformity ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.263845236:9(1532-1544)Online publication date: Sep-2017
https://doi.org/10.1109/TCAD.2016.2638452
Geng CLiu BNakatake S(2017)Explicit layout pattern density controlling based on transistor-array-style2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053233(1557-1560)Online publication date: Aug-2017
https://doi.org/10.1109/MWSCAS.2017.8053233
Shomalnasab GZhang L(2017)Analog layout density uniformity improvement using interconnect widening and dummy fill insertion2017 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2017.8050745(1-4)Online publication date: May-2017
https://doi.org/10.1109/ISCAS.2017.8050745
Chiang HLiu CJiang JChang Y(2016)Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware DummificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248849235:4(598-610)Online publication date: Apr-2016
https://doi.org/10.1109/TCAD.2015.2488492
Chang YLiu RFang S(2015)EUV and e-beam manufacturabilityProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2747925(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2747925
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