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The DAC 2012 routability-driven placement contest and benchmark suite

Authors:

Natarajan Viswanathan,

Charles Alpert,

Yaoguang WeiAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 774 - 782

https://doi.org/10.1145/2228360.2228500

Published: 03 June 2012 Publication History

Abstract

Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing blockages, etc. In addition, they are hampered by congestion metrics that do not accurately score or represent design congestion. This is in large part due to the non-availability of public designs depicting industrial wiring stacks and other complexities affecting design routability.

The aim of the DAC 2012 routability-driven placement contest is to address these issues, by way of the following: (a) release challenging benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, (b) present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms. We hope that a set of challenging benchmarks, along with a standard, publicly available evaluation framework will further advance research in routability-driven placement.

References

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Cited By

Cai HZhou RHuang PJing YLiu G(2024)SLDPSO-TA: Track Assignment Algorithm Based on Social Learning Discrete Particle Swarm OptimizationElectronics10.3390/electronics1322457113:22(4571)Online publication date: 20-Nov-2024
https://doi.org/10.3390/electronics13224571
Gottesbüren LHeuer TMaas NSanders PSchlag S(2024)Scalable High-Quality Hypergraph PartitioningACM Transactions on Algorithms10.1145/362652720:1(1-54)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1145/3626527
Qi ZPeng QHu SYou H(2024)Effective Heterogeneous Graph Neural Network for Routing Congestion Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617734(369-373)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617734
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Index Terms

The DAC 2012 routability-driven placement contest and benchmark suite
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Cai HZhou RHuang PJing YLiu G(2024)SLDPSO-TA: Track Assignment Algorithm Based on Social Learning Discrete Particle Swarm OptimizationElectronics10.3390/electronics1322457113:22(4571)Online publication date: 20-Nov-2024
https://doi.org/10.3390/electronics13224571
Gottesbüren LHeuer TMaas NSanders PSchlag S(2024)Scalable High-Quality Hypergraph PartitioningACM Transactions on Algorithms10.1145/362652720:1(1-54)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1145/3626527
Qi ZPeng QHu SYou H(2024)Effective Heterogeneous Graph Neural Network for Routing Congestion Prediction2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617734(369-373)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617734
Qi YGan ZDing JFu ZGong MYu W(2024)Track Assignment Using Gradient Indication and Simulated Annealing2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557940(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557940
Jin YYang XLu Y(2024)Deep Learning-based Algorithm for Multi-objective Driver Chip Cell Layout Optimization2024 IEEE 7th International Conference on Electronic Information and Communication Technology (ICEICT)10.1109/ICEICT61637.2024.10671092(1369-1374)Online publication date: 31-Jul-2024
https://doi.org/10.1109/ICEICT61637.2024.10671092
Liu BQiao CXu NGeng XZhu ZYang JKim T(2024)Variational Label-Correlation Enhancement for Congestion PredictionProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473930(466-471)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473930
Yu HHuang SRen L(2024)Research on Methods for Very Large Scale Integration Track Assignment RoutingMATEC Web of Conferences10.1051/matecconf/202439900015399(00015)Online publication date: 24-Jun-2024
https://doi.org/10.1051/matecconf/202439900015
Qiu YXing YZheng XGao PCai SXiong X(2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
https://doi.org/10.3390/electronics12020337
Schlag SHeuer TGottesbüren LAkhremtsev YSchulz CSanders P(2023)High-Quality Hypergraph PartitioningACM Journal of Experimental Algorithmics10.1145/352909027(1-39)Online publication date: 10-Feb-2023
https://dl.acm.org/doi/10.1145/3529090
Chai ZZhao YLiu WLin YWang RHuang R(2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning StrategiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328797042:12(5034-5047)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3287970
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