A Technique for Logic Fault Diagnosis of Interconnect Open Defects

A technique for performing logic diagnosis of defects that cause interconnects in a digital logic circuit to become open or highly resistive is presented. The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect on an interconnect and diagnosis algorithms that leverage the diagnostic model. The technique circumvents the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitances, and is easily integratable into conventional test and simulation tools. Other aspects of the technique include a path-tracing procedure to limit the number of interconnects that need to be analyzed and extensions for multiple defects. Experimental results include simulation results on processor functional blocks and silicon results on a chipset from artificially induced defects and production fallout.