Cited By
View all- Koenemann B(2004)Design/process learning from electrical testProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382673(733-738)Online publication date: 7-Nov-2004
Yield Analysis of Logic Circuits
Abstract
Complex SOC's developed in VDSMtechnologies require adequate solutions to diagnose andanalyze yield losses. This paper focuses on the diagnosisof logic circuits embedded in SOCs. The core instrumentleveraged is ATPG used during test vectors generation andanalysis of failures. This work emphasizes the resultsobtained in systematically applying ATPG diagnosis onfailures detected in the manufacturing test floor. Details ondiagnosis flow and ATE data collection are given.Experimental results are provided.
References
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Index Terms
- Yield Analysis of Logic Circuits
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Published In
April 2004
ISBN:0769521347
Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Publisher
IEEE Computer Society
United States
Publication History
Published: 25 April 2004
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Cited By
View all- Koenemann B(2004)Design/process learning from electrical testProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382673(733-738)Online publication date: 7-Nov-2004