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In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is ...

This paper describes the use of Symbolic Trajectory Evaluation (STE), a modified form of symbolic simulation, to verify the equivalence between RTL and transistor-level representations of on-chip custom memories for the latest PowerPC microprocessor. ...

This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its ...

Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes ...

In the last decade, researchers devoted many efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application ...

Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause problems both with heat dissipation and with current spikes. Compacting scan ...

Silicon-on-insulator (SOI) SRAMs have different characteristics from those fabricated in traditional bulk silicon. Fault models and sensitivities must be considered when testing for SOI manufacturing defects. Circuit details of SOI SRAMs that relate to ...

Capacitive coupling between interconnects can lead to pattern-dependent delay variation. Statistical process variation results in variation in gate and interconnects delays, and interconnect coupling. These effects become increasingly important in deep ...

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may ...

Boundary-Scan (B-S) strategies require successful coordination of B-S activities for the devices integrated on boards and systems. The original Boundary-Scan Master (BSM) chip was developed to achieve this coordination. We have recently designed the ...

A novel design-for-test (DFT) technique is presented for designing a core with a virtual scan chain which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are ...

This paper presents a rapid and scalable built-in self-test (BIST) diagnosis scheme for handling BIST environments with a large number of scan chains. The problem of identifying which scan cells captured errors during the BIST session is formulated here ...

We describe a new framework to minimize test escape (TE) and yield loss (YL) during IDDQ testing. The proposed framework defines the concept of critical severity of a fault Sk', that provides a link between the fault magnitude and violation of one or ...

Various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature can affect the performance of deep sub-micron designs. In order to capture the effects of these statistical variations on circuit ...

Bridging faults in CMOS, circuits are usually modeled as a wired-OR, wired-AND, or small fixed resistance, however real bridging faults have a resistance distribution ranging from very small to quite large resistances. The parametric model has been ...

We present a new test data compression method and decompression architecture based on Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SOC). The major advantages of ...

This paper describes the test challenges faced and testability features implemented on Level One's networking System on Chip (SoC), IXE2000. The IXE2000 SoC is a 20+ million transistor Layer 2/3/4 Switch with 24 IO/IOOMbps and 2 IOOOMbps Ethernet ports, ...

Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. Efficient test access architecture ...

ATPG approaches for analog circuits in the past have targeted the testing of catastrophic and parametric faults. It has been shown recently that analog circuit specifications can be predicted from the transient response of the circuit under test.In this ...

We propose a comprehensive built-in self-test (BIST) methodology for analog and mixed-signal circuits. A time-division multiplexing (TDM) comparator scheme was proposed as an effective signature analyzer for on-chip analog response compaction and pass/...