More Web Proxy on the site http://driver.im/

research-article

Efficient SMT-based ATPG for interconnect open defects

Authors:

Karsten Scheibler,

Matthias Sauer,

Bernd BeckerAuthors Info & Claims

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

Article No.: 125, Pages 1 - 6

Published: 24 March 2014 Publication History

Abstract

Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy.

This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations. It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values. Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude.

References

[1]

S. Murarka, I. Verner, and R. Gutmann, Copper-fundamental mechanisms for microelectronic applications. John Wiley, 2000.

[2]

Y. Sato, L. Yamazaki et al., "A persistent diagnostic technique for unstable defects," in Test Conference, 2002. Proceedings. International, 2002.

Digital Library

[3]

G. Chen, S. Reddy et al., "A unified fault model and test generation procedure for interconnect opens and bridges," in Test Symposium, 2005.

Digital Library

[4]

S. Rafiq, A. Ivanov et al., "Testing for floating gates defects in CMOS circuits," in Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian, 1998, pp. 228--236.

Digital Library

[5]

D. Arumí, R. Rodríguez-Montañés, and J. Figueras, "Experimental characterization of CMOS interconnect open defects," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 27, no. 1, pp. 123--136, 2008.

Digital Library

[6]

H. Konuk and F. Ferguson, "Oscillation and sequential behavior caused by interconnect opens in digital CMOS circuits," in Test Conference, 1997. Proceedings., International, 1997, pp. 597--606.

Digital Library

[7]

R. Gomez, A. Giron, and V. Champac, "Test of interconnection opens considering coupling signals," in Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on, 2005.

Digital Library

[8]

S. Spinner, I. Polian et al., "Automatic test pattern generation for interconnect open defects," in 26th IEEE VTS 2008., 2008.

Digital Library

[9]

S. Reddy, I. Pomeranz, and C. Liu, "On tests to detect via opens in digital CMOS circuits," in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 840--845.

Digital Library

[10]

S. Hillebrecht, I. Polian et al., "Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model," in Test Conference, 2008. ITC 2008. IEEE International, 2008, pp. 1--10.

[11]

S. Venkataraman and S. Drummonds, "A technique for logic fault diagnosis of interconnect open defects," in VLSI Test Symposium, 2000. Proceedings. 18th IEEE, 2000, pp. 313--318.

Digital Library

[12]

S. Reddy, I. Pomeranz et al., "On testing of interconnect open defects in combinational logic circuits with stems of large fanout," in Test Conference, 2002. Proceedings. International, 2002, pp. 83--89.

Digital Library

[13]

S. Hillebrecht, M. A. Kochte et al., "Exact stuck-at fault classification in presence of unknowns," in Proc. IEEE ETS, 2012, pp. 1--6.

[14]

M. A. Kochte and H.-J. Wunderlich, "SAT-based fault coverage evaluation in the presence of unknown values," in Proc. Design, Automation and Test in Europe (DATE'11), 2011, pp. 1--6.

[15]

M. Fränzle, C. Herde et al., "Efficient solving of large non-linear arithmetic constraint systems with complex Boolean structure," Journal on Satisfiability, Boolean Modeling and Computation, vol. 1, pp. 209--236, 2007.

[16]

K. Scheibler, S. Kupferschmid, and B. Becker, "Recent improvements in the SMT solver iSAT," in MBMV'13, 2013, pp. 231--241.

[17]

K. Scheibler and B. Becker, "Implication graph compression inside the SMT solver iSAT3," in to appear in MBMV'14, 2014.

[18]

M. Davis, G. Logemann, and D. Loveland, "A machine program for theorem proving," Communications of the ACM, vol. 5, pp. 394--397, 1962.

Digital Library

[19]

G. Tseitin, "On the complexity of derivation in propositional calculus," Studies in constructive mathematics and mathematical logic, vol. 2, 1968.

[20]

D. Erb, M. A. Kochte et al., "Accurate multi-cycle ATPG in presence of x-values," in to be published in ATS13, 2013.

Digital Library

[21]

T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. CAD, vol. 11, no. 1, pp. 4--15, jan 1992.

Digital Library

Cited By

Pomeranz I(2019)Incomplete Tests for Undetectable Faults to Improve Test Set QualityACM Transactions on Design Automation of Electronic Systems10.1145/330649324:2(1-13)Online publication date: 13-Feb-2019
https://dl.acm.org/doi/10.1145/3306493
Scheibler KBecker BJobstmann B(2014)Using Interval Constraint Propagation for Pseudo-Boolean Constraint SolvingProceedings of the 14th Conference on Formal Methods in Computer-Aided Design10.5555/2682923.2682958(203-206)Online publication date: 21-Oct-2014
https://dl.acm.org/doi/10.5555/2682923.2682958

Index Terms

Efficient SMT-based ATPG for interconnect open defects
1. Hardware

Recommendations

Automatic Test Pattern Generation for Interconnect Open Defects
VTS '08: Proceedings of the 26th IEEE VLSI Test Symposium

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open-via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the ...
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects
ATS '14: Proceedings of the 2014 IEEE 23rd Asian Test Symposium

Open defects such as interconnect opens are known to be one of the predominant defects in nanoscale technologies. Yet, test pattern generation for open defects is challenging because of the high number of parameters which need to be considered. ...
Gate Leakage Impact on Full Open Defects in Interconnect Lines

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

March 2014

1959 pages

ISBN:9783981537024

General Chairs:
Gerhard Fettweis
TU Dresden, DE
,
Wolfgang Nebel
OFFIS, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

In-Cooperation

SIGDA: ACM Special Interest Group on Design Automation

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 24 March 2014

Check for updates

Author Tags

Qualifiers

Research-article

Conference

DATE '14

Sponsor:

EDAA
EDAC
The Russian Academy of Sciences

DATE '14: Design, Automation and Test in Europe

March 24 - 28, 2014

Dresden, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
40
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 18 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Pomeranz I(2019)Incomplete Tests for Undetectable Faults to Improve Test Set QualityACM Transactions on Design Automation of Electronic Systems10.1145/330649324:2(1-13)Online publication date: 13-Feb-2019
https://dl.acm.org/doi/10.1145/3306493
Scheibler KBecker BJobstmann B(2014)Using Interval Constraint Propagation for Pseudo-Boolean Constraint SolvingProceedings of the 14th Conference on Formal Methods in Computer-Aided Design10.5555/2682923.2682958(203-206)Online publication date: 21-Oct-2014
https://dl.acm.org/doi/10.5555/2682923.2682958

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents