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Logic design principles with emphasis on testable semicustom circuitsJune 1986
Publisher:
  • Prentice-Hall, Inc.
  • Division of Simon and Schuster One Lake Street Upper Saddle River, NJ
  • United States
ISBN:978-0-13-539784-8
Published:24 June 1986
Pages:
549
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Abstract

No abstract available.

Cited By

  1. Sapozhnikov V, Sapozhnikov V and Efanov D (2022). Duplication of Boolean Complements for Synthesis of Fault-Tolerant Digital Devices and Systems, Automatic Control and Computer Sciences, 56:1, (1-9), Online publication date: 1-Feb-2022.
  2. Efanov D, Sapozhnikov V, Sapozhnikov V and Pivovarov D (2020). The Synthesis Conditions of Completely Self-Testing Embedded-Control Circuits Based on the Boolean Complement Method to the “1-out-of-m” Constant-Weight Code, Automatic Control and Computer Sciences, 54:2, (89-99), Online publication date: 1-Mar-2020.
  3. Efanov D, Sapozhnikov V and Sapozhnikov V (2019). Sum Codes with Fixed Values of Multiplicities for Detectable Unidirectional and Asymmetrical Errors for Technical Diagnostics of Discrete Systems, Automation and Remote Control, 80:6, (1082-1097), Online publication date: 1-Jun-2019.
  4. Tsunoda Y and Fujiwara Y On the Maximum Number of Codewords of X-Codes of Constant Weight Three 2019 IEEE International Symposium on Information Theory (ISIT), (1752-1756)
  5. Dmitriev V, Efanov D, Sapozhnikov V and Sapozhnikov V (2018). Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices, Automation and Remote Control, 79:4, (665-678), Online publication date: 1-Apr-2018.
  6. Lin D, Hong T, Li Y, Fallah F, Gardner D, Hakim N and Mitra S Overcoming post-silicon validation challenges through quick error detection (QED) Proceedings of the Conference on Design, Automation and Test in Europe, (320-325)
  7. Fujiwara Y and Colbourn C (2010). A combinatorial approach to X-tolerant compaction circuits, IEEE Transactions on Information Theory, 56:7, (3196-3206), Online publication date: 1-Jul-2010.
  8. Faraj K and Almaini A Optimal polarity for dual Reed-Muller expressions Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics, (45-52)
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    Saluja N, Gulati K and Khatri S (2008). SAT-based ATPG using multilevel compatible don't-cares, ACM Transactions on Design Automation of Electronic Systems, 13:2, (1-18), Online publication date: 2-Apr-2008.
  10. Faraj K and Almaini A Exact minimization of dual Reed-Muller expansions Proceedings of the 6th WSEAS international conference on Applied computer science, (361-367)
  11. Mitra S and Kim K (2006). XPAND, IEEE Transactions on Computers, 55:2, (163-173), Online publication date: 1-Feb-2006.
  12. Su M and Wang C High level equivalence symmetric input identification Proceedings of the 2006 Asia and South Pacific Design Automation Conference, (249-253)
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  14. Mange D, Sanchez E, Stauffer A, Tempesti G, Marchal P and Piguet C Embryonics Readings in hardware/software co-design, (643-655)
  15. Smalla C Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow Proceedings of the 2nd International Symposium on Quality Electronic Design
  16. Matthes D and Ford J Technique For Testing A Very High Speed Mixed Signal Read Channel Design Proceedings of the 2000 IEEE International Test Conference
  17. Mitra S and McCluskey E COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS Proceedings of the 2000 IEEE International Test Conference
  18. Mitra S, Avra L and McCluskey E (2000). Efficient Multiplexer Synthesis Techniques, IEEE Design & Test, 17:4, (90-97), Online publication date: 1-Oct-2000.
  19. Metra C and Lo J (2000). Intermediacy Prediction for High Speed Berger Code Checkers, Journal of Electronic Testing: Theory and Applications, 16:6, (607-615), Online publication date: 1-Dec-2000.
  20. Schmid J and Knäblein J Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs Proceedings of the 1999 17TH IEEE VLSI Test Symposium
  21. Konuk H and Ferguson F Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits Proceedings of the 1997 IEEE International Test Conference
  22. Shen Y, Chen X, Horiguchi S and Lombardi F On the multiple fault diagnosis of multistage interconnection networks Proceedings of the international Conference on Parallel Processing
  23. Mitra S, Avra L and McCluskey E SCAN SYNTHESIS FOR ONE-HOT SIGNALS Proceedings of the 1997 IEEE International Test Conference
  24. Mitra S, Avra L and McCluskey E An output encoding problem and a solution technique Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (304-307)
  25. Bertacco V and Damiani M The disjunctive decomposition of logic functions Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (78-82)
  26. Saxena N and McCluskey E (1996). Counting Two-State Transition-Tour Sequences, IEEE Transactions on Computers, 45:11, (1337-1342), Online publication date: 1-Nov-1996.
  27. Lee C and Sheu M (1996). A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines, IEEE Transactions on Computers, 45:9, (1079-1083), Online publication date: 1-Sep-1996.
  28. Bogliolo A and Damiani M Synthesis of multilevel fault-tolerant combinational circuits Proceedings of the 1995 European conference on Design and Test
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  30. Benini L, Siegel P and De Micheli G (1994). Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, 11:4, (32-41), Online publication date: 1-Oct-1994.
  31. Siegel P and De Micheli G Decomposition methods for library binding of speed-independent asynchronous designs Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (558-565)
  32. Pomeranz I and Reddy S On testing delay faults in macro-based combinational circuits Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (332-339)
  33. Clark D and Weng L (1994). Maximal and Near-Maximal Shift Register Sequences, IEEE Transactions on Computers, 43:5, (560-568), Online publication date: 1-May-1994.
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  36. Kameda T, Pilarski S and Ivanov A (1993). Notes on Multiple Input Signature Analysis, IEEE Transactions on Computers, 42:2, (228-234), Online publication date: 1-Feb-1993.
  37. Łuba T, Górski K and Wroński L ROM-based finite state machines with PLA address modifiers Proceedings of the conference on European design automation, (272-277)
  38. Lombardi F, Feng C and Huang W (1992). Detection and Location of Multiple Faults in Baseline Interconnection Networks, IEEE Transactions on Computers, 41:10, (1340-1344), Online publication date: 1-Oct-1992.
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  41. Wagner K (1988). Clock system design, IEEE Design & Test, 5:5, (9-27), Online publication date: 1-Sep-1988.
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  44. Wagner K, Chin C and McCluskey E (1987). Pseudorandom Testing, IEEE Transactions on Computers, 36:3, (332-343), Online publication date: 1-Mar-1987.
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Contributors
  • Stanford Engineering

Reviews

Chang Nian Zhang

This is an introductory level textbook on logic design. McCluskey has organized the book into four parts. The Overview part, the first four chapters, covers most of the basics: binary numbers and conversion to other bases, binary arithmetic, binary code. In addition, N-cubes, error detecting and correcting, Boolean rings, multiple-valued logic, and combinational hazards are also discussed. The second part, Combinational Circuit Design, covers the standard topic of combinational logic design. Chapter 5 presents special classes of combinational functions, and Chapter 6 discusses two techniques for implementing arbitrary combinational functions: the Karnaugh map technique and tabular techniques (Quine-McCluskey method) by various implementation procedures of two-stage realization. An introduction to multistage gate network design is also presented briefly. The third part, Sequential Circuit Design, consists of Chapters 7–9. Chapter 7 introduces the various types of latches and flip-flops. It also describes analyses of fundamental sequential circuits that use feedback or latches as memory elements. Chapter 8 presents different implementations of finite state machines. Chapter 9 discusses design methods for sequential circuits, either fundamental or pulse mode. The state reduction, variable assignment techniques are also presented. The final part, Design Structure, includes Chapters 10 and 11. Chapter 10 covers the problem of design for testability. This is the first time I have seen such a featured chapter in a logic design textbook. It discusses the current techniques and structures, as well as improvements used to ensure that the final design can be tested economically. The structures used in semicustom or MSI design to permit designing at a higher level than with individual gates are discussed in Chapter 11. But the functions of these MSI or cell libraries are limited to a few types. No general approach or other existing techniques are mentioned, such as silicon compilers, logic design based on production systems, or other more sophisticated AI-based design schemes, which seems to be a prevailing and appropriate topic at this level of text. The writing is clear, and the figures and tables are well done. Each chapter ends with a list of references and a sufficient amount of exercises (but no solutions are included). The author assumes some prerequisite technical and mathematical knowledge, which is required by the reader (such as basic hardware and electrical engineering theory). And the book covers more up-to-date techniques and applications than most other logic design textbooks. The book could be used by masters-level graduates in both computer science and electrical engineering, or as an excellent reference by students in the field.

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