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Testability of asynchronous timed control circuits with delay assumptions

Authors:

Peter A. Beerel,

Teresa H.-Y. MengAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 446 - 451

https://doi.org/10.1145/127601.127710

Published: 01 June 1991 Publication History

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References

[1]

Peter A. Beerel and Teresa H. Y. Meng, "Semi-Modularity and Self-Diagnostic Asynchronous Control Circuits", Proceedings of Advanced Research in VLSI Conference, 1990.

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Peter A. Beerel and Teresa H. Y. Meng, "Testability of Asynchronous Self-Timed Circuits with Delay Assumptions", to be submitted to the IEEE Transactions on Computer Aided Design.

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Tam-Anh Chu, Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Speciftcations, PhD thesis, Massachusetts Institute of Technology, 1987.

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Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, and Alberto Sangiovanni-Vincentelli, "A Synthesis and Optimation Procedure for Fully and Easily Testable Sequential Machines", IEEE Transactions on Computer-Aided Design, October 1989.

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Michiel Kamps, "Testing of Delay-Insensitive Circuits: A Case Study", Designing Delay-lnsensitve Circuits, Eindhoven University of Techology, September 1990.

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Alain J. Martin and Pieter J. Hazewindus, "Tesing Delay- Insensitive Circuits", Proceedings of Advanced Research in VLSI Conference, 1990.

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Edward J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, Englewood Cliffs, NJ, 1986.

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Teresa H. Y. Meng, Robert W. Brodersen, and David G. Messershmitt, "Automatic Synthesis of Asynchronous Circuits from High-Level Specifications", IEEE Transactions on Computer-Aided Design, November 1989.

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Cited By

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Lavagno LNowick S(2002)Asynchronous Control CircuitsLogic Synthesis and Verification10.1007/978-1-4615-0817-5_10(255-284)Online publication date: 2002
https://doi.org/10.1007/978-1-4615-0817-5_10
Brzozowski JRaahemifar K(1995)Testing C-elements is not elementaryProceedings Second Working Conference on Asynchronous Design Methodologies10.1109/WCADM.1995.514652(150-159)Online publication date: 1995
https://doi.org/10.1109/WCADM.1995.514652
Ding Lu Tong C(1995)High level fault modeling of asynchronous circuitsProceedings 13th IEEE VLSI Test Symposium10.1109/VTEST.1995.512636(190-195)Online publication date: 1995
https://doi.org/10.1109/VTEST.1995.512636
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Testability of asynchronous timed control circuits with delay assumptions
1. Hardware

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Lavagno LNowick S(2002)Asynchronous Control CircuitsLogic Synthesis and Verification10.1007/978-1-4615-0817-5_10(255-284)Online publication date: 2002
https://doi.org/10.1007/978-1-4615-0817-5_10
Brzozowski JRaahemifar K(1995)Testing C-elements is not elementaryProceedings Second Working Conference on Asynchronous Design Methodologies10.1109/WCADM.1995.514652(150-159)Online publication date: 1995
https://doi.org/10.1109/WCADM.1995.514652
Ding Lu Tong C(1995)High level fault modeling of asynchronous circuitsProceedings 13th IEEE VLSI Test Symposium10.1109/VTEST.1995.512636(190-195)Online publication date: 1995
https://doi.org/10.1109/VTEST.1995.512636
Davis ANowick S(1995)Asynchronous Circuit Design: Motivation, Background, & MethodsAsynchronous Digital Circuit Design10.1007/978-1-4471-3575-3_1(1-49)Online publication date: 1995
https://doi.org/10.1007/978-1-4471-3575-3_1
Ming-Der Shieh Chin-Long Wey Fisher P(1993)A scan design for asynchronous sequential logic circuits using SR-latchesProceedings of 36th Midwest Symposium on Circuits and Systems10.1109/MWSCAS.1993.343339(1300-1303)Online publication date: 1993
https://doi.org/10.1109/MWSCAS.1993.343339
Wey CShieh MFisher P(1993)ASLCScan: A scan design technique for asynchronous sequential logic circuitsProceedings of 1993 IEEE International Conference on Computer Design ICCD'9310.1109/ICCD.1993.393388(159-162)Online publication date: 1993
https://doi.org/10.1109/ICCD.1993.393388

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Delay Fault Testability on Two-Rail Logic Circuits

Optimization of NULL convention self-timed circuits

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability