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SAT-based ATPG using multilevel compatible don't-cares

Published: 23 April 2008 Publication History

Abstract

In a typical IC design flow, circuits are optimized using multilevel don't cares. The computed don't cares are discarded before Technology Mapping or Automatic Test Pattern Generation (ATPG). In this paper, we present two combinational ATPG algorithms for combinational designs. These algorithms utilize the multilevel don't cares that are computed for the design during technology independent logic optimization. They are based on Boolean Satisfiability (SAT), and utilize the single stuck-at fault model. Both algorithms make use of the Compatible Observability Don't Cares (CODCs) associated with nodes of the circuit, to speed up the ATPG process. For large circuits, both algorithms make use of approximate CODCs (ACODCs), which we can compute efficiently. Our first technique speeds up fault propagation by modifying the active clauses in the transitive fanout (TFO) of the fault site. In our second technique, we define new j-active variables for specific nodes in the transitive fanin (TFI) of the fault site. Using these j-active variables we write additional clauses to speed up fault justification. Experimental results demonstrate that the combination of these techniques (when using CODCs) results in an average reduction of 45% in ATPG runtimes. When ACODCs are used, a speed-up of about 30% is obtained in the ATPG run-times for large designs. We compare our method against a commercial structural ATPG tool as well. Our method is slower for small designs, but for large designs, we obtain a 31% average speedup over the commercial tool.

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  • (2013)ATPG for Cancer TherapyLogic Synthesis for Genetic Diseases10.1007/978-1-4614-9429-4_5(77-92)Online publication date: 1-Nov-2013
  • (2012)Application of logic synthesis to the understanding and cure of genetic diseasesProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228493(734-740)Online publication date: 3-Jun-2012

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 2
      April 2008
      272 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1344418
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 23 April 2008
      Accepted: 01 July 2007
      Revised: 01 March 2007
      Received: 01 June 2003
      Published in TODAES Volume 13, Issue 2

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      Author Tags

      1. Automatic test pattern generation (ATPG)
      2. Boolean satisfiabilty (SAT)
      3. don't cares
      4. testing

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      View all
      • (2013)ATPG for Cancer TherapyLogic Synthesis for Genetic Diseases10.1007/978-1-4614-9429-4_5(77-92)Online publication date: 1-Nov-2013
      • (2012)Application of logic synthesis to the understanding and cure of genetic diseasesProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228493(734-740)Online publication date: 3-Jun-2012

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