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Technique For Testing A Very High Speed Mixed Signal Read Channel Design

Published: 03 October 2000 Publication History

Abstract

PRML (Partial Response Maximum Likelihood)read channel devices are heterogeneous, complex,mixed signal devices. This paper describesmethodology for testing a state-of-the-art CMOS readchannel, including Design-for-Test (DfT) techniques,Device-Interface-Board (DIB) design features and testflow. DfT techniques such as scan, Built-In Self-Test(BIST) loop-back and ad-hoc analog test features arediscussed. Analog test grading methods (Test-for-Quality or TFQ) are also presented. Afterwards a briefoverview of the DIB hardware highlighting criticalfeatures such as wide band analog and high speeddigital undersampling tester interfaces are reviewed.An overview of the test suite defining the mix offunctional, structured, IDDQ and BIST tests is offered.The problems and possible solutions of embedding aPRML channel into a System-on-Chip are alsoextensively explored.

References

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  1. Technique For Testing A Very High Speed Mixed Signal Read Channel Design

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    cover image Guide Proceedings
    ITC '00: Proceedings of the 2000 IEEE International Test Conference
    October 2000
    ISBN:0780365461

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    IEEE Computer Society

    United States

    Publication History

    Published: 03 October 2000

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