[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/309847.309889acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free access

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

Published: 01 June 1999 Publication History
First page of PDF

References

[1]
S.S. Appleton, S.V. Morton, and M.J. Liebelt. Two-phase asynchronous pipeline control. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1997.
[2]
P.A. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In ICCAD, pages 581-586. IEEE Computer Society Press, November 1992.
[3]
M. Benes, S.M. Nowick, and A. Wolfe. A fast asynchronous Huffman decoder for compressed-code embedded processors. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, pages 43-56, 1998.
[4]
K. van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F. Schalij. A fully-asynchronous low-power error corrector for the DCC player. IEEE JSSC, 29(12):1429- 1439, December 1994.
[5]
J.G. Bredeson and P.T. Hulina. Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits. Information and Control, 20:114-224, 1972.
[6]
E. Brunvand. The NSR processor. In Proceedings of the 26th International Conference on System Sciences, Jan 1993.
[7]
E. Brunvand and R.F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD, pages 262- 265. IEEE Computer Society Press, November 1989.
[8]
S.M. Burns. General condition for the decomposition of state holding elements. In Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, pages 48-57. IEEE Computer Society Press, November 1996.
[9]
S.M. Burns and A.J. Martin. Syntax-directed translation of concurrent programs into self-timed circuits. In Advanced Research in VLSI, pages 35-50. MIT Press, Cambridge, MA, 1988.
[10]
S. Chakraborty, D.L. Dill, and K.Y. Yun. Min-max timing analysis and its application to asynchronous circuits. Proceedings of the IEEE, 87(2), Feb 1999.
[11]
D.M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University, October 1984.
[12]
T.-A. Chu. Synthesis of self-timed vlsi circuits from graphtheoretic specifications. Technical Report MIT-LCS-TR-393, MIT, 1987. Ph.D. Thesis.
[13]
W.A. Clark. Macromodular computer systems. In Spring Joint Computer Conference. AFIPS, April 1967.
[14]
W.A. Clark and C.E. Molnar. Macromodular system design. Technical Report 23, Computer Systems Laboratory, Washington University, April 1973.
[15]
W.S. Coates, J.K. Lexau, I.W. Jones, S.M. Fairbanks, and I. E. Sutherland. A FIFO data switch design experiment. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, pages 4-17, 1998.
[16]
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Methodology and tools for state encoding in asynchronous circuit synthesis. In DAC, June 1996.
[17]
A. Davis, B. Coates, and K. Stevens. Automatic synthesis of fast compact self-timed control circuits. In IFIP Working Conference on Asynchronous Design Methodologies, 1993.
[18]
A.L. Davis. The architecture and system method for DDMI: A recursively structured data-driven machine. In 5th Annual Syrup. on Computer Architecture, April 1978.
[19]
P. Day and J.V. Woods. Investigation into micropipeline latch design styles. IEEE TVLSI, 3(2):264-272, June 1995.
[20]
M.E. Dean. STRIP: A Self-Timed RISC Processor Architecture. PhD thesis, Stanford University, 1992.
[21]
J.C. Ebergen. A formal approach to designing delayinsensitive circuits. Distributed Computing, 5(3):107-119, 1991.
[22]
E.B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM Journal of Research and Development, 9(2):90-99, 1965.
[23]
R.M. Fuhrer, B. Lin, and S.M. Nowick. Symbolic hazardfree minimization and encoding of asynchronous finite state machines. In ICCAD, pages 604-611, November 1995.
[24]
S. Furber. Computing without clocks: Micropipelining the ARM processor. In Graham Birtwistle and A1 Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 211-262. Springer-Verlag, 1995.
[25]
S.B. Furber and P. Day. Four-phase micropipeline latch control circuits. IEEE TVLSI, 4(2):247-253, June 1996.
[26]
S.B. Furber, P. Day, J.D. Garside, N.C. Paver, and J.V. Woods. A micropipelined ARM. In Proceedings of VLSI93, Grenoble, France, 1993.
[27]
S.B. Furber, J. D. Garside, S. Temple, J. Liu, P. Day, and N.C. Paver. AMULET2e: An asynchronous embedded controller. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1997.
[28]
S.B. Furber and J. Liu. Dynamic logic in four-phase micropipelines. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, March 1996.
[29]
J. D. Garside, S. Temple, and R. Mehra. The AMULET2e cache system. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, March 1996.
[30]
J.D. Garside, S.B. Furber, and S.-H. Chung. AMULET3 revealed. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1999.
[31]
R. Ginosar and R. Kol. Adaptive synchronization. In ICCD, pages 188-189, October 1998.
[32]
D. Harris and M.A. Horowitz. Skew-tolerant domino circuits. IEEE JSSC, 32(11):1702-1711, November 1997.
[33]
M.B. Josephs and J.T. Udding. An overview of D-I algebra. In HICSS, volume I, pages 329-338. IEEE Computer Society Press, January 1993.
[34]
D. Kearney and N.W. Bergmann. Bundled data asynchronous multipliers with data dependant computation times. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1997.
[35]
A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speedindependent circuits. In DAC, pages 56-62. ACM, June 1994.
[36]
D.S. Kung. Hazard-non-increasing gate-level optimization algorithms. In ICCAD, pages 631-634, November 1992.
[37]
L. Lavagno, C.W. Moon, R.K. Brayton, and A. Sangiovanni- Vincentelli. Solving the state assignment problem for signal transition graphs. In DAC, pages 568-572, June 1992.
[38]
L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for synthesis and testing of asynchronous circuits. Kluwer Academic, 1993.
[39]
B. Lin and S. Devadas. Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. In ICCAD, pages 542-549, Nov. 1994.
[40]
A. Marshall, B. Coates, and P. Siegel. The design of an asynchronous communications chip. IEEE Design and Test, 11(2):8-21, Summer 1994.
[41]
A. Martin, S. Burns, T.K. Lee, D. Borkovic, and P. Hazewindus. The design of an asynchronous microprocessor. In Proc. Cal Tech Conference on VLSI, 1989.
[42]
A.J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C.A.R. Hoare, editor, Developments in Concurrency and Communication, pages 1-64. Addison-Wesley, Reading, MA, 1990.
[43]
A.J. Martin. Asynchronous datapaths and the design of an asynchronous adder. Formal Methods in System Design, 1(1):119-137, July 1992.
[44]
A.J. Martin, A. Lines, R. Manohar, M. Nystroem, P. Penzes, R. Southworth, and U. Cummings. The design of an asynchronous MIPS R3000 microprocessor. In Advanced Research in VLSI, September 1997.
[45]
G. Matsubara and N. Ide. A low power zero-overhead selftimed division and square root unit combining a single-rail static circuit with a duM-rail dynamic circuit. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1997.
[46]
T.H.-Y. Meng, R.W. Brodersen, and D.G. Messerschmitt. Automatic synthesis of asynchronous circuits from high-level specifications. IEEE TCAD, 8(11):1185-1205, November 1989.
[47]
S. Moore, P. Robinson, and S. Wilcox. Rotary pipeline processors. IEE Proceedings, Computers and Digital Techniques, 143(5), September 1996.
[48]
C. Myers and T. Meng. Synthesis of Timed Asynchronous Circuits. IEEE TVLSI, 1(2):106-119, June 1993.
[49]
T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, and A. Takamura. TITAC: Design of a quasi-delay-insensitive microprocessor. IEEE Design ~4 Test of Computers, 11(2):50-63, 1994.
[50]
S.M. Nowick. Automatic synthesis of burst-mode asynchronous controllers. Technical report, Stanford University, March 1993. Ph.D. Thesis (available as Stanford Univ. Cptr. Sys. Lab. tech report, CSL-TR-95-686, Dec. 95).
[51]
S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. INTEGRATION, the VLSI journal, 15(3):241-262, October 1993.
[52]
S.M. Nowick and D.L. Dill. Synthesis of asynchronous state machines using a local clock. In ICCD, pages 192-197. IEEE Computer Society Press, October 1991.
[53]
S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE TCAD, 14(8):986-997, August 1995.
[54]
S.M. Nowick, N.K. Jha, and F.-C. Cheng. Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE TCAD, 16(12):1514-1521, December 1997.
[55]
S.M. Nowick, K.Y. Yun, and P.A. Beerel. Speculative completion for the design of high-performance asynchronous dynamic adders. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1997.
[56]
N.C. Paver. The Design and Implementation of an Asynchronous Microprocessor. PhD thesis, University of Manchester, 1994.
[57]
W.F. Richardson and E. Brunvand. Precise exception handling for a self-timed processor. In ICCD, pages 32-37, Los Alamitos, CA, October 1995. IEEE Computer Society Press.
[58]
W.F. Richardson and E. Brunvand. Architectural considerations for a self-timed decoupled processor. IEE Proceedings, Computers and Digital Techniques, 143(5), September 1996.
[59]
W.F. Richardson and E. Brunvand. Fred: An architecture for a self-timed decoupled computer. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, 1996.
[60]
S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev. RAP- PID: an asynchronous instruction length decoder. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, 1999.
[61]
P. Siegel, G. De Micheli, and D. Dill. Technology mapping for generalized fundamentM-mode asynchronous designs. In DAC, pages 61-67. ACM, June 1993.
[62]
R.F. Sproull, I.E. Sutherland, and C.E. Molnar. The counterflow pipeline processor architecture. IEEE Design ~ Test of Computers, 11(3):48-59, Fall 1994.
[63]
I.E. Sutherland. Micropipelines. CACM, 32(6):720-738, June 1989.
[64]
A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, U. Ueno, and T. Nanya. TITAC-2: an asynchronous 32-bit microprocessor based on scMable-delayinsensitive model. In ICCD, pages 288-294, October 1997.
[65]
H. Terada, S. Miyata, and M. Iwata. Ddmps: Self-timed super-pipelined data-driven multimedia processors. Proceedings of the IEEE, 87(2), Feb 1999.
[66]
M. Theobald, S.M. Nowick, and T. Wu. Espresso-HF: a heuristic hazard-free minimizer for two-level logic. In DAC, pages 71-76, June 1996.
[67]
S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley-Interscience, John Wiley ~z Sons, Inc., New York, 1969.
[68]
C.H. van Berkel and R.W.J.J. Saeijs. Compilation of communicating processes into delay-insensitive circuits. In ICCD, pages 157-162. IEEE Computer Society Press, 1988.
[69]
K. van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F. SchMij. Asynchronous Circuits for Low Power: a DCC Error Corrector. IEEE Design ~4 Test, 11(2):22-32, June 1994.
[70]
H. van Gageldonk. An asynchronous low-power 80C51 microcontroller. Technical report, Eindhoven University of Technology, Sept 1998. Ph.D. Thesis.
[71]
H. van Gageldonk, K. van Berkel, A. Peeters, D. Baumann, D. Gloor, and G. Stegmann. An asynchronous low-power 80C51 microcontroller. In IEEE Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, April 1998.
[72]
V.I. Varshavsky, M.A. Kishinevsky, V.B. Marakhovsky, V.A. Peschansky, L.Y. Rosenblum, A.R. Taubin, and B.S. Tzirlin. Self-timed Control of Concurrent Processes. Kluwer Academic Publishers, 1990. Russian edition: 1986.
[73]
T. Williams, N. Patkar, and G. Shen. SPARC64: A 64- b 64-active-instruction out-of-order-execution MCM processor. IEEE JSSC, 30(11):1215-1226, November 1995.
[74]
T.E. Williams. Self-Timed Rings and their Application to Division. PhD thesis, Stanford University, June 1991.
[75]
T.E. Williams and M.A. Horowitz. A zero-overhead selftimed 160ns 54b CMOS divider. IEEE JSSC, 26(11):1651- 1661, November 1991.
[76]
K.Y. Yun, P.A. Beerel, and J. Arceo. High-performance twophase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits. IEE Proceedings, Circuits, Devices and Systems, 143(5):282-288, October 1996.
[77]
K.Y. Yun, P.A. Beerel, V. Vakilotojar, A.E. Dooply, and J. Arceo. The design and verification of a highperformance low-control-overhead asynchronous differential equation solver. IEEE TVLSI, 6(4):643-655, December 1998.
[78]
K.Y. Yun, S. Chakraborty, K.W. James, R. Fairlie- Cuninghame, and R.L. Cruz. A self-timed real-time sorting network. In ICCD, pages 427-434, October 1998.
[79]
K.Y. Yun and D.L. Dill. Automatic synthesis of 3D asynchronous finite-state machines. In ICCAD, Nov. 1992.
[80]
K.Y. Yun and D.L. Dill. Unifying synchronous/asynchronous state machine synthesis. In ICCAD, pages 255-260. IEEE Computer Society Press, November 1993.
[81]
K.Y. Yun and D.L. Dill. A high-performance asynchronous SCSI controller. In ICCD, pages 44-49, Oct. 1995.
[82]
K.Y. Yun and D.L. Dill. Automatic synthesis of extended burst-mode circuits: part I (specification and hazard-free implementations). IEEE TCAD, 18(2):101-117, February 1999.
[83]
K.Y. Yun and D.L. Dill. Automatic synthesis of extended burst-mode circuits: part II (automatic synthesis). IEEE TCAD, 18(2):118-132, February 1999.
[84]
K.Y. Yun and R.P. Donohue. Pausible clocking: A first step toward heterogeneous systems. In ICCD, pages 118-123, October 1996.
[85]
K.Y. Yun and A.E. Dooply. Optimal evaluation clocking of self-resetting domino pipelines. In Proc. of Asia and South Pacific Design Automation Conference, pages 121-124, January 1999.

Cited By

View all
  • (2010)HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous CircuitsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E93.A.2590E93-A:12(2590-2599)Online publication date: 2010
  • (2008)Level-crossing sampling using microprocessor based system2008 International Conference on Signals and Electronic Systems10.1109/ICSES.2008.4673346(19-22)Online publication date: Sep-2008
  • (2007)A Power Aware Design Technique for High Performance Self-Timed Datapaths2007 IEEE Conference on Electron Devices and Solid-State Circuits10.1109/EDSSC.2007.4450259(851-854)Online publication date: Dec-2007
  • Show More Cited By

Index Terms

  1. Practical advances in asynchronous design and in asynchronous/synchronous interfaces

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference
    June 1999
    1000 pages
    ISBN:1581131097
    DOI:10.1145/309847
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 June 1999

    Permissions

    Request permissions for this article.

    Check for updates

    Qualifiers

    • Article

    Conference

    DAC99
    Sponsor:
    DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference
    June 21 - 25, 1999
    Louisiana, New Orleans, USA

    Acceptance Rates

    DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;
    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)80
    • Downloads (Last 6 weeks)17
    Reflects downloads up to 18 Dec 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2010)HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous CircuitsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E93.A.2590E93-A:12(2590-2599)Online publication date: 2010
    • (2008)Level-crossing sampling using microprocessor based system2008 International Conference on Signals and Electronic Systems10.1109/ICSES.2008.4673346(19-22)Online publication date: Sep-2008
    • (2007)A Power Aware Design Technique for High Performance Self-Timed Datapaths2007 IEEE Conference on Electron Devices and Solid-State Circuits10.1109/EDSSC.2007.4450259(851-854)Online publication date: Dec-2007
    • (2003)Using dynamic domino circuits in self-timed systemsProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764874(253-256)Online publication date: 28-Apr-2003
    • (2001)Synthesis of four-phase asynchronous control circuits from pipeline dependency graphsProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370439(425-430)Online publication date: 30-Jan-2001
    • (2000)System-level power optimizationACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/335043.3350445:2(115-192)Online publication date: 1-Apr-2000

    View Options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Login options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media