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Asynchronous Circuits for Low Power: A DCC Error Corrector

Authors:

Ad PeetersAuthors Info & Claims

IEEE Design & Test, Volume 11, Issue 2

Pages 22 - 32

https://doi.org/10.1109/54.282442

Published: 01 April 1994 Publication History

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Abstract

The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on DCC specifications.

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Cited By

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Thonnart YBeigné EValentian AVivet P(2009)Power reduction of asynchronous logic circuits using activity detectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201191217:7(893-906)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011912
Branover AKol RGinosar R(2004)Asynchronous Design By ConversionProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969197Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969197
Garnica OLanchares JHermida R(2002)A New Methodology to Design Low-Power Asynchronous CircuitsProceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation10.5555/646949.712740(108-117)Online publication date: 11-Sep-2002
https://dl.acm.org/doi/10.5555/646949.712740
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Index Terms

Asynchronous Circuits for Low Power: A DCC Error Corrector
1. Hardware

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Published In

IEEE Design & Test Volume 11, Issue 2

April 1994

78 pages

ISSN:0740-7475

Editor:
Ken Wagner
Synopsys Inc., Mountain View, CA

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 April 1994

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Thonnart YBeigné EValentian AVivet P(2009)Power reduction of asynchronous logic circuits using activity detectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201191217:7(893-906)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011912
Branover AKol RGinosar R(2004)Asynchronous Design By ConversionProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969197Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969197
Garnica OLanchares JHermida R(2002)A New Methodology to Design Low-Power Asynchronous CircuitsProceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation10.5555/646949.712740(108-117)Online publication date: 11-Sep-2002
https://dl.acm.org/doi/10.5555/646949.712740
Kessels JPeeters AGoto S(2001)The tangram framework (embedded tutorial)Proceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370339(255-260)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370339
Brunvand ENowick SYun K(1999)Practical advances in asynchronous design and in asynchronous/synchronous interfacesProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309889(104-109)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309889
García TAcosta AMora JRamos JHuertas J(1999)Self-Timed Boundary-Scan Cells for Multi-Chip Module TestJournal of Electronic Testing: Theory and Applications10.1023/A:100838831883515:1-2(115-127)Online publication date: 1-Aug-1999
https://dl.acm.org/doi/10.1023/A%3A1008388318835
Zangi UGinosar RChandrakasan AKiaei S(1998)A low power video processorProceedings of the 1998 international symposium on Low power electronics and design10.1145/280756.280835(136-138)Online publication date: 10-Aug-1998
https://dl.acm.org/doi/10.1145/280756.280835
Plana LNowick S(1998)Architectural optimization for low-power nonpipelined asynchronous systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.6612476:1(56-65)Online publication date: 1-Mar-1998
https://dl.acm.org/doi/10.1109/92.661247
Akella VVaidya NRedinbo G(1998)Asynchronous Comparison-Based Decoders for Delay-Insensitive CodesIEEE Transactions on Computers10.1109/12.70938047:7(802-811)Online publication date: 1-Jul-1998
https://dl.acm.org/doi/10.1109/12.709380
Khoche ABrunvand E(1997)Critical hazard free test generation for asynchronous circuitsProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836342Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836342
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Abstract

References

Cited By

Index Terms

Recommendations

Synthesis of High Performance Low Power Dynamic CMOS Circuits

Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Stored State Asynchronous Sequential Circuits

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