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EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors

Authors:

Hsiang-Yun Cheng,

Narges Shahidi,

Mary Jane Irwin,

Mahmut Kandemir,

Yuan XieAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 12, Issue 2

Article No.: 17, Pages 1 - 22

https://doi.org/10.1145/2756552

Published: 08 July 2015 Publication History

Abstract

Power management for large last-level caches (LLCs) is important in chip multiprocessors (CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads running on CMPs need the entire cache, portions of a large, shared LLC can be disabled to save energy. In this article, we explore different design choices, from circuit-level cache organization to microarchitectural management policies, to propose a low-overhead runtime mechanism for energy reduction in the large, shared LLC. We first introduce a slice-based cache organization that can shut down parts of the shared LLC with minimal circuit overhead. Based on this slice-based organization, part of the shared LLC can be turned off according to the spatial and temporal cache access behavior captured by low-overhead sampling-based hardware. In order to eliminate the performance penalties caused by flushing data before powering off a cache slice, we propose data migration policies to prevent the loss of useful data in the LLC. Results show that our energy-efficient cache design (EECache) provides 14.1% energy savings at only 1.2% performance degradation and consumes negligible hardware overhead compared to prior work.

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Cited By

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Index Terms

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 12, Issue 2

July 2015

410 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2775085

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 08 July 2015

Accepted: 01 April 2015

Revised: 01 January 2015

Received: 01 October 2014

Published in TACO Volume 12, Issue 2

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Cited By

Ravipati DGoel RSanten VAmrouch HPanda P(2024)CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based CachesIEEE Transactions on Computers10.1109/TC.2024.345773473:12(2830-2843)Online publication date: Dec-2024
https://doi.org/10.1109/TC.2024.3457734
Biswas ATyagi A(2023)Huffman Cache Trails2023 IEEE International Symposium on Smart Electronic Systems (iSES)10.1109/iSES58672.2023.00063(277-282)Online publication date: 18-Dec-2023
https://doi.org/10.1109/iSES58672.2023.00063
Ravipati Dvan Santen VSalamin SAmrouch HPanda P(2023)Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPATIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.328510531:9(1280-1293)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3285105
Ge FWang LWu NZhou F(2019)A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPsElectronics10.3390/electronics80606398:6(639)Online publication date: 6-Jun-2019
https://doi.org/10.3390/electronics8060639
Ghaemi SAhmadpour IArdebili MFarbeh H(2019)Sleepy-LRUThe Journal of Supercomputing10.1007/s11227-019-02758-075:7(3945-3974)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s11227-019-02758-0
Asad AOzturk OFathy MJahed-Motlagh M(2017)Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchyMicroprocessors and Microsystems10.1016/j.micpro.2017.03.01151(76-98)Online publication date: Jun-2017
https://doi.org/10.1016/j.micpro.2017.03.011
Cataldo RKorol GFernandes RMatos DMarcon Cde Lima Monteiro DTorres FIndrusiak L(2016)Architectural exploration of last-level caches targeting homogeneous multicore systemsProceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains10.5555/3145862.3145876(1-6)Online publication date: 29-Aug-2016
https://dl.acm.org/doi/10.5555/3145862.3145876
Zhang ZJu LJia ZFanucci LTeich J(2016)Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overheadProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972025(942-947)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972025
Cataldo RKorol GFernandes RMatos DMarcon C(2016)Architectural exploration of Last-Level Caches targeting homogeneous multicore systems2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2016.7724050(1-6)Online publication date: Aug-2016
https://doi.org/10.1109/SBCCI.2016.7724050

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