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10.1109/HPCA.2012.6169036guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs

Published: 25 February 2012 Publication History

Abstract

Intelligently partitioning the last-level cache within a chip multiprocessor can bring significant performance improvements. Resources are given to the applications that can benefit most from them, restricting each core to a number of logical cache ways. However, although overall performance is increased, existing schemes fail to consider energy saving when making their partitioning decisions. This paper presents Cooperative Partitioning, a runtime partitioning scheme that reduces both dynamic and static energy while maintaining high performance. It works by enforcing cached data to be way-aligned, so that a way is owned by a single core at any time. Cores cooperate with each other to migrate ways between themselves after partitioning decisions have been made. Upon access to the cache, a core needs only to consult the ways that it owns to find its data, saving dynamic energy. Unused ways can be power-gated for static energy saving. We evaluate our approach on two-core and four-core systems, showing that we obtain average dynamic and static energy savings of 35% and 25% compared to a fixed partitioning scheme. In addition, Cooperative Partitioning maintains high performance while transferring ways five times faster than an existing state-of-the-art technique.

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  • (2022)CASHT: Contention Analysis in Shared Hierarchies with TheftsACM Transactions on Architecture and Code Optimization10.1145/349453819:1(1-27)Online publication date: 23-Jan-2022
  • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
  • (2018)Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/320266317:3(1-25)Online publication date: 22-May-2018
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  1. Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs

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        cover image Guide Proceedings
        HPCA '12: Proceedings of the 2012 IEEE 18th International Symposium on High-Performance Computer Architecture
        February 2012
        457 pages
        ISBN:9781467308274

        Publisher

        IEEE Computer Society

        United States

        Publication History

        Published: 25 February 2012

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        • (2022)CASHT: Contention Analysis in Shared Hierarchies with TheftsACM Transactions on Architecture and Code Optimization10.1145/349453819:1(1-27)Online publication date: 23-Jan-2022
        • (2019)Reducing Writebacks Through In-Cache DisplacementACM Transactions on Design Automation of Electronic Systems10.1145/328918724:2(1-21)Online publication date: 10-Jan-2019
        • (2018)Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache ManagementACM Transactions on Embedded Computing Systems10.1145/320266317:3(1-25)Online publication date: 22-May-2018
        • (2018)DarkCacheACM Transactions on Architecture and Code Optimization10.1145/318689515:2(1-26)Online publication date: 1-May-2018
        • (2018)Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache PartitioningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.271266637:2(445-457)Online publication date: 1-Feb-2018
        • (2017)A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioningProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130572(800-805)Online publication date: 27-Mar-2017
        • (2017)A Survey of Techniques for Cache Partitioning in Multicore ProcessorsACM Computing Surveys10.1145/306239450:2(1-39)Online publication date: 10-May-2017
        • (2017)Exploring Energy-Efficient Cache Design in Emerging Mobile PlatformsACM Transactions on Design Automation of Electronic Systems10.1145/284394022:4(1-20)Online publication date: 20-Jul-2017
        • (2017)Multi-cache resizing via greedy coordinate descentThe Journal of Supercomputing10.1007/s11227-016-1927-073:6(2402-2429)Online publication date: 1-Jun-2017
        • (2016)Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage LifetimeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.254006924:10(3118-3131)Online publication date: 1-Oct-2016
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