Architectural exploration of last-level caches targeting homogeneous multicore systems
Authors: 
Rodrigo Cataldo, Guilherme Korol, Ramon Fernandes, Debora Matos, César MarconAuthors Info & Claims
Article No.: 14, Pages 1 - 6
Abstract
The Last-Level Cache (LLC) influences the overall system performance and power dissipation in multicore systems significantly. This paper evaluates five LLC architectures targeting execution time, dynamic and static power dissipation, and area consumption. They are measured using the widely adopted PARSEC benchmark suite for parallel shared-memory systems. Employing Gem5 full-system simulator and 32 nm technology characterization of the McPAT framework, this work had two interesting findings: (i) the shared LLC has the overall best performance under the PARSEC parallel workload, even for applications with less than 20% of shared data. (ii) A privately accessed cache can reduce up to 20 times the dynamic power dissipation on 32 nm technology and 25 times the area consumption when compared to shared-accessed caches.
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- Architectural exploration of last-level caches targeting homogeneous multicore systems
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Published In
August 2016
250 pages
ISBN:9781509027361
- General Chair:
- Davies William de Lima Monteiro,
- Program Chairs:
- Frank Sill Torres,
- Leandro Soares Indrusiak
Sponsors
- SBC: Brazilian Computer Society
- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- SBMICRO: Brazilian Microelectronics Society
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IEEE Press
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Published: 29 August 2017
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SBCCI '16
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- SBC
- SIGDA
- SBMICRO
SBCCI '16: 29th Symposium on Integrated Circuits and Systems Design
August 29 - September 3, 2016
Belo Horizonte, Brazil
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Overall Acceptance Rate 133 of 347 submissions, 38%
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