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A workload independent energy reduction strategy for D-NUCA caches

Authors:

Pierfrancesco Foglia,

Manuel ComparettiAuthors Info & Claims

The Journal of Supercomputing, Volume 68, Issue 1

Pages 157 - 182

https://doi.org/10.1007/s11227-013-1033-5

Published: 01 April 2014 Publication History

Abstract

Wire delays and leakage energy consumption are both growing problems in the design of large on chip caches built in deep submicron technologies. D-NUCA caches (Dynamic-Nonuniform Cache Architecture) exploit an aggressive subbanking of the cache and a migration mechanism to speed up frequently accessed data access latency, to limit wire delays effects on performances. Way Adaptable D-NUCA is a leakage power reduction technique specifically suited for D-NUCA caches. It dynamically varies the portion of the powered-on cache area based on the running workload caching needs, but it relies on application dependent parameters that must be evaluated off-line. This limits the effectiveness of Way Adaptable D-NUCA in the general purpose, multiprogrammed environment. In this paper, we propose a new power reduction technique for D-NUCA caches, which still adapts the powered-on cache area to the needs of the running workload, but it does not rely on application-dependent parameters. Results show that our proposal saves around 49 % of total cache energy consumption in a single core environment and 44 % in CMP environment. By adding a timer, it performs similarly to previously proposed techniques to reduce leakage power consumptions, and outperforms them when they are applied in a workload independent manner.

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Cited By

Chakraborty SKapoor H(2017)Performance linked dynamic cache tuningMicroprocessors & Microsystems10.1016/j.micpro.2017.06.01252:C(221-235)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2017.06.012
Chakraborty SDas SKapoor HOssowski S(2016)Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPsProceedings of the 31st Annual ACM Symposium on Applied Computing10.1145/2851613.2851674(1739-1744)Online publication date: 4-Apr-2016
https://dl.acm.org/doi/10.1145/2851613.2851674
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie Y(2015)EECacheACM Transactions on Architecture and Code Optimization10.1145/275655212:2(1-22)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.1145/2756552
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A workload independent energy reduction strategy for D-NUCA caches
1. General and reference
  1. Cross-computing tools and techniques
2. Hardware
  1. Integrated circuits
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Published In

cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 68, Issue 1

April 2014

507 pages

ISSN:0920-8542

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Copyright © Copyright © 2014 Springer Science+Business Media New York.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 April 2014

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Cited By

Chakraborty SKapoor H(2017)Performance linked dynamic cache tuningMicroprocessors & Microsystems10.1016/j.micpro.2017.06.01252:C(221-235)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2017.06.012
Chakraborty SDas SKapoor HOssowski S(2016)Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPsProceedings of the 31st Annual ACM Symposium on Applied Computing10.1145/2851613.2851674(1739-1744)Online publication date: 4-Apr-2016
https://dl.acm.org/doi/10.1145/2851613.2851674
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie Y(2015)EECacheACM Transactions on Architecture and Code Optimization10.1145/275655212:2(1-22)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.1145/2756552
Kapoor HDas SChakraborty SWainwright RCorchado JBechini AHong J(2015)Static energy reduction by performance linked cache capacity management in tiled CMPsProceedings of the 30th Annual ACM Symposium on Applied Computing10.1145/2695664.2695763(1913-1918)Online publication date: 13-Apr-2015
https://dl.acm.org/doi/10.1145/2695664.2695763

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