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ICCAD 2015: Austin, Texas, USA
- Diana Marculescu, Frank Liu:
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015. IEEE 2015, ISBN 978-1-4673-8389-9 - Sai Ma, Debjit Pal
, Rui Jiang, Sandip Ray, Shobha Vasudevan:
Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. 1-8 - Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris
Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion. 9-14 - Sai Zhang, Naresh R. Shanbhag:
Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. 15-21 - Hung-Sheng Chang, Yuan-Hao Chang
A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems. 22-29 - Chien-Chung Ho, Yuan-Hao Chang
Access Pattern Reshaping for eMMC-enabled SSDs. 30-37 - Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. 38-45 - Nikil D. Dutt
Self-Aware Cyber-Physical Systems-on-Chip. 46-50 - Abhishek Koneru, Arunkumar Vijayan, Krishnendu Chakrabarty
Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure. 51-58 - Debashis Banerjee, Shreyas Sen, Abhijit Chatterjee:
Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental Uncertainties. 59-64 - Robert Wille
Formal Methods for Emerging Technologies. 65-70 - Marco Lattuada
Code Transformations Based on Speculative SDC Scheduling. 71-77 - Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang
ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. 78-85 - Enzo Tartaglione
Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs. 86-93 - Andreas Abel, Jan Reineke:
MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines. 94-101 - Stephan Held, Dirk Müller, Daniel Rotter, Vera Traub
Global Routing with Inherent Static Timing Constraints. 102-109 - Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan:
TILA: Timing-Driven Incremental Layer Assignment. 110-117 - Minghua Shen, Guojie Luo:
Accelerate FPGA Routing with Parallel Recursive Partitioning. 118-125 - Hyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim:
Synthesis for Power-Aware Clock Spines. 126-131 - Wei Yan, Fatemeh Tehranipoor, John A. Chandy
A Novel Way to Authenticate Untrusted Integrated Circuits. 132-138 - Md Tanvir Arafin
RRAM Based Lightweight User Authentication. 139-145 - Kai He, Xin Huang, Sheldon X.-D. Tan:
EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs. 146-151 - Lingxiao Wei, Chaosheng Song, Yannan Liu, Jie Zhang, Feng Yuan, Qiang Xu
BoardPUF: Physical Unclonable Functions for Printed Circuit Board Authentication. 152-158 - Vivek De:
Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs. 159-164 - Partha Pratim Pande, Ryan Gary Kim
The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoC. 165-169 - Paul Bogdan, Yuankun Xue:
Mathematical Models and Control Algorithms for Dynamic Optimization of Multicore Platforms: A Complex Dynamics Approach. 170-175 - Muhammad Shafique
Mitigating the Power Density and Temperature Problems in the Nano-Era. 176-177 - Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. 178-185 - Indranil Palit, Qiuwen Lou, Nicholas Acampora, Joseph Nahas, Michael T. Niemier, Xiaobo Sharon Hu
Analytically Modeling Power and Performance of a CNN System. 186-193 - Pai-Yu Chen, Binbin Lin, I-Ting Wang
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. 194-199 - Md Muztoba, Ujjwal Gupta, Tanvir Mustofa, Ümit Y. Ogras
Robust Communication with IoT Devices using Wearable Brain Machine Interfaces. 200-207 - Yan Zhang, Sriram Sankaranarayanan, Benjamin M. Gyori
Simulation-Guided Parameter Synthesis for Chance-Constrained Optimization of Control Systems. 208-215 - John B. Finn, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli:
A Mixed Discrete-Continuous Optimization Scheme for Cyber-Physical System Architecture Exploration. 216-223 - Wei-Ming Chen, Sheng-Wei Cheng, Pi-Cheng Hsiu
A User-Centric CPU-GPU Governing Framework for 3D Games on Mobile Devices. 224-231 - Jason Thong, Nicola Nicolici:
SAT Solving using FPGA-based Heterogeneous Computing. 232-239 - Nauman Ahmed, Vlad Mihai Sima
Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm. 240-246 - Andrew B. Kahng, Farinaz Koushanfar
Evolving EDA Beyond its E-Roots: An Overview. 247-254 - Farinaz Koushanfar
DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives. 255-262 - Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins:
Toward Metrics of Design Automation Research Impact. 263-270 - Miodrag Potkonjak, Deming Chen, Priyank Kalla, Steven P. Levitan:
DA Vision 2015: From Here to Eternity. 271-277 - Jason Cong, Cody Hao Yu:
Impact of Loop Transformations on Software Reliability. 278-285 - Ameneh Golnari, Yakir Vizel, Sharad Malik
Error-Tolerant Processors: Formal Specification and Verification. 286-293 - Deepashree Sengupta, Sachin S. Sapatnekar
FEMTO: Fast Error Analysis in Multipliers through Topological Traversal. 294-299 - Fan Lin, Chun-Kai Hsu, Alberto Giovanni Busetto, Kwang-Ting Cheng
Pairwise Proximity-Based Features for Test Escape Screening. 300-306 - Shengcheng Wang, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty
Defect Clustering-Aware Spare-TSV Allocation for 3D ICs. 307-314 - Yutaka Masuda, Masanori Hashimoto
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. 315-322 - Vito Giovanni Castellana, Marco Minutoli
High Level Synthesis of RDF Queries for Graph Analytics. 323-330 - Skyler Windh
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. 331-336 - Wenjie Che
PUF-Based Authentication. 337-344 - Sandip Ray, Yier Jin
Security Policy Enforcement in Modern SoC Designs. 345-350 - Kun Yang, Domenic Forte
Protecting Endpoint Devices in IoT Supply Chain. 351-356 - Wei Zuo, Warren Kemmerer, Jong Bin Lim, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Kyungtae Han, Deming Chen:
A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration. 357-364 - Karthik Sangaiah, Mark Hempstead, Baris Taskin:
Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling. 365-372 - Asad Khan, Weiqiang Ma, Chris Wolf, Bengt Werner:
Multi-Threaded Simics SystemC Virtual Platform. 373-379 - Jason Cong, Zhenman Fang, Michael Gill, Glenn Reinman:
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration. 380-387 - Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang
Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. 388-395 - Yibo Lin
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. 396-403 - Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization. 404-409 - Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu:
Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly. 410-417 - Soheil Hashemi, R. Iris Bahar
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. 418-425 - Ankur Sharma, David G. Chinnery
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. 426-433 - Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. 434-441 - Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. 442-449 - Hengyang Zhao, Daniel Quach, Shujuan Wang, Hai Wang, Hai-Bao Chen, Xin Li, Sheldon X.-D. Tan:
Learning Based Compact Thermal Modeling for Energy-Efficient Smart Building Management: (invited). 450-456 - Xiaoming Chen, Xin Li, Sheldon X.-D. Tan:
From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance. 457-464 - Tianshu Wei, Bowen Zheng, Qi Zhu
Security Analysis of Proactive Participation of Smart Buildings in Smart Grid. 465-472 - Mehdi Maasoumy, Alberto L. Sangiovanni-Vincentelli:
Buildings to Grid Integration: A Dynamic Contract Approach. 473-478 - Yu-Ming Chang, Yung-Chun Li, Yuan-Hao Chang
On Relaxing Page Program Disturbance over 3D MLC Flash Memory. 479-486 - Rui Wu, Chin-Hui Chen, Cheng Li, Tsung-Ching Huang, Fan Lan, Chong Zhang, Yun Pan, John E. Bowers, Raymond G. Beausoleil, Kwang-Ting Cheng
Variation-Aware Adaptive Tuning for Nanophotonic Interconnects. 487-493 - Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko:
Threshold Logic Synthesis Based on Cut Pruning. 494-499 - Ermao Cai, Diana Marculescu
TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems. 500-507 - Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. 508-513 - Nima Karimpour Darav, Andrew A. Kennings, David T. Westwick
High Performance Global Placement and Legalization Accounting for Fence Regions. 514-519 - Tao Lin, Chris C. N. Chu, Gang Wu:
POLAR 3.0: An Ultrafast Global Placement Engine. 520-527 - Vinicius S. Livramento, Chrystian Guth, Renan Netto, José Luís Almada Güntzel, Luiz C. V. dos Santos
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization. 528-535 - Abhishek Basak, Swarup Bhunia
A Flexible Architecture for Systematic Implementation of SoC Security Policies. 536-543 - Xueyang Wang, Charalambos Konstantinou
ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance Counters. 544-551 - Baolei Mao
Quantifying Timing-Based Information Flow in Cryptographic Hardware. 552-559 - Nicole Fern, Kwang-Ting (Tim) Cheng
Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing. 560-566 - Sooeun Lee, Gunbok Lee, Jae-Yoon Sim, Hong-June Park, Wee Sang Park, Byungsub Kim:
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design. 567-574 - Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia:
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information. 575-582 - Haotian Liu, Xiaoyan Y. Z. Xiong, Kim Batselier
STAVES: Speedy Tensor-Aided Volterra-Based Electronic Simulator. 583-588 - Deniz Kilinç
Simulation of Noise in Neurons and Neuronal Circuits. 589-596 - Shouyi Yin, Pengcheng Zhou, Leibo Liu
Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. 597-604 - Yeseong Kim, Francesco Paterna, Sameer Tilak, Tajana Simunic Rosing:
Smartphone Analysis and Optimization based on User Activity Recognition. 605-612 - Arian Maghazeh, Unmesh D. Bordoloi, Mattias Villani, Petru Eles, Zebo Peng:
Perception-Aware Power Management for Mobile Games via Dynamic Resolution Scaling. 613-620 - Nga Dang, Roberto Valentini
A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems. 621-626 - Xue Lin, Paul Bogdan, Naehyuck Chang, Massoud Pedram:
Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost. 627-634 - Kishwar Ahmed
A Contract Design Approach for Colocation Data Center Demand Response. 635-640 - Tian Qin, Sunil Rana
Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. 641-648 - Yarui Peng
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. 649-655 - Michael Zwerger, Maximilian Neuner, Helmut E. Graeb:
Power-Down Circuit Synthesis for Analog/Mixed-Signal. 656-663 - Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu
Statistical Learning in Chip (SLIC). 664-669 - Kaisheng Ma
Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. 670-675 - Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. 676-681 - Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. 682-689 - Yeseong Kim, Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile Devices. 690-696 - Woo-Cheol Kwon, Li-Shiuan Peh:
A universal ordered NoC design platform for shared-memory MPSoC. 697-704 - Sourav Das, Janardhan Rao Doppa, Daehyun Kim, Partha Pratim Pande, Krishnendu Chakrabarty
Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach. 705-712 - Naval Gupte, Jia Wang:
Transient Noise Bounds using Vectorless Power Grid Verification. 713-720 - Tao Wang, Jinglan Liu, Cheng Zhuo, Yiyu Shi:
1-Bit Compressed Sensing Based Framework for Built-in Resonance Frequency Prediction Using On-Chip Noise Sensors. 721-728 - Hari Cherupalli, John Sartori:
Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions. 729-735 - Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. 736-743 - Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim
A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis. 744-751 - Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. 752-757 - Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar
Optimization of FinFET-based circuits using a dual gate pitch technique. 758-763 - Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao:
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. 764-769 - Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Hardware Accelerator Design for Data Centers. 770-775 - Yada Zhu, Jinjun Xiong
Modern Big Data Analytics for "Old-fashioned" Semiconductor Industry Applications. 776-780 - Jinglan Liu, Da-Cheng Juan, Yiyu Shi:
Effective CAD Research in the Sea of Papers. 781-785 - Yifang Liu:
Dynamically Resilient and Agile Fine-Grained Replication Configuration. 786-793 - Ting-Wei Chiang, Jie-Hong R. Jiang:
Property-Directed Synthesis of Reactive Systems from Safety Specifications. 794-801 - Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin:
Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. 802-807 - Xiaobing Shi, Nicola Nicolici:
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation. 808-815 - Ricardo Ochoa Gallardo, Alan J. Hu, André Ivanov, Maryam S. Mirian:
Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection. 816-823 - Qian Zhang, Ye Tian, Ting Wang, Feng Yuan, Qiang Xu
ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-Decomposition. 824-830 - Francesco Paterna, Tajana Simunic Rosing:
Modeling and Mitigation of Extra-SoC Thermal Coupling Effects and Heat Transfer Variations in Mobile Devices. 831-838 - Onur Sahin, Paul Thomas Varghese, Ayse K. Coskun:
Just Enough is More: Achieving Sustainable Performance in Mobile Devices under Thermal Limitations. 839-846 - Dongwook Lee, Taemin Kim, Kyungtae Han, Yatin Hoskote, Lizy K. John, Andreas Gerstlauer:
Learning-Based Power Modeling of System-Level Black-Box IPs. 847-853 - Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. 854-860 - Chien-Pang Lu, Iris Hui-Ru Jiang, Chin-Hsiung Hsu:
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design. 861-866 - Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. 867-873 - Oliver Keszöcze
A General and Exact Routing Methodology for Digital Microfluidic Biochips. 874-881 - Jin Hu, Greg Schaeffer, Vibhor Garg:
TAU 2015 Contest on Incremental Timing Analysis: Incremental Timing and CPPR Analysis. 882-889 - Pei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, Yu-Ming Yang:
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis. 890-894 - Tsung-Wei Huang, Martin D. F. Wong
OpenTimer: A High-Performance Timing Analysis Tool. 895-902 - Chaitanya Peddawad, Aman Goel
iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal. 903-909 - Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim:
Overview of the 2015 CAD Contest at ICCAD. 910-911 - Arvind Sridhar, Mohamed M. Sabry, David Atienza:
ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network. 912-915 - Chih-Jen Hsu, Chi-An Wu, Wei-Hsun Lin, Kei-Yong Khoo:
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite. 916-920 - Myung-Chul Kim, Jin Hu, Jiajia Li, Natarajan Viswanathan:
ICCAD-2015 CAD Contest in Incremental Timing-driven Placement and Benchmark Suite. 921-926 - Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte
Rebooting Computing and Low-Power Image Recognition Challenge. 927-932
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