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Shantanu Dutt
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- affiliation: University of Illinois at Chicago, Department of Electrical and Computer Engineering, IL, USA
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2020 – today
- 2022
- [c46]Xiuyan Zhang, Shantanu Dutt:
Limiting Interconnect Heating in Power-Driven Physical Synthesis. SLIP 2022: 2:1-2:7 - [e1]Mustafa Badaroglu, Shantanu Dutt:
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022. ACM 2022, ISBN 978-1-4503-9536-6 [contents] - 2021
- [c45]Shantanu Dutt, Xiuyan Zhang, Ouwen Shi:
On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis. ISQED 2021: 355-360
2010 – 2019
- 2019
- [j27]Xiuyan Zhang, Ouwen Shi, Jian Xu, Shantanu Dutt:
A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding. J. Low Power Electron. 15(4): 388-409 (2019) - 2018
- [c44]Shantanu Dutt, Ouwen Shi:
A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. DATE 2018: 31-36 - 2017
- [c43]Shantanu Dutt, Ouwen Shi:
Power-delay product based resource library construction for effective power optimization in HLS. ISQED 2017: 229-236 - 2016
- [j26]Ouwen Shi, Shantanu Dutt:
Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis. J. Low Power Electron. 12(4): 295-308 (2016) - 2015
- [c42]Enzo Tartaglione
, Shantanu Dutt:
Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs. ICCAD 2015: 86-93 - 2014
- [j25]Shantanu Dutt, Dinesh P. Mehta
New Algorithmic Techniques for Complex EDA Problems. VLSI Design 2014: 134946:1-134946:2 (2014) - 2013
- [j24]Huan Ren, Shantanu Dutt:
Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm. VLSI Design 2013: 474601:1-474601:15 (2013) - 2011
- [j23]Huan Ren, Shantanu Dutt:
Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous Vdd, Vth Assignments, Gate Sizing, and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 746-759 (2011) - [j22]Shantanu Dutt, Huan Ren:
Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1277-1290 (2011) - [j21]Huan Ren, Shantanu Dutt:
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1291-1304 (2011) - 2010
- [c41]Shantanu Dutt, Huan Ren:
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. ICCAD 2010: 570-577
2000 – 2009
- 2009
- [j20]Shantanu Dutt, Li Li:
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. ACM Trans. Reconfigurable Technol. Syst. 2(1): 6:1-6:36 (2009) - [c40]Shantanu Dutt, Yang Dai, Huan Ren, Joel Fontanarosa:
Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach. BICoB 2009: 211-223 - 2008
- [j19]Shantanu Dutt, Vinay Verma, Vishal Suthar:
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 309-326 (2008) - [c39]Huan Ren, Shantanu Dutt:
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. ICCAD 2008: 93-100 - 2007
- [j18]Nihar R. Mahapatra, Shantanu Dutt:
An efficient delay-optimal distributed termination detection algorithm. J. Parallel Distributed Comput. 67(10): 1047-1066 (2007) - [c38]Huan Ren, Shantanu Dutt:
Constraint satisfaction in incremental placement with application to performance optimization under power constraints. ICCD 2007: 251-258 - 2006
- [c37]Shantanu Dutt, Hasan Arslan:
Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. DATE 2006: 768-773 - [c36]Vishal Suthar, Shantanu Dutt:
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. DATE 2006: 1165-1170 - [c35]Federico Rota, Shantanu Dutt, Sahithi Krishna:
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. DFT 2006: 507-515 - [c34]Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar:
A network-flow approach to timing-driven incremental placement for ASICs. ICCAD 2006: 375-382 - [c33]Vishal Suthar, Shantanu Dutt:
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. VTS 2006: 36-43 - 2005
- [c32]Vishal Suthar, Shantanu Dutt:
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ACM Great Lakes Symposium on VLSI 2005: 78-83 - 2004
- [j17]Nihar R. Mahapatra, Shantanu Dutt:
Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. Parallel Comput. 30(5-6): 867-881 (2004) - [c31]Vinay Verma, Shantanu Dutt, Vishal Suthar:
Efficient on-line testing of FPGAs with provable diagnosabilities. DAC 2004: 498-503 - [c30]Vinay Verma, Shantanu Dutt:
Roving testing using new built-in-self-tester designs for FPGAs. FPGA 2004: 257 - [c29]Hasan Arslan, Shantanu Dutt:
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. ACM Great Lakes Symposium on VLSI 2004: 208-213 - [c28]Hasan Arslan, Shantanu Dutt:
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. ICCD 2004: 86-92 - 2003
- [c27]Hasan Arslan, Shantanu Dutt:
ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. ICCD 2003: 350- - 2002
- [j16]Shantanu Dutt, Wenyong Deng:
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. ACM Trans. Design Autom. Electr. Syst. 7(1): 91-121 (2002) - [j15]Shantanu Dutt, Vinay Verma, Hasan Arslan:
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 664-693 (2002) - [c26]Ke Zhong, Shantanu Dutt:
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. DAC 2002: 854-859 - 2001
- [j14]Nihar R. Mahapatra, Shantanu Dutt:
Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. J. Parallel Distributed Comput. 61(10): 1391-1411 (2001) - [c25]Vinay Verma, Shantanu Dutt:
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. ICCAD 2001: 144- - 2000
- [j13]Nihar R. Mahapatra, Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. Int. J. Found. Comput. Sci. 11(2): 231-246 (2000) - [j12]Shantanu Dutt, Wenyong Deng:
Probability-based approaches to VLSI circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 534-549 (2000) - [c24]Ke Zhong, Shantanu Dutt:
Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. ICCAD 2000: 254-259
1990 – 1999
- 1999
- [j11]Shantanu Dutt, Hasan Arslan, Halim Theny:
Partitioning using second-order information and stochastic-gainfunctions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 421-435 (1999) - [c23]Nihar R. Mahapatra, Shantanu Dutt:
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. FTCS 1999: 122-129 - [c22]Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger:
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. ICCAD 1999: 173-177 - 1998
- [j10]Fran Hanchek, Shantanu Dutt:
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Trans. Computers 47(1): 15-33 (1998) - [c21]Nihar R. Mahapatra, Shantanu Dutt:
Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. IPPS/SPDP 1998: 796-800 - [c20]Shantanu Dutt, Halim Theny:
Partitioning using second-order information and stochastic-gain functions. ISPD 1998: 112-117 - 1997
- [j9]Shantanu Dutt, Nihar R. Mahapatra:
Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. IEEE Trans. Computers 46(9): 997-1015 (1997) - [j8]Nihar R. Mahapatra, Shantanu Dutt:
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. IEEE Trans. Parallel Distributed Syst. 8(7): 738-756 (1997) - [j7]Shantanu Dutt, Fran Hanchek:
REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 34-56 (1997) - [c19]Shantanu Dutt, Halim Theny:
Partitioning around roadblocks: tackling constraints with intermediate relaxations. ICCAD 1997: 350-355 - 1996
- [j6]Shantanu Dutt, Fikri T. Assaad:
Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations. IEEE Trans. Computers 45(4): 408-424 (1996) - [c18]Shantanu Dutt, Wenyong Deng:
A Probability-Based Approach to VLSI Circuit Partitioning. DAC 1996: 100-105 - [c17]Nihar R. Mahapatra, Shantanu Dutt:
Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. FTCS 1996: 272-281 - [c16]Shantanu Dutt, Wenyong Deng:
VLSI circuit partitioning by cluster-removal using iterative improvement techniques. ICCAD 1996: 194-200 - [c15]Fran Hancheck, Shantanu Dutt:
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. ICCD 1996: 326-331 - [c14]Shantanu Dutt, Nam Trinh:
Are There Advantages to High-Dimension Architectures? Analysis of k-ary n-Cubes for the Class of Parallel Divide-and-Conquer Algorithms. International Conference on Supercomputing 1996: 398-406 - [c13]Nihar R. Mahapatra, Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. IPPS 1996: 881-885 - [c12]Fran Hanchek, Shantanu Dutt:
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. VLSI Design 1996: 225-229 - 1995
- [c11]Shantanu Dutt, Nihar R. Mahapatra:
Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. FTCS 1995: 320-329 - 1994
- [j5]Shantanu Dutt, Nihar R. Mahapatra:
Scalable Load Balancing Strategies for Parallel A* Algorithms. J. Parallel Distributed Comput. 22(3): 488-505 (1994) - [c10]Nihar R. Mahapatra, Shantanu Dutt:
New Anticipatory Load Balancing Strategies for Parallel A* Algorithms. Parallel Processing of Discrete Optimization Problems 1994: 197-232 - 1993
- [c9]Shantanu Dutt:
New faster Kernighan-Lin-type graph-partitioning algorithms. ICCAD 1993: 370-377 - [c8]Shantanu Dutt, Nihar R. Mahapatra:
Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. IPPS 1993: 797-803 - [c7]Nihar R. Mahapatra, Shantanu Dutt:
Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. SPDP 1993: 290-297 - [c6]Shantanu Dutt:
Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors. SPDP 1993: 762-770 - 1992
- [j4]Shantanu Dutt, John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. IEEE Trans. Computers 41(5): 588-598 (1992) - [c5]Fikri T. Assaad, Shantanu Dutt:
More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication. FTCS 1992: 430-439 - 1991
- [j3]Shantanu Dutt, John P. Hayes:
Designing Fault-Tolerant System Using Automorphisms. J. Parallel Distributed Comput. 12(3): 249-268 (1991) - [j2]Shantanu Dutt, John P. Hayes:
Subcube Allocation in Hypercube Computers. IEEE Trans. Computers 40(3): 341-352 (1991) - [c4]Shantanu Dutt, John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. FTCS 1991: 292-299 - 1990
- [b1]Shantanu Dutt:
Designing and reconfiguring fault-tolerant multiprocessor systems. University of Michigan, USA, 1990 - [j1]Shantanu Dutt, John P. Hayes:
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. IEEE Trans. Computers 39(4): 490-503 (1990)
1980 – 1989
- 1989
- [c3]Shantanu Dutt, John P. Hayes:
An automorphic approach to the design of fault-tolerant multiprocessors. FTCS 1989: 496-503 - 1988
- [c2]Shantanu Dutt, John P. Hayes:
On allocating subcubes in a hypercube multiprocessor. C³P 1988: 801-810 - [c1]Shantanu Dutt, John P. Hayes:
Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures. FTCS 1988: 328-333
Coauthor Index
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