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Yarui Peng
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2020 – today
- 2022
- [j5]Chixiao Chen
, Jieming Yin, Yarui Peng
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39(6): 99-109 (2022) - 2021
- [c14]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design. ACM Great Lakes Symposium on VLSI 2021: 135-140 - [c13]Imam Al Razi, Quang Le, H. Alan Mantooth, Yarui Peng:
Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation. ICCAD 2021: 1-8 - [c12]M. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization. VLSI-DAT 2021: 1-4 - 2020
- [c11]M. D. Arafat Kabir, Yarui Peng
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools. ASP-DAC 2020: 351-356 - [c10]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design. ICCAD 2020: 3:1-3:8 - [c9]M. D. Arafat Kabir, Yarui Peng:
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study. SoCC 2020: 277-282
2010 – 2019
- 2017
- [j4]Moongon Jung
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2109-2117 (2017) - 2016
- [j3]Taigon Song, Chang Liu, Yarui Peng
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1636-1648 (2016) - 2015
- [j2]Yarui Peng
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1964-1976 (2015) - [c8]Yarui Peng
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. DAC 2015: 91:1-91:6 - [c7]Yarui Peng
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD 2015: 649-655 - 2014
- [j1]Yarui Peng
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1900-1913 (2014) - [c6]Moongon Jung, Taigon Song, Yang Wan, Yarui Peng
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. DAC 2014: 4:1-4:6 - [c5]Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. DAC 2014: 28:1-28:6 - 2013
- [c4]Taigon Song, Chang Liu, Yarui Peng
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. DAC 2013: 180:1-180:7 - [c3]Yarui Peng
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD 2013: 281-288 - [c2]Sandeep Kumar Samal, Yarui Peng
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs. ISLPED 2013: 21-26
2000 – 2009
- 2004
- [c1]Yarui Peng, Wenhua Hou:
A Framework of Total Performance Improvement and Transaction Cost-driven Business Process Outsourcing Strategy. PACIS 2004: 76
Coauthor Index
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