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Hsiang-Pang Li
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2020 – today
- 2024
- [c23]Shi-Zhe Lin
, Yun-Chih Chen
LUTIN: Efficient Neural Network Inference with Table Lookup. ISLPED 2024: 1-6 - 2023
- [c22]Chieh-Lin Tsai, Chun-Feng Wu, Yuan-Hao Chang, Han-Wen Hu, Yung-Chun Lee, Hsiang-Pang Li, Tei-Wei Kuo:
A digital 3D TCAM accelerator for the inference phase of Random Forest. DAC 2023: 1-6 - 2022
- [j7]Wei-Ting Lin, Hsiang-Yun Cheng
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21(3): 24:1-24:29 (2022) - [c21]Han-Wen Hu
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices. ISSCC 2022: 138-140 - [c20]Han-Wen Hu, Wei-Chen Wang, Yuan-Hao Chang, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Ming Huang, Chong-Ying Lee, Tzu-Hsiang Su, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Chung Kuang Chen, Han-Sung Chen, Hsiang-Pang Li, Tei-Wei Kuo, Meng-Fan Chang, Keh-Chung Wang, Chun-Hsiung Hung, Chih-Yuan Lu:
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration. MICRO 2022: 763-783 - [c19]Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li:
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA 2022: 1-7
2010 – 2019
- 2019
- [c18]Tzu-Hsien Yang, Hsiang-Yun Cheng
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA 2019: 236-249 - 2018
- [c17]Meng-Yao Lin, Hsiang-Yun Cheng
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD 2018: 31 - [c16]Tse-Yuan Wang, Che-Wei Tsao, Yuan-Hao Chang
A partnership-based approach to minimize the maximal response time of flash-memory storage systems. SAC 2018: 616-619 - 2017
- [j6]Yu-Ming Huang, Hsie-Chia Chang, Hsiang-Pang Li:
Re-Polarization Processing in Extended Polar Codes. IEICE Trans. Commun. 100-B(10): 1765-1777 (2017) - [j5]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, SangBum Kim
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications. IEEE J. Solid State Circuits 52(1): 218-228 (2017) - [j4]Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. ACM Trans. Design Autom. Electr. Syst. 22(2): 27:1-27:22 (2017) - 2016
- [j3]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. IEEE Trans. Computers 65(4): 1090-1102 (2016) - [j2]Yu-Ming Chang, Yuan-Hao Chang
Disturbance Relaxation for 3D Flash Memory. IEEE Trans. Computers 65(5): 1467-1483 (2016) - [c15]Yu-Ming Chang, Yung-Chun Li, Ping-Hsien Lin, Hsiang-Pang Li, Yuan-Hao Chang
Realizing erase-free SLC flash memory with rewritable programming design. CODES+ISSS 2016: 7:1-7:10 - [c14]Hung-Sheng Chang, Yuan-Hao Chang
A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory. CODES+ISSS 2016: 20:1-20:10 - [c13]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. ISSCC 2016: 134-135 - [c12]Hung-Sheng Chang, Yuan-Hao Chang
Pattern-aware write-back strategy to minimize energy consumption of PCM-based storage systems. NVMSA 2016: 1-6 - 2015
- [j1]Hung-Sheng Chang, Yuan-Hao Chang
Marching-Based Wear-Leveling for PCM-Based Storage Systems. ACM Trans. Design Autom. Electr. Syst. 20(2): 25:1-25:22 (2015) - [c11]Chun-Ta Lin, Yuan-Hao Chang
How to improve the space utilization of dedup-based PCM storage devices? CODES+ISSS 2015: 11-20 - [c10]Yu-Ming Chang, Yuan-Hao Chang
Achieving SLC performance with MLC flash memory. DAC 2015: 192:1-192:6 - [c9]Hung-Sheng Chang, Yuan-Hao Chang
A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems. ICCAD 2015: 22-29 - [c8]Yu-Ming Chang, Yung-Chun Li, Yuan-Hao Chang
On Relaxing Page Program Disturbance over 3D MLC Flash Memory. ICCAD 2015: 479-486 - [c7]Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang
Fine-grained write scheduling for PCM performance improvement under write power budget. ISLPED 2015: 19-24 - [c6]Ye-Jyun Lin, Chia-Lin Yang
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. NVMSA 2015: 1-6 - 2014
- [c5]Bing-Jing Chang, Yuan-Hao Chang
A PCM translation layer for integrated memory and storage management. CODES+ISSS 2014: 6:1-6:10 - [c4]Yu-Ming Chang, Yuan-Hao Chang, Jian-Jia Chen
On Trading Wear-leveling with Heal-leveling. DAC 2014: 83:1-83:6 - [c3]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. DAC 2014: 145:1-145:6 - 2013
- [c2]Yu-Ming Chang, Yuan-Hao Chang
A disturb-alleviation scheme for 3D flash memory. ICCAD 2013: 421-428 - [c1]Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang:
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. ISSCC 2013: 222-223
Coauthor Index
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