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Eduardo Quiñones
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2020 – today
- 2024
- [j20]Adrian Munera, Sara Royuela, Michael Pressler, Harald Mackamul, Dirk Ziegenbein, Eduardo Quiñones:
Fine-grained adaptive parallelism for automotive systems through AMALTHEA and OpenMP. J. Syst. Archit. 146: 103034 (2024) - [j19]Mohammad Samadi
, Sara Royuela, Luís Miguel Pinho
Time-predictable task-to-thread mapping in multi-core processors. J. Syst. Archit. 148: 103068 (2024) - [c90]Chenle Yu
Enhancing Heterogeneous Computing Through OpenMP and GPU Graph. ICPP 2024: 534-543 - [c89]Cyril Cetre, Chenle Yu, Sara Royuela, Rémi Barrere, Eduardo Quiñones, Damien Gratadour:
Event-Based OpenMP Tasks for Time-Sensitive GPU-Accelerated Systems. IWOMP 2024: 31-45 - 2023
- [j18]Chenle Yu
Taskgraph: A Low Contention OpenMP Tasking Framework. IEEE Trans. Parallel Distributed Syst. 34(8): 2325-2336 (2023) - [c88]Elli Kartsakli, Jordi Pérez-Romero, Nikolaos G. Bartzoudis
An Evolutionary Edge Computing Architecture for the Beyond 5G Era. CAMAD 2023: 61-67 - [c87]Elli Kartsakli
AI-Powered Edge Computing Evolution for Beyond 5G Communication Networks. EuCNC/6G Summit 2023: 478-483 - [c86]Tiago Carvalho
Framework for the Analysis and Configuration of Real-Time OpenMP Applications. INDIN 2023: 1-8 - [c85]Alessio Medaglini
Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles. MECO 2023: 1-7 - 2022
- [c84]Mohammad Samadi Gharajeh
Heuristic-based Task-to-Thread Mapping in Multi-Core Processors. ETFA 2022: 1-4 - [p3]Maria A. Serrano, César A. Marín, Anna Queralt, Cristovao Cordeiro, Marco Gonzalez, Luís Miguel Pinho
An Elastic Software Architecture for Extreme-Scale Big Data Analytics. Technologies and Applications for Big Data Value 2022: 89-110 - [p2]Marco Aldinucci, David Atienza, Federico Bolelli
The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures. Technologies and Applications for Big Data Value 2022: 183-202 - [p1]Maria A. Serrano, Erez Hadad, Roberto Cavicchioli, Rut Palmero
Distributed Big Data Analytics in a Smart City. Technologies and Applications for Big Data Value 2022: 475-496 - [i1]Chenle Yu, Sara Royuela, Eduardo Quiñones:
Taskgraph: A Low Contention OpenMP Tasking Framework. CoRR abs/2212.04771 (2022) - 2021
- [c83]Chenle Yu
A Low Overhead Tasking Model for OpenMP. Euro-Par Workshops 2021: 520-524 - [c82]Chenle Yu
Enhancing OpenMP Tasking Model: Performance and Portability. IWOMP 2021: 35-49 - 2020
- [j17]Sara Royuela, Luís Miguel Pinho
Enabling Ada and OpenMP runtimes interoperability through template-based execution. J. Syst. Archit. 105: 101702 (2020) - [c81]Adrian Munera, Sara Royuela, Eduardo Quiñones:
Towards a Qualifiable OpenMP Framework for Embedded Systems. DATE 2020: 903-908 - [c80]Adrian Munera, Sara Royuela, Germán Llort
Experiences on the characterization of parallel applications in embedded systems with Extrae/Paraver. ICPP 2020: 53:1-53:11 - [c79]Eduardo Quiñones, Sara Royuela, Claudio Scordino
The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization. ISORC 2020: 201-206 - [c78]José Flich
Distributed Training on a Highly Heterogeneous HPC System. SAMOS 2020: 359-370 - [c77]Chenle Yu
OpenMP to CUDA graphs: a compiler-based transformation to enhance the programmability of NVIDIA devices. SCOPES 2020: 42-47 - [c76]Adrian Munera, Sara Royuela, Roger Ferrer, Raúl Peñacoba Veigas
Static Analysis to Enhance Programmability and Performance in OmpSs-2. ISC Workshops 2020: 19-33
2010 – 2019
- 2019
- [c75]Sara Royuela, Maria A. Serrano, Marta Garcia-Gasulla
The Cooperative Parallel: A Discussion About Run-Time Schedulers for Nested Parallelism. IWOMP 2019: 171-185 - 2018
- [c74]Sara Royuela
Safe Parallelism: Compiler Analysis Techniques for Ada and OpenMP. Ada-Europe 2018: 141-157 - [c73]Maria A. Serrano, Eduardo Quiñones:
Response-time analysis of DAG tasks supporting heterogeneous computing. DAC 2018: 125:1-125:6 - [c72]Sara Royuela
Converging safety and high-performance domains: Integrating OpenMP into Ada. DATE 2018: 1021-1026 - [c71]Maria A. Serrano, Sara Royuela
Towards an OpenMP Specification for Critical Real-Time Systems. IWOMP 2018: 143-159 - [c70]Eduardo Quiñones, Marko Bertogna, Erez Hadad, Ana Juan Ferrer, Luca Chiantore, Alfredo Reboa:
Big Data Analytics for Smart Cities: The H2020 CLASS Project. SYSTOR 2018: 130 - 2017
- [j16]Milos Panic
Adapting TDMA arbitration for measurement-based probabilistic timing analysis. Microprocess. Microsystems 52: 188-201 (2017) - [j15]Gabriel Fernandez, Javier Jalle, Jaume Abella
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. IEEE Trans. Computers 66(4): 586-600 (2017) - [c69]Sara Royuela
OpenMP Tasking Model for Ada: Safety and Correctness. Ada-Europe 2017: 184-200 - [c68]Alessandra Melani, Maria A. Serrano, Marko Bertogna, Isabella Cerutti, Eduardo Quiñones, Giorgio C. Buttazzo:
A static scheduling approach to enable safety-critical OpenMP applications. ASP-DAC 2017: 659-665 - [c67]Mikel Fernández
Probabilistic timing analysis on time-randomized platforms for the space domain. DATE 2017: 738-739 - [c66]Maria A. Serrano, Alessandra Melani, Sebastian Kehr, Marko Bertogna, Eduardo Quiñones:
An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling. ISORC 2017: 193-202 - [c65]Sara Royuela
A Functional Safety OpenMP ^* for Critical Real-Time Embedded Systems. IWOMP 2017: 231-245 - [c64]Sebastian Kehr, Eduardo Quiñones, Dominik Langen, Bert Böddeker, Günter Schäfer:
Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications. RTAS 2017: 343-352 - 2016
- [j14]Leonidas Kosmidis
Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocess. Microsystems 47: 287-302 (2016) - [j13]Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore. ACM Trans. Embed. Comput. Syst. 15(3): 53:1-53:27 (2016) - [c63]Roberto Vargas, Sara Royuela
A lightweight OpenMP4 run-time for embedded systems. ASP-DAC 2016: 43-49 - [c62]Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schäfer:
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications. DATE 2016: 25-30 - [c61]Maria A. Serrano, Alessandra Melani, Marko Bertogna, Eduardo Quiñones:
Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions. DATE 2016: 1066-1071 - [c60]Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla:
Improving performance guarantees in wormhole mesh NoC designs. DATE 2016: 1485-1488 - [c59]Francisco J. Cazorla, Jaume Abella
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. DSD 2016: 276-285 - [c58]Mladen Slijepcevic
pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems. DSD 2016: 404-412 - [c57]Leonidas Kosmidis
TASA: toolchain-agnostic static software randomisation for critical real-time systems. ICCAD 2016: 59 - [c56]Pedro Benedicte
A confidence assessment of WCET estimates for software time randomized caches. INDIN 2016: 90-97 - [c55]Milos Panic
Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. RTAS 2016: 267-278 - [c54]Pedro Benedicte
Modelling the confidence of timing analysis for time randomised caches. SIES 2016: 141-148 - [c53]Javier Jalle, Eduardo Quiñones, Jaume Abella
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. SIES 2016: 272-279 - [c52]Leonidas Kosmidis
Measurement-Based Timing Analysis of the AURIX Caches. WCET 2016: 9:1-9:11 - [e1]Marko Bertogna
Reliable Software Technologies - Ada-Europe 2016 - 21st Ada-Europe International Conference on Reliable Software Technologies, Pisa, Italy, June 13-17, 2016, Proceedings. Lecture Notes in Computer Science 9695, Springer 2016, ISBN 978-3-319-39082-6 [contents] - 2015
- [j12]Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems. Leibniz Trans. Embed. Syst. 2(1): 01:1-01:10 (2015) - [j11]Luís Miguel Pinho, Vincent Nélis, Patrick Meumeu Yomsi, Eduardo Quiñones, Marko Bertogna, Paolo Burgio, Andrea Marongiu, Claudio Scordino, Paolo Gai, Michele Ramponi, Michal Mardiak:
P-SOCRATES: A parallel software framework for time-critical many-core systems. Microprocess. Microsystems 39(8): 1190-1203 (2015) - [c51]Suzana Milutinovic
Speeding up Static Probabilistic Timing Analysis. ARCS 2015: 236-247 - [c50]Maria A. Serrano
Timing characterization of OpenMP4 tasking model. CASES 2015: 157-166 - [c49]Sebastian Kehr, Eduardo Quiñones
Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication. DAC 2015: 42:1-42:6 - [c48]Suzana Milutinovic
PACO: fast average-performance estimation for time-randomized caches. DAC 2015: 124:1-124:6 - [c47]Gabriel Fernandez, Javier Jalle, Jaume Abella
Increasing confidence on measurement-based contention bounds for real-time round-robin buses. DAC 2015: 125:1-125:6 - [c46]Gabriel Fernandez, Javier Jalle, Jaume Abella
Resource usage templates and signatures for COTS multicore processors. DAC 2015: 155:1-155:6 - [c45]Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoë R. Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla:
Timing analysis of an avionics case study on complex hardware/software platforms. DATE 2015: 397-402 - [c44]Roberto Vargas, Eduardo Quiñones, Andrea Marongiu:
OpenMP and timing predictability: a possible union? DATE 2015: 617-620 - [c43]Milos Panic
Enabling TDMA Arbitration in the Context of MBPTA. DSD 2015: 462-469 - [c42]Milos Panic
CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. DSD 2015: 685-692 - [c41]Gabriel Fernandez, Jaume Abella
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. ISORC 2015: 208-217 - [c40]Gabriel Fernandez, Jaume Abella
Introduction to partial time composability for COTS multicores. SAC 2015: 1955-1956 - [c39]Jaume Abella
WCET analysis methods: Pitfalls and challenges on their trustworthiness. SIES 2015: 39-48 - 2014
- [j10]Mladen Slijepcevic
Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments. IEEE Micro 34(6): 8-19 (2014) - [j9]Leonidas Kosmidis
Efficient Cache Designs for Probabilistically Analysable Real-Time Systems. IEEE Trans. Computers 63(12): 2998-3011 (2014) - [c38]Milos Panic
RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores. CODES+ISSS 2014: 29:1-29:10 - [c37]Leonidas Kosmidis
Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware. DAC 2014: 22:1-22:6 - [c36]Mladen Slijepcevic
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems. DAC 2014: 198:1-198:6 - [c35]Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Bus designs for time-probabilistic multicore processors. DATE 2014: 1-6 - [c34]Luís Miguel Pinho
P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems. DSD 2014: 214-221 - [c33]Leonidas Kosmidis
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. DSD 2014: 401-410 - [c32]Jaume Abella
Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. ECRTS 2014: 255-265 - [c31]Jaume Abella
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. ECRTS 2014: 266-275 - [c30]Leonidas Kosmidis
PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis. ECRTS 2014: 276-287 - [c29]Milos Panic
Parallel many-core avionics systems. EMSOFT 2014: 26:1-26:10 - [c28]Javier Jalle, Jaume Abella
AHRB: A high-performance time-composable AMBA AHB bus. RTAS 2014: 225-236 - [c27]Javier Jalle, Eduardo Quiñones
A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. RTSS 2014: 207-217 - [c26]Gabriel Fernandez, Jaume Abella
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art. WCET 2014: 31-42 - [c25]Vincent Nélis
The Challenge of Time-Predictability in Modern Many-Core Architectures. WCET 2014: 63-72 - 2013
- [j8]Marco Paolieri, Eduardo Quiñones
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions. ACM Trans. Embed. Comput. Syst. 12(1s): 64:1-64:26 (2013) - [j7]Francisco J. Cazorla
PROARTIS: Probabilistically Analyzable Real-Time Systems. ACM Trans. Embed. Comput. Syst. 12(2s): 94:1-94:26 (2013) - [j6]Marco Paolieri, Jörg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones
A hard real-time capable multi-core SMT processor. ACM Trans. Embed. Comput. Syst. 12(3): 79:1-79:26 (2013) - [c24]Sylvain Girbal
On the convergence of mainstream and mission-critical markets. DAC 2013: 185:1-185:10 - [c23]Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
A cache design for probabilistically analysable real-time systems. DATE 2013: 513-518 - [c22]Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger
Probabilistic timing analysis on conventional cache designs. DATE 2013: 603-606 - [c21]Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. DSD 2013: 363-370 - [c20]Mladen Slijepcevic
DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis. ECRTS 2013: 237-248 - [c19]Leonidas Kosmidis
Achieving timing composability with measurement-based probabilistic timing analysis. ISORC 2013: 1-8 - [c18]Milos Panic
On-chip ring network designs for hard-real time systems. RTNS 2013: 23-32 - [c17]Leonidas Kosmidis
Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems. RTSS 2013: 360-371 - [c16]Javier Jalle, Jaume Abella
Deconstructing bus access control policies for Real-Time multicores. SIES 2013: 31-38 - [c15]Franck Wartel, Leonidas Kosmidis
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. SIES 2013: 241-248 - [c14]Francisco J. Cazorla
Upper-bounding Program Execution Time with Extreme Value Theory. WCET 2013: 64-76 - [c13]Leonidas Kosmidis
Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources. WCET 2013: 97-108 - 2012
- [j5]Petar Radojkovic
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM Trans. Archit. Code Optim. 8(4): 34:1-34:25 (2012) - [c12]Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. ECRTS 2012: 91-101 - [c11]Mikel Fernández
Assessing the suitability of the NGMP multi-core processor in the space domain. EMSOFT 2012: 175-184 - 2011
- [j4]Eduardo Quiñones, Jaume Abella
Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems. SIGBED Rev. 8(3): 32-35 (2011) - [c10]Jaume Abella
RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106 - [c9]Jaume Abella
RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30 - [c8]Jaume Abella
Towards improved survivability in safety-critical systems. IOLTS 2011: 240-245 - [c7]Marco Paolieri, Eduardo Quiñones
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks. ISORC 2011: 233-240 - [c6]Marco Paolieri, Eduardo Quiñones
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2011: 280-290 - 2010
- [j3]Theo Ungerer, Francisco J. Cazorla
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. IEEE Micro 30(5): 66-75 (2010) - [j2]Eduardo Quiñones
Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum. IEEE Trans. Computers 59(12): 1598-1610 (2010)
2000 – 2009
- 2009
- [j1]Marco Paolieri, Eduardo Quiñones
An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embed. Syst. Lett. 1(4): 86-90 (2009) - [c5]Eduardo Quiñones
Using Randomized Caches in Probabilistic Real-Time Systems. ECRTS 2009: 129-138 - [c4]Marco Paolieri, Eduardo Quiñones
Hardware support for WCET analysis of hard real-time multicore systems. ISCA 2009: 57-68 - 2008
- [b1]Eduardo Quiñones:
Predicated execution and register windows for out-of-order processors. Polytechnic University of Catalonia, Spain, 2008 - 2007
- [c3]Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Early Register Release for Out-of-Order Processors with RegisterWindows. PACT 2007: 225-234 - [c2]Eduardo Quiñones
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. HPCA 2007: 75-84 - 2006
- [c1]Eduardo Quiñones, Joan-Manuel Parcerisa
Selective predicate prediction for out-of-order processors. ICS 2006: 46-54
Coauthor Index
[j16] [j15] [c67] [j14] [j13] [c62] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [j12] [c51] [c48] [c47] [c46] [c45] [c43] [c42] [c41] [c40] [c39] [j10] [j9] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j7] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [j4] [c10] [c9] [c8]
[j16] [j15] [c67] [j14] [j13] [c62] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [j12] [c51] [c48] [c47] [c46] [c45] [c43] [c42] [c41] [c40] [c39] [j10] [j9] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j8] [j7] [j6] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j5] [c12] [c11] [j4] [c10] [c9] [c8] [c7] [c6] [j3] [j1] [c5] [c4]
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