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2020 – today
- 2024
- [c48]Georgia Antoniou, Haris Volos, Yiannakis Sazeides:
Taming Performance Variability caused by Client-Side Hardware Configuration. IISWC 2024: 94-107 - [i6]Georgia Antoniou, Haris Volos, Yiannakis Sazeides:
Taming Performance Variability caused by Client-Side Hardware Configuration. CoRR abs/2410.11554 (2024) - 2022
- [j19]Yiannakis Sazeides
, Arkady Bramnik, Ron Gabor, Ramon Canal
A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays. IEEE Trans. Emerg. Top. Comput. 10(2): 524-536 (2022) - [j18]Panagiota Nikolaou
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study. IEEE Trans. Sustain. Comput. 7(2): 334-345 (2022) - [c47]Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael:
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. DFT 2022: 1-7 - [c46]Jawad Haj-Yahya, Jeremie S. Kim, Abdullah Giray Yaglikçi, Jisung Park
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors. HPCA 2022: 1170-1183 - [c45]Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. MICRO 2022: 799-814 - [c44]Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. MICRO 2022: 835-850 - [c43]Georgia Antoniou, Haris Volos, Davide B. Bartolini
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. MICRO 2022: 851-867 - [i5]Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides:
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. CoRR abs/2203.02550 (2022) - [i4]Georgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet, Yiannakis Sazeides, Jawad Haj-Yahya:
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. CoRR abs/2204.10466 (2022) - [i3]Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael:
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. CoRR abs/2206.11566 (2022) - 2021
- [j17]Alex Gendler, Ernest Knoll, Yiannakis Sazeides
I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling. IEEE Micro 41(5): 76-84 (2021) - [j16]Zacharias Hadjilambrou
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers 70(9): 1338-1349 (2021) - [c42]Ramon Canal, Yiannakis Sazeides, Arkady Bramnik:
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. DATE 2021: 711-716 - [i2]Jawad Haj-Yahya, Jeremie S. Kim, Abdullah Giray Yaglikçi, Jisung Park, Efraim Rotem, Yanos Sazeides, Onur Mutlu:
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors. CoRR abs/2112.11587 (2021) - 2020
- [c41]Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). DFT 2020: 1-4 - [c40]Jawad Haj-Yahya, Yanos Sazeides, Mohammed Alser, Efraim Rotem, Onur Mutlu:
Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices. HPCA 2020: 623-636 - [c39]Georgia Antoniou, Zacharias Hadjilambrou, Yiannakis Sazeides:
Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application. ISPASS 2020: 231-240 - [c38]Panagiota Nikolaou, Yiannakis Sazeides:
Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters. ISPASS 2020: 296-305
2010 – 2019
- 2019
- [j15]Zacharias Hadjilambrou, Marios Kleanthous, Georgia Antoniou, Antoni Portero
Comprehensive Characterization of an Open Source Document Search Engine. ACM Trans. Archit. Code Optim. 16(2): 19:1-19:21 (2019) - [c37]Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. DATE 2019: 812-817 - [c36]Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides:
GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS 2019: 1-10 - 2018
- [j14]Zacharias Hadjilambrou
Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. 17(1): 68-71 (2018) - [c35]Georgios Karakonstantis, Konstantinos Tovletoglou
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE 2018: 1099-1104 - [c34]Konstantinos Tovletoglou
Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops 2018: 6-9 - [c33]Alex Gendler, Arkady Bramnik, Ariel Szapiro, Yiannakis Sazeides:
Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag. HPCA 2018: 571-582 - [c32]Arkady Bramnik, Yiannakis Sazeides:
To Detect or to Correct? IOLTS 2018: 35-38 - [c31]Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO 2018: 573-585 - [c30]Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos
Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH 2018: 1-6 - 2017
- [j13]Georgios Karakonstantis, Dimitrios S. Nikolopoulos
Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer 50(12): 78-81 (2017) - [j12]Davide Zoni
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. 104: 130-145 (2017) - [c29]Nikolaos Zompakis
HARPA: Tackling physically induced performance variability. DATE 2017: 97-102 - [i1]Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavrík, Vít Vondrák:
A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application. CoRR abs/1702.07748 (2017) - 2016
- [j11]Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos
Toward Multi-Layer Holistic Evaluation of System Designs. IEEE Comput. Archit. Lett. 15(1): 58-61 (2016) - [j10]Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. 13(2): 22:1-22:26 (2016) - [c28]Dimitrios Rodopoulos, Philippe Roussel, Francky Catthoor, Yiannakis Sazeides, Dimitrios Soudris:
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point. ERMAVSS@DATE 2016: 13-16 - [c27]Damien Hardy, Isabelle Puaut, Yiannakis Sazeides:
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. DATE 2016: 91-96 - 2015
- [c26]Zacharias Hadjilambrou, Marios Kleanthous, Yanos Sazeides:
Characterization and analysis of a web search benchmark. ISPASS 2015: 328-337 - [c25]Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Marios Kleanthous:
Modeling the implications of DRAM failures and protection techniques on datacenter TCO. MICRO 2015: 572-584 - [c24]Dimitrios Rodopoulos, Simone Corbetta, Giuseppe Massari
HARPA: Solutions for dependable performance under physically induced performance variability. SAMOS 2015: 270-277 - 2013
- [j9]Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian
Modeling the impact of permanent faults in caches. ACM Trans. Archit. Code Optim. 10(4): 29:1-29:23 (2013) - [c23]Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji:
Memory array protection: check on read or check on write? DATE 2013: 214-219 - [c22]Damien Hardy, Marios Kleanthous, Isidoros Sideris, Ali G. Saidi, Emre Ozer, Yiannakis Sazeides:
An analytical framework for estimating TCO and exploring data center design space. ISPASS 2013: 54-63 - [c21]Yiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. MICRO 2013: 160-171 - 2012
- [j8]Boris Grot
Optimizing Data-Center TCO with Scale-Out Processors. IEEE Micro 32(5): 52-63 (2012) - [c20]Dragomir Milojevic
Thermal characterization of cloud workloads on a power-efficient server-on-chip. ICCD 2012: 175-182 - [c19]Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides:
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. MICRO 2012: 48-59 - [c18]Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures. MICRO 2012: 60-71 - 2011
- [j7]Marios Kleanthous, Yiannakis Sazeides:
CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches. ACM Trans. Archit. Code Optim. 8(3): 11:1-11:27 (2011) - [j6]Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous:
Improving Branch Prediction by Considering Affectors and Affectees Correlations. Trans. High Perform. Embed. Archit. Compil. 3: 69-88 (2011) - [c17]Jaume Abella
RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106 - [c16]Jaume Abella
RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30 - [c15]Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón
An analytical model for the calculation of the Expected Miss Ratio in faulty caches. IOLTS 2011: 252-257 - [c14]Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer:
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. ISLPED 2011: 181-186 - 2010
- [c13]Pierre Michaud
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers 2010: 237-246 - [c12]Marios Kleanthous, Yiannakis Sazeides, Marios D. Dikaiakos:
Extrinsic and Intrinsic Text Cloning. ISCA Workshops 2010: 324-340 - [c11]Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet:
Performance-effective operation below Vcc-min. ISPASS 2010: 223-234
2000 – 2009
- 2008
- [c10]Marios Kleanthous, Yiannakis Sazeides:
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. DATE 2008: 1426-1431 - [c9]Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous:
The Significance of Affectors and Affectees Correlations for Branch Prediction. HiPEAC 2008: 243-257 - 2007
- [j5]Pierre Michaud
A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. 4(2): 9 (2007) - 2005
- [j4]Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen
The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. IEEE Comput. Archit. Lett. 4(1): 1 (2005) - [j3]Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud
Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News 33(4): 80-91 (2005) - 2003
- [j2]Yiannakis Sazeides:
Instruction-Isomorphism in Program Execution. J. Instr. Level Parallelism 5 (2003) - [c8]Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen:
Selecting long atomic traces for high coverage. ICS 2003: 2-11 - 2002
- [c7]Yiannakis Sazeides:
Modeling Value Speculation. HPCA 2002: 211-222 - [c6]André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides:
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA 2002: 295-306 - 2001
- [c5]Yiannakis Sazeides, Toni Juan:
How to compare the performance of two SMT microarchitectures. ISPASS 2001: 180-183
1990 – 1999
- 1999
- [j1]Yiannakis Sazeides, James E. Smith:
Limits of Data Value Predictability. Int. J. Parallel Program. 27(4): 229-256 (1999) - 1998
- [c4]Yiannakis Sazeides, James E. Smith:
Modeling Program Predictability. ISCA 1998: 73-84 - 1997
- [c3]Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith:
Trace Processors. MICRO 1997: 138-148 - [c2]Yiannakis Sazeides, James E. Smith:
The Predictability of Data Values. MICRO 1997: 248-258 - 1996
- [c1]Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith:
The Performance Potential of Data Dependence Speculation & Collapsing. MICRO 1996: 238-247
Coauthor Index
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