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Hardware support for WCET analysis of hard real-time multicore systems

Published: 20 June 2009 Publication History

Abstract

The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent a good design solution for such systems due to their high performance, low cost and power consumption characteristics. However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when accessing shared hardware resources. In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time analizability for the hard real-time tasks so that they can meet their deadlines. Moreover our architecture proposal provides high-performance for the non hard real-time tasks.

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        cover image ACM Conferences
        ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture
        June 2009
        510 pages
        ISBN:9781605585260
        DOI:10.1145/1555754
        • cover image ACM SIGARCH Computer Architecture News
          ACM SIGARCH Computer Architecture News  Volume 37, Issue 3
          June 2009
          495 pages
          ISSN:0163-5964
          DOI:10.1145/1555815
          Issue’s Table of Contents
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Publication History

        Published: 20 June 2009

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        Author Tags

        1. analyzability
        2. cache partitioning
        3. hard real-time
        4. interconnection network
        5. multicore
        6. real-time embedded systems
        7. wcet

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        • (2024)Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+2024 27th Euromicro Conference on Digital System Design (DSD)10.1109/DSD64264.2024.00045(282-290)Online publication date: 28-Aug-2024
        • (2024)Access Interval Prediction by Partial Matching for Tightly Coupled Memory SystemsInternational Journal of Parallel Programming10.1007/s10766-024-00764-152:1-2(3-19)Online publication date: 1-Apr-2024
        • (2023)Compiler-Directed Constant Execution Time on Flat Memory Systems2023 IEEE 26th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC58943.2023.00019(64-75)Online publication date: May-2023
        • (2022) PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time SystemsACM Transactions on Embedded Computing Systems10.1145/355697522:1(1-27)Online publication date: 29-Oct-2022
        • (2022)Improving the Configuration of the Predictable ACDC Data Cache for Real-Time SystemsIEEE Access10.1109/ACCESS.2022.323006810(132708-132724)Online publication date: 2022
        • (2022)Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration schemeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102345122:COnline publication date: 1-Jan-2022
        • (2022)Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory SystemsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-15074-6_6(90-100)Online publication date: 3-Jul-2022
        • (2021)Addressing Multi-core Timing Interference using Co-Runner Locking2021 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS52674.2021.00017(54-67)Online publication date: Dec-2021
        • (2020)Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time SystemsIEEE Transactions on Computers10.1109/TC.2020.3037747(1-1)Online publication date: 2020
        • (2020)Enforcing Deadlines for Skeleton-based Parallel Programming2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.000-7(188-199)Online publication date: Apr-2020
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