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Resource usage templates and signatures for COTS multicore processors

Authors:

Gabriel Fernandez,

Eduardo Quiñones,

Tullio Vardanega,

Francisco J. CazorlaAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 155, Pages 1 - 6

https://doi.org/10.1145/2744769.2744901

Published: 07 June 2015 Publication History

Abstract

Upper bounding the execution time of tasks running on multicore processors is a hard challenge. This is especially so with commercial-off-the-shelf (COTS) hardware that conceals its internal operation. The main difficulty stems from the contention effects on access to hardware shared resources (e.g., buses) which cause task's timing behavior to depend on the load that co-runner tasks place on them. This dependence reduces time composability and constrains incremental verification. In this paper we introduce the concepts of resource-usage signatures and templates, to abstract the potential contention caused and incurred by tasks running on a multicore. We propose an approach that employs resource-usage signatures and templates to enable the analysis of individual tasks largely in isolation, with low integration costs, producing execution time estimates per task that are easily composable throughout the whole system integration process. We evaluate the proposal on a 4-core NGMP-like multicore architecture.

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Cited By

Yarza IAgirre IMugarza INitsche GUven POrbegozo J(2023)Towards a Contract-Based Definition of Update-Compatibility – Modelling Safety Integration Criteria2023 IEEE 26th International Conference on Intelligent Transportation Systems (ITSC)10.1109/ITSC57777.2023.10422590(710-717)Online publication date: 24-Sep-2023
https://doi.org/10.1109/ITSC57777.2023.10422590
Díaz EMezzetti EKosmidis LAbella JCazorla F(2018)Modelling multicore contention on the AURIX TC27xProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196077(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196077
Mezzetti EKosmidis LAbella JCazorla F(2018)High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&VIEEE Micro10.1109/MM.2018.11213023538:1(56-65)Online publication date: Jan-2018
https://doi.org/10.1109/MM.2018.112130235
Show More Cited By

Index Terms

Resource usage templates and signatures for COTS multicore processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware
  1. Hardware validation
  2. Integrated circuits

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Published In

cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2015

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Research-article

Funding Sources

Ministerio de Economía y Competitividad
European Union's Horizon 2020
European Space Agency
European Cooperation in Science and Technology
Ministerio de Ciencia e Innovación

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DAC '15

Sponsor:

SIGDA

DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Yarza IAgirre IMugarza INitsche GUven POrbegozo J(2023)Towards a Contract-Based Definition of Update-Compatibility – Modelling Safety Integration Criteria2023 IEEE 26th International Conference on Intelligent Transportation Systems (ITSC)10.1109/ITSC57777.2023.10422590(710-717)Online publication date: 24-Sep-2023
https://doi.org/10.1109/ITSC57777.2023.10422590
Díaz EMezzetti EKosmidis LAbella JCazorla F(2018)Modelling multicore contention on the AURIX TC27xProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196077(1-6)Online publication date: 24-Jun-2018
https://dl.acm.org/doi/10.1145/3195970.3196077
Mezzetti EKosmidis LAbella JCazorla F(2018)High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&VIEEE Micro10.1109/MM.2018.11213023538:1(56-65)Online publication date: Jan-2018
https://doi.org/10.1109/MM.2018.112130235
Agirre IAbella JAzkarate-Askasua MCazorla F(2017)On the tailoring of CAST-32A certification guidance to real COTS multicore architectures2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)10.1109/SIES.2017.7993376(1-8)Online publication date: Jun-2017
https://doi.org/10.1109/SIES.2017.7993376
Abella JCazorla F(2017)Harsh computing in the space domainRugged Embedded Systems10.1016/B978-0-12-802459-1.00009-9(267-293)Online publication date: 2017
https://doi.org/10.1016/B978-0-12-802459-1.00009-9
Díaz EFernández MKosmidis LMezzetti EHernandez CAbella JCazorla F(2017)MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter BoundingReliable Software Technologies – Ada-Europe 201710.1007/978-3-319-60588-3_7(102-118)Online publication date: 30-May-2017
https://doi.org/10.1007/978-3-319-60588-3_7
Compagnin DVardanega T(2016)An automated framework for the timing analysis of applications for an automotive multicore processor2016 IEEE 21st International Conference on Emerging Technologies and Factory Automation (ETFA)10.1109/ETFA.2016.7733570(1-8)Online publication date: Sep-2016
https://doi.org/10.1109/ETFA.2016.7733570
Nélis VYomsi PPinho L(2015)Methodologies for the WCET Analysis of Parallel Applications on Many-Core ArchitecturesProceedings of the 2015 Euromicro Conference on Digital System Design10.1109/DSD.2015.105(748-755)Online publication date: 26-Aug-2015
https://dl.acm.org/doi/10.1109/DSD.2015.105

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