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WO2020147689A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2020147689A1
WO2020147689A1 PCT/CN2020/071815 CN2020071815W WO2020147689A1 WO 2020147689 A1 WO2020147689 A1 WO 2020147689A1 CN 2020071815 W CN2020071815 W CN 2020071815W WO 2020147689 A1 WO2020147689 A1 WO 2020147689A1
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WO
WIPO (PCT)
Prior art keywords
pull
transistor
node
voltage
circuit
Prior art date
Application number
PCT/CN2020/071815
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English (en)
French (fr)
Inventor
蒲巡
吴君辉
郭建东
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/051,722 priority Critical patent/US20210241708A1/en
Publication of WO2020147689A1 publication Critical patent/WO2020147689A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • Each stage (ie shift register) of the GOA circuit is electrically connected to a row of gate lines. It is configured to output a gate scanning signal to the gate line, thereby realizing progressive scanning (driving) of a plurality of gate lines in the display device.
  • a shift register which includes a pull-up node, an output control sub-circuit, a first energy storage sub-circuit, and an output sub-circuit.
  • the output control sub-circuit is coupled to the pull-up node, the first clock signal terminal, and the first energy storage sub-circuit; the output control sub-circuit is configured to set the voltage at the pull-up node Under the control of, the first clock signal received at the first clock signal terminal is transmitted to the first energy storage sub-circuit.
  • the first energy storage sub-circuit is coupled to the pull-up node and the output control sub-circuit; the first energy storage sub-circuit is configured to store the voltage of the pull-up node, and in the first Under the action of a clock signal, the voltage of the pull-up node is raised.
  • the output sub-circuit is coupled to the pull-up node and the signal output terminal; the output sub-circuit is configured to increase the voltage of the pull-up node under the control of the voltage of the pull-up node Output to the signal output terminal.
  • the output control sub-circuit includes a first transistor, the control electrode of the first transistor is coupled to the pull-up node, and the first electrode of the first transistor is connected to the first clock signal.
  • the second electrode of the first transistor is coupled to the first energy storage sub-circuit.
  • the first energy storage sub-circuit includes a first capacitor, a first terminal of the first capacitor is coupled to the pull-up node, and a second terminal of the first capacitor is connected to a second terminal of the first transistor. Coupling.
  • the output sub-circuit includes a second transistor, a control electrode of the second transistor is coupled to the pull-up node, a first electrode of the second transistor is coupled to the pull-up node, and the second transistor The second pole of is coupled to the signal output terminal.
  • the shift register further includes a pull-down sub-circuit; the pull-down sub-circuit is coupled to the second clock signal terminal, the signal output terminal, and the first voltage terminal, and is configured to respond to the The second clock signal received at the clock signal terminal transmits the first voltage signal received at the first voltage terminal to the signal output terminal.
  • the pull-down sub-circuit includes a third transistor, the control electrode of the third transistor is coupled to the second clock signal terminal, and the first electrode of the third transistor is connected to the first voltage The second electrode of the third transistor is coupled to the signal output terminal.
  • the shift register further includes a second energy storage sub-circuit; the second energy storage sub-circuit is coupled between the first energy storage sub-circuit and the signal output terminal, and is configured to During the process of outputting the raised voltage of the pull-up node to the signal output terminal, the voltage of the pull-up node is kept stable.
  • the second energy storage sub-circuit includes a second capacitor, and the first end of the second capacitor is coupled to the signal output end; the first energy storage sub-circuit includes a first capacitor In the case of, the second end of the second capacitor is coupled to the second end of the first capacitor.
  • the shift register further includes an input sub-circuit and a reset sub-circuit.
  • the input sub-circuit is coupled to a signal input terminal, a second voltage terminal, and the pull-up node, and is configured to receive an input signal at the second voltage terminal in response to an input signal received at the signal input terminal The second voltage signal is transmitted to the pull-up node.
  • the reset sub-circuit is coupled to a reset signal terminal, a first voltage terminal, and the pull-up node, and is configured to receive a reset signal at the first voltage terminal in response to a reset signal received at the reset signal terminal The first voltage signal is transmitted to the pull-up node.
  • the input sub-circuit includes a fourth transistor, the control electrode of the fourth transistor is coupled to the signal input terminal, and the first electrode of the fourth transistor is coupled to the second voltage terminal. Connected, the second electrode of the fourth transistor is coupled to the pull-up node.
  • the reset sub-circuit includes a fifth transistor, a control electrode of the fifth transistor is coupled to the reset signal terminal, a first electrode of the fifth transistor is coupled to the first voltage terminal, and the fifth transistor The second pole of the transistor is coupled to the pull-up node.
  • the shift register further includes: a pull-down node, a node control sub-circuit, a first noise reduction sub-circuit, and a second noise reduction sub-circuit.
  • the node control sub-circuit is coupled to the second voltage terminal, the pull-up node, the first voltage terminal, and the pull-down node.
  • the node control sub-circuit is configured to transmit the first voltage signal received at the first voltage terminal in response to the voltage of the pull-up node and the second voltage signal received at the second voltage terminal To the pull-down node; and, in response to the voltage of the pull-up node and the second voltage signal received at the second voltage terminal, transmitting the second voltage signal received at the second voltage terminal to The drop-down node.
  • the first noise reduction sub-circuit is coupled to the pull-up node, the pull-down node, and the first voltage terminal, and is configured to control the voltage at the first voltage under the control of the pull-down node.
  • the first voltage signal received at the terminal is transmitted to the pull-up node.
  • the second noise reduction sub-circuit is coupled to the pull-down node, the first voltage terminal, and the signal output terminal, and is configured to, under the control of the voltage of the pull-down node, switch to the first voltage
  • the first voltage signal received at the terminal is transmitted to the signal output terminal.
  • the node control sub-circuit includes a sixth transistor and a seventh transistor; the control electrode of the sixth transistor is coupled to the second voltage terminal, and the first electrode of the sixth transistor is connected to the second voltage terminal.
  • the second voltage terminal is coupled, the second pole of the sixth transistor is coupled to the pull-down node; the control pole of the seventh transistor is coupled to the pull-up node, and the first pole of the seventh transistor is coupled to the pull-up node.
  • the electrode is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the pull-down node.
  • the first noise reduction sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the pull-down node, a first electrode of the eighth transistor is coupled to the second voltage terminal, and the The second electrode of the eighth transistor is coupled to the pull-up node.
  • the second noise reduction sub-circuit includes a ninth transistor, a control electrode of the ninth transistor is coupled to the pull-down node, a first electrode of the ninth transistor is coupled to the second voltage terminal, and the The second electrode of the ninth transistor is coupled to the signal output terminal.
  • the size of the seventh transistor is larger than the size of the sixth transistor.
  • the shift register includes: a pull-up node, an output control sub-circuit, a first energy storage sub-circuit, an output sub-circuit, a pull-down sub-circuit, an input sub-circuit, a reset sub-circuit, a pull-down node, and a node control sub-circuit A first noise reduction sub-circuit and a second noise reduction sub-circuit; wherein the output control sub-circuit includes a first transistor, the first energy storage sub-circuit includes a first capacitor, and the output sub-circuit includes a second transistor , The pull-down sub-circuit includes a third sub-circuit, the input sub-circuit includes a fourth transistor, the reset sub-circuit includes a fifth transistor, the node control sub-circuit includes a sixth transistor and a seventh transistor, the first A noise reduction sub-circuit includes an eighth transistor, and the second noise reduction sub-circuit includes a ninth transistor.
  • the control electrode of the first transistor is coupled to the pull-up node, the first electrode of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the first clock signal terminal.
  • the second end of a capacitor is coupled.
  • the first terminal of the first capacitor is coupled to the pull-up node, and is also coupled to the control electrode of the first transistor.
  • the control electrode of the second transistor is coupled to the pull-up node, the first electrode of the second transistor is coupled to the pull-up node, and the second electrode of the second transistor is coupled to the signal output terminal Coupling.
  • the control electrode of the third transistor is coupled to the second clock signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the signal output terminal.
  • the control electrode of the fourth transistor is coupled to the signal input terminal, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the pull-up node.
  • the control electrode of the fifth transistor is coupled to the reset signal terminal, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the pull-up node Pick up.
  • the control electrode of the sixth transistor is coupled to the second voltage terminal, the first electrode of the sixth transistor is coupled to the second voltage terminal, and the second electrode of the sixth transistor is coupled to the pull-down terminal. Node coupling.
  • the control electrode of the seventh transistor is coupled to the pull-up node, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the pull-down node Coupling.
  • the control electrode of the eighth transistor is coupled to the pull-down node, the first electrode of the eighth transistor is coupled to the first voltage terminal, and the second electrode of the eighth transistor is coupled to the pull-up node Coupling.
  • the control electrode of the ninth transistor is coupled to the pull-down node, the first electrode of the ninth transistor is coupled to the first voltage terminal, and the second stage of the ninth transistor is coupled to the signal output terminal Coupling.
  • the shift register further includes: a second capacitor; the first terminal of the second capacitor is coupled to the second electrode of the first transistor, and the second terminal of the second capacitor is connected to the The signal output terminal is coupled.
  • a gate driving circuit which includes at least two cascaded shift registers as described in the above aspect.
  • the signal input terminal of the first stage shift register is coupled to the start signal terminal. Except for the first stage of shift register, the signal input terminal of any stage of shift register is coupled to the signal output terminal of the previous stage of shift register of the stage of shift register. Except for the last stage of shift register, the reset signal terminal of any stage of shift register is coupled to the signal output terminal of the next stage of shift register of this stage.
  • the reset signal terminal of the last-stage shift register is coupled to a separately provided signal terminal for outputting a reset signal, or is coupled to the start signal terminal.
  • a display device including the gate driving circuit as described above.
  • a method for driving a shift register which is applied to the above-mentioned shift register.
  • the driving method includes: one frame period includes a charging phase and an output phase.
  • the charging phase includes: under the voltage control of the pull-up node, the output control sub-circuit is turned on, and the first clock signal received at the first clock signal terminal is transmitted to the first energy storage sub-circuit.
  • the first energy storage sub-circuit stores the voltage of the pull-up node.
  • the output stage includes: under the voltage control of the pull-up node, the output control sub-circuit is turned on, and the first clock signal is transmitted to the first energy storage sub-circuit.
  • the first energy storage sub-circuit boosts the voltage of the pull-up node in response to the first clock signal.
  • the output sub-circuit transmits the raised voltage of the pull-up node to the signal output terminal under the control of the voltage of the pull-up node.
  • the charging phase further includes: under the control of the second clock signal transmitted from the second clock signal terminal, the pull-down sub-circuit is turned on , Transmitting the first voltage signal received at the first voltage terminal to the signal output terminal.
  • the output stage further includes: the voltage of the second energy storage sub-circuit at the raised pull-up node During the process of outputting to the signal output terminal, the voltage of the pull-up node is kept stable.
  • the charging The stage also includes: under the control of the input signal transmitted by the signal input terminal, the input sub-circuit is turned on, and the second voltage signal received at the second voltage terminal is transmitted to the pull-up node.
  • the node control sub-circuit transmits the first voltage signal received at the first voltage terminal to the Drop down the node.
  • the driving method further includes a reset stage after the output stage, the reset stage includes: under the control of the reset signal transmitted by the reset signal terminal, the reset sub-circuit is turned on, and the reset sub-circuit is switched on at the first voltage terminal.
  • the first voltage signal received at is output to the pull-up node.
  • the node control sub-circuit transmits the second voltage signal received at the second voltage terminal to the Drop down the node. Under the control of the voltage of the pull-down node, the first noise reduction sub-circuit is turned on, and the first voltage signal received at the first voltage terminal is transmitted to the pull-up node.
  • the second noise reduction sub-circuit Under the control of the voltage of the pull-down node, the second noise reduction sub-circuit is turned on, and the first voltage signal received at the first voltage terminal is transmitted to the signal output terminal. Under the control of the second clock signal transmitted from the second clock signal terminal, the pull-down sub-circuit is turned on and transmits the first voltage signal received at the first voltage terminal to the signal output terminal.
  • the driving method further includes: a noise reduction stage located after the reset stage and before the next frame period, the noise reduction stage includes: under the control of the voltage of the pull-down node, the second noise reduction sub-circuit Keep on, and transmit the first voltage signal received at the first voltage terminal to the signal output terminal.
  • Figure 1 is a structural diagram of a shift register according to the related art
  • Fig. 2 is a structural diagram of a shift register according to some embodiments of the present disclosure
  • Fig. 3 is another structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 4 is another structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 5 is another structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a timing diagram of a driving method of a shift register according to some embodiments of the present disclosure.
  • FIG. 8 is a flowchart of a driving method of a shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a timing diagram of another driving method of the shift register according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "plurality” is two or more.
  • Coupled and “connected” and their extensions may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components do not directly contact each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • the GOA circuit includes a plurality of shift registers, and each stage (ie, shift register) of the GOA circuit is electrically connected to a row of gate lines, that is, the number of shift registers included in the GOA circuit and the resolution of the display device Equivalently, each shift register is configured to provide a scanning signal to the gate line electrically connected to it, so as to realize the progressive scanning (driving) of the multiple gate lines in the display panel.
  • Each gate line corresponds to a row of sub-pixels. Under the control of the scan signal, the switching transistor in the pixel drive circuit corresponding to each sub-pixel in the row of sub-pixels is turned on to receive the data signal transmitted by the data line. Sub-pixel charging.
  • the shift register includes a pull-up node PU and a pull-down node PD.
  • the potentials of the pull-up node PU and the pull-down node PD are opposite.
  • the potential of the node PD controls the signal output terminal Output to output the scanning signal and stop outputting the scanning signal.
  • the potential of the pull-up node PU is high, and the potential of the pull-down node PD is low.
  • the transistor M3 is turned on under the control of the pull-up node PU, and will be at the clock signal terminal CLK.
  • the received clock signal clk (the level of the clock signal clk is high at this time) is output as a scanning signal through the signal output terminal Output.
  • the high level (for example, 22V) of the clock signal clk is used as a scan signal and output to the signal output terminal Output.
  • the charging time for each row of sub-pixels is getting less and less, which may cause insufficient sub-pixel charging.
  • the high level of the clock signal clk can be increased (for example, the original 22V can be increased to 30V) to solve the problem, but this , Will greatly increase the power consumption of the display device, which is inconsistent with the current concept of low power consumption.
  • the shift register includes: a pull-up node PU, The output control sub-circuit 101, the first energy storage sub-circuit 201 and the output sub-circuit 102.
  • the output control sub-circuit 101 is coupled to the pull-up node PU, the first clock signal terminal CK1 and the first energy storage sub-circuit 201.
  • the output control sub-circuit 101 is configured to transmit the first clock signal ck1 received at the first clock signal terminal CK1 to the first energy storage sub-circuit 201 under the control of the voltage of the pull-up node.
  • the first clock signal terminal CK1 is configured to receive the first clock signal ck1, and input the first clock signal ck1 into the output control sub-circuit 101.
  • the first energy storage sub-circuit 201 is coupled to the pull-up node PU and the output control sub-circuit 101.
  • the first energy storage sub-circuit 201 is configured to store the voltage of the pull-up node PU and raise the voltage of the pull-up node PU under the action of the first clock signal ck1.
  • the output sub-circuit 102 is coupled to the pull-up node PU and the signal output terminal Output; the output sub-circuit 102 is configured to output the raised voltage of the pull-up node PU to the signal output under the control of the voltage of the pull-up node PU End Output.
  • the output sub-circuit 102 is coupled to the pull-up node PU and the signal output terminal Output, so that the output sub-circuit 102 controls the voltage of the pull-up node PU.
  • the voltage of the pull-up node PU can be directly output to the signal output terminal Output, so the voltage output to the signal output terminal Output is the voltage of the pull-up node PU, and the voltage output to the signal output terminal Output in the related technology is The high level of the clock signal clk.
  • the low level of the first clock signal ck1 is transmitted to the first energy storage sub-circuit 201 through the output control sub-circuit 101 during the charging phase, and passes through the first storage sub-circuit 201.
  • the energy sub-circuit 201 stores the voltage of the pull-up node PU, and transmits the high level of the first clock signal ck1 to the first energy storage sub-circuit 201 through the output control sub-circuit 101 during the output stage, so that the first energy storage sub-circuit 201 is Under the action of the first clock signal ck1, the voltage of the pull-up node PU is raised, and through the output sub-circuit 102, the voltage of the raised pull-up node PU is output to the signal output terminal Output, which is the pull-up node PU to be raised.
  • the voltage as the scan signal.
  • the high-level signal of the clock signal terminal CK1 is used as the scan signal to be output through the signal output terminal Output, (exemplarily, the high-level signal (scan signal) of the clock signal terminal is different from that of the present disclosure.
  • the voltage of the pull-up node PU in the charging phase in the provided shift register is basically the same), the shift register in the present disclosure can raise the voltage of the pull-up node PU under the action of the first clock signal ck1, and The voltage of the raised pull-up node PU is output as a scan signal to the signal output terminal Output.
  • the voltage of the scan signal output by the shift register provided by some embodiments of the present disclosure is higher than that of the shift register in the related art
  • the voltage of the output scan signal (the high level of the clock signal).
  • the voltage of the scan signal can be increased without increasing the high level of the clock signal clk and without increasing the power consumption of the display device, thereby increasing the charging rate of the sub-pixels, which is more conducive to the high resolution of the gate drive circuit.
  • the voltage of the scan signal can be increased to ensure the charging rate of the sub-pixel, and the size of the transistor included in the pixel driving circuit in the sub-pixel can be For example, the aspect ratio of the transistor can be reduced, which can increase the aperture ratio of the sub-pixels and improve the display effect.
  • the output control sub-circuit 101 includes a first transistor T1, the control electrode of the first transistor T1 is coupled to the pull-up node PU, and the first electrode of the first transistor T1 is connected to the first transistor T1.
  • the clock signal terminal CK1 is coupled, and the second electrode of the first transistor T1 is coupled to the first energy storage sub-circuit 201.
  • the first transistor T1 is configured to be turned on under the control of the voltage of the pull-up node, and transmits the first clock signal ck1 received at the first clock signal terminal CK1 to the first energy storage sub-circuit 201.
  • the first energy storage sub-circuit 201 includes a first capacitor C1, a first terminal of the first capacitor C1 is coupled to the pull-up node PU, and a second terminal of the first capacitor C1 is coupled to the second pole of the first transistor T1.
  • the first capacitor C1 is configured to store the voltage of the pull-up node PU.
  • the output sub-circuit 102 includes a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the pull-up node PU, the first electrode of the second transistor T2 is coupled to the pull-up node PU, and the second electrode of the second transistor T2 is coupled to the pull-up node PU.
  • the signal output terminal Output is coupled.
  • the second transistor T2 is configured to be turned on under the control of the voltage of the pull-up node, and output the raised voltage of the pull-up node PU to the signal output terminal Output.
  • the shift register further includes: a pull-down sub-circuit 103.
  • the pull-down sub-circuit 103 is coupled to the second clock signal terminal CK2, the signal output terminal Output, and the first voltage terminal VGL, and is configured to respond to the second clock signal ck2 received at the second clock signal terminal CK2,
  • the first voltage signal vgl received at the first voltage terminal VGL is transmitted to the signal output terminal Output.
  • the first voltage signal vgl is a low-level signal.
  • the shift register when the voltage of the pull-up node PU is not raised, the first voltage signal vgl is output to the signal output terminal Output through the pull-down sub-circuit 103, which ensures that the shift register does not output a scan signal at this stage .
  • the pull-down sub-circuit 103 includes a third transistor T3, the control electrode of the third transistor T3 is coupled to the second clock signal terminal CK2, and the first electrode of the third transistor T3 is coupled to the second clock signal terminal CK2.
  • a voltage terminal VGL is coupled, and the second electrode of the third transistor T3 is coupled to the signal output terminal Output.
  • the third transistor T3 is configured to be turned on under the control of the second clock signal ck2 to transmit the first voltage signal vgl to the signal output terminal Output.
  • the shift register further includes: a second energy storage sub-circuit 202; the second energy storage sub-circuit 202 is coupled to the first energy storage sub-circuit 201 and a signal output Between the terminals Output, it is configured to keep the voltage of the pull-up node PU stable while the voltage of the raised pull-up node PU is output to the signal output terminal Output.
  • the voltage of the pull-up node PU will slowly decrease due to the leakage phenomenon, and the scan signal output by the signal output terminal Output can pass
  • the end of the second energy storage sub-circuit 202 coupled to the signal output terminal raises the voltage of the end of the first energy storage sub-circuit 201 coupled to the second energy storage sub-circuit 202, and then passes through the first energy storage sub-circuit 201
  • the voltage of the pull-up node PU is further increased, so that the decrease in the voltage of the pull-up node PU caused by the leakage phenomenon and the further increase of the voltage of the pull-up node PU can be balanced, so that the voltage of the pull-up node PU remains stable.
  • the scanning signal output by the signal output terminal Output is more stable.
  • the second energy storage sub-circuit includes a second capacitor C2, and the first end of the second capacitor C2 is coupled to the signal output terminal Output; the first energy storage sub-circuit 201 includes In the case of the first capacitor C1, the second terminal of the second capacitor C2 is coupled to the second terminal of the first capacitor C1.
  • shift registers often include other sub-circuits, such as input sub-circuits, multiple control sub-circuits, and reset sub-circuits. Circuits, noise reduction sub-circuits, etc.
  • the present disclosure does not specifically limit the specific settings of other sub-circuits. Under the premise that the shift register can work normally, the settings can be selected according to actual needs.
  • the shift register includes all or part of the aforementioned sub-circuits, as shown in FIGS. 3 to 5, the shift register further includes: an input sub-circuit 104 and a reset sub-circuit 105 .
  • the aforementioned input sub-circuit 104 is coupled to the signal input terminal Input, the second voltage terminal VGH and the pull-up node PU.
  • the input sub-circuit 104 is configured to transmit the second voltage signal vgh received at the second voltage terminal VGH to the pull-up node PU in response to the input signal input received at the signal input terminal Input.
  • the reset sub-circuit 105 is coupled to the reset signal terminal Reset, the first voltage terminal VGL and the pull-up node PU.
  • the reset sub-circuit 105 is configured to output the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU in response to the reset signal reset received at the reset signal terminal Reset.
  • the input sub-circuit 104 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the signal input terminal Input, the first electrode of the fourth transistor T4 is coupled to the second voltage terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the pull-up node PU.
  • the fourth transistor T4 is configured to transmit the second voltage signal vgh to the pull-up node PU under the control of the input signal input.
  • the reset sub-circuit 105 includes a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the reset signal terminal Reset, the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VGL, and the second electrode of the fifth transistor T5 is coupled to the pull-up node PU.
  • the fifth transistor T5 is configured to output the first voltage signal vgl to the pull-up node PU under the control of the reset signal reset.
  • the shift register further includes: a pull-down node PD, a node control sub-circuit 106, a first noise reduction sub-circuit 107, and a second noise reduction sub-circuit 108.
  • the aforementioned node control sub-circuit 106 is coupled to the second voltage terminal VGH, the pull-up node PU, the first voltage terminal VGL, and the pull-down node PD.
  • the node control sub-circuit 106 is configured to respond to the voltage of the pull-up node PU and the second voltage signal vgh received at the second voltage terminal VGH to transmit the first voltage signal vgl received at the first voltage terminal VGL to Pull-down node PD; and, in response to the voltage of the pull-up node PU and the second voltage signal vgh received at the second voltage terminal VGH, transmit the second voltage signal vgh received at the second voltage terminal VGH to the pull-down node PD .
  • the first control sub-circuit 106 includes a sixth transistor T6 and a seventh transistor T7.
  • the control electrode of the sixth transistor T6 is coupled to the second voltage terminal VGH, the first electrode of the sixth transistor T6 is coupled to the second voltage terminal VGH, and the second electrode of the sixth transistor T6 is coupled to the pull-down node PD.
  • the sixth transistor T6 is configured to be turned on under the control of the second voltage signal vgh to transmit the second voltage signal vgh to the pull-down node PD.
  • the control electrode of the seventh transistor T7 is coupled to the pull-up node PU, the first electrode of the seventh transistor T7 is coupled to the first voltage terminal VGL, and the second electrode of the seventh transistor T7 is coupled to the pull-down node PD.
  • the seventh transistor T7 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the first voltage signal vgl to the pull-down node PD.
  • the function realization process of the first control sub-circuit 106 is: the sixth transistor T6 is turned on under the control of the second voltage signal vgh, and the first The seventh transistor T7 is turned on under the control of the voltage of the pull-up node PU, and the seventh transistor T7 transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-down node PD. And, the sixth transistor T6 is turned on under the control of the second voltage signal vgh, the seventh transistor T7 is turned off under the control of the voltage of the pull-up node PU, and the sixth transistor T6 will receive the second signal at the second voltage terminal VGH. The voltage signal vgh is transmitted to the pull-down node PD.
  • the size of the transistor means the width-to-length ratio of the channel of the transistor.
  • a transistor generally includes a gate, an active layer, a source, and a drain.
  • the “channel” refers to the active layer of the transistor between its source and drain in the working state.
  • Channel aspect ratio refers to the ratio of the width to the length of the channel, where the length of the channel refers to the size of the channel in the direction X from the source to the drain (or the drain to the source).
  • the width of the channel refers to the size of the channel in the vertical direction of the direction X described above.
  • the sixth transistor and the seventh transistor are both NMOS as an example, when the voltage of the pull-up node PU is high, Both the sixth transistor and the seventh transistor are turned on.
  • the potential of the pull-down node PD can be controlled by setting the size of the seventh transistor T7 to be greater than the size of the sixth transistor T6, that is, the aspect ratio of the channel of the seventh transistor T7 is greater than that of the channel of the sixth transistor T6. . Since the aspect ratio of the channel of the seventh transistor T7 is greater than the aspect ratio of the channel of the sixth transistor T6, it can be regarded that the resistance of the sixth transistor T6 is greater than the resistance of the sixth transistor T6.
  • the seventh transistor T7 When the second voltage signal vgh is turned on, and the seventh transistor T7 is configured to be turned on under the control of the voltage of the pull-up node PU, the divided voltage of the sixth transistor T6 is larger, so that the voltage of the pull-down node PD
  • the reduction means that when the sixth transistor T6 and the seventh transistor T7 are both turned on, the pull-down node PD can still be maintained at a low level, which can be regarded as transmitting the second voltage signal vgl to the pull-down node PD.
  • the aforementioned first noise reduction sub-circuit 107 is coupled to the pull-up node PU, the pull-down node PD, and the first voltage terminal VGL.
  • the first noise reduction sub-circuit 107 is configured to, under the control of the voltage of the pull-down node PD, transmit the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU, so as to implement the pull-up node PU. Noise reduction processing.
  • the first noise reduction sub-circuit 107 includes an eighth transistor T8.
  • the control electrode of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is coupled to the first voltage terminal VGL, and the second electrode of the eighth transistor T8 is coupled to the pull-up node PU.
  • the eighth transistor T8 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the pull-up node PU.
  • the aforementioned second noise reduction sub-circuit 108 is connected to the first voltage terminal VGL, the pull-down node PD, and the signal output terminal Output.
  • the second noise reduction sub-circuit 108 is configured to output the first voltage signal vgl of the first voltage terminal VGL to the signal output terminal Output under the control of the voltage of the pull-down node PD.
  • the second noise reduction sub-circuit 108 includes a ninth transistor T9.
  • the control electrode of the ninth transistor T9 is coupled to the pull-down node PD, the first electrode of the ninth transistor T9 is coupled to the first voltage terminal VGL, and the second electrode of the ninth transistor T9 is coupled to the signal output terminal Output.
  • the ninth transistor T9 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the signal output terminal Output.
  • the shift register includes: a pull-up node PU, an output control sub-circuit 101, a first energy storage sub-circuit 201, an output sub-circuit 102, a pull-down sub-circuit 103, an input sub-circuit 104, and a reset sub-circuit
  • the noise reduction sub-circuit 107 includes an eighth transistor T8, the second noise reduction sub-circuit
  • the control electrode of the first transistor T1 is coupled to the pull-up node PU, the first electrode of the first transistor T1 is coupled to the first clock signal terminal CK1, and the second electrode of the first transistor T1 is coupled to the second terminal of the first capacitor C1 Coupling.
  • the first transistor T1 is configured to be turned on under the control of the voltage of the pull-up node PU, and transmit the first clock signal ck1 to the second end of the first capacitor C1.
  • the first terminal of the first capacitor C1 is coupled to the pull-up node PU, and is also coupled to the control electrode of the first transistor T1.
  • the first capacitor C1 is configured to store the voltage of the pull-up node PU.
  • the control electrode of the second transistor T2 is coupled to the pull-up node PU, the first electrode of the second transistor T2 is coupled to the pull-up node PU, and the second electrode of the second transistor T2 is coupled to the signal output terminal Output.
  • the first transistor T1 is configured to be turned on under the control of the voltage of the pull-up node PU, and output the raised voltage of the pull-up node PU to the signal output terminal Output.
  • the control electrode of the third transistor T3 is coupled to the second clock signal terminal CK2, the first electrode of the third transistor T3 is coupled to the first voltage terminal VGL, and the second electrode of the third transistor T3 is coupled to the signal output terminal Output.
  • the third transistor T3 is configured to be turned on under the control of the second clock signal ck2 to output the first voltage signal vgl to the signal output terminal Output.
  • the control electrode of the fourth transistor T4 is coupled to the signal input terminal Input, the first electrode of the fourth transistor T4 is coupled to the second voltage terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the pull-up node PU.
  • the fourth transistor T4 is configured to be turned on under the control of the input signal input to transmit the second voltage signal vgh to the pull-up node PU.
  • the control electrode of the fifth transistor T5 is coupled to the reset signal terminal Reset, the first electrode of the fifth transistor T5 is coupled to the first voltage terminal VGL, and the second electrode of the fifth transistor T5 is coupled to the pull-up node PU.
  • the fifth transistor T5 is configured to be turned on under the control of the reset signal reset to transmit the first voltage signal vgl to the pull-up node PU.
  • the control electrode of the sixth transistor T6 is coupled to the second voltage terminal VGH, the first electrode of the sixth transistor T6 is coupled to the second voltage terminal VGH, and the second electrode of the sixth transistor T6 is coupled to the pull-down node PD Pick up.
  • the sixth transistor T6 is configured to be turned on under the control of the second voltage signal vgh to transmit the second voltage signal vgh to the pull-down node PD.
  • the control electrode of the seventh transistor T7 is coupled to the pull-up node PU, the first electrode of the seventh transistor T7 is coupled to the first voltage terminal VGL, and the second electrode of the seventh transistor T7 is coupled to the pull-down node PD.
  • the seventh transistor T7 is configured to be turned on under the control of the pull-up node PU, and transmit the first voltage signal vgl to the pull-down node PD.
  • the control electrode of the eighth transistor T8 is coupled to the pull-down node PD, the first electrode of the eighth transistor T8 is coupled to the first voltage terminal VGL, and the second electrode of the eighth transistor T8 is coupled to the pull-up node PU.
  • the eighth transistor T8 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the pull-up node PU.
  • the control electrode of the ninth transistor T9 is coupled to the pull-down node PD, the first electrode of the ninth transistor T9 is coupled to the first voltage terminal VGL, and the second stage of the ninth transistor T9 is coupled to the signal output terminal Output.
  • the eighth transistor T8 is configured to be turned on under the control of the voltage of the pull-down node PD, and transmit the first voltage signal vgl to the signal output terminal Output.
  • the transistors used in the shift register provided in the embodiments of the present disclosure may be N-type transistors or P-type transistors.
  • the transistors are all N-type transistors.
  • the transistors used in the shift register provided in the embodiments of the present disclosure may be enhancement transistors, depletion transistors or other switching devices with the same characteristics.
  • the above-mentioned transistor can also be an amorphous silicon thin film transistor, a polysilicon thin film transistor or an amorphous-indium gallium zinc oxide thin film transistor, which is not limited in the present disclosure.
  • control electrode of the transistor used in the above shift register may be the gate of the transistor, the first electrode may be the source and the second electrode may be the drain, or the first electrode of the transistor may be the drain and the second electrode Source, this disclosure does not limit this. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first and second electrodes of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.
  • the gate driving circuit includes at least two cascaded shift registers RS as described above.
  • the gate driving circuit includes n cascaded shift registers RS as described above, RS1 to RSn, respectively.
  • the signal input terminal Input of the first-stage shift register RS1 is coupled to the start signal terminal STV.
  • the signal input terminal Input of any stage shift register RS is coupled to the signal output terminal Output of the previous stage shift register RS of this stage shift register RS.
  • the signal input terminal Input of the second stage shift register RS2 is coupled to the signal output terminal Output of the first stage shift register RS1.
  • the signal input terminal Input of the third stage shift register RS3 is coupled to the signal output terminal Output of the second stage shift register RS2.
  • the reset signal terminal Reset of any stage of shift register RS is coupled to the signal output terminal Output of the next stage of shift register RS of the stage of shift register RS.
  • the second-stage shift register RS2 is coupled to the signal output terminal Output of the third-stage shift register RS3.
  • the reset signal terminal Reset of the third stage shift register RS3 is coupled to the signal output terminal Outpu of the fourth stage shift register RS4.
  • the reset signal terminal Reset of the last-stage shift register RSn is coupled to a separately set signal terminal for outputting a reset signal, or is coupled to a start signal terminal.
  • FIG. 6 only illustrates the coupling of the reset signal terminal Reset of the last-stage shift register RSn with a separately set signal terminal for outputting a reset signal as an example for illustration).
  • the gate driving circuit also includes n-stage shift registers.
  • the i-th stage shift register RSi is coupled to the i-th gate line Gi in the display panel, where i is a positive integer greater than or equal to 1 and less than or equal to n.
  • the gate driving circuit includes the shift register as described above, it has the same structure and beneficial effects as the shift register provided in the foregoing embodiment. Since the foregoing embodiment has described the structure and beneficial effects of the shift register in detail, it will not be repeated here.
  • Some embodiments of the present disclosure further provide a display device, including the above-mentioned gate driving circuit provided by the present disclosure, and also including the foregoing shift register, which has the same structure and beneficial effects as the shift register provided by the foregoing embodiment. Since the foregoing embodiment has described the structure and beneficial effects of the shift register in detail, it will not be repeated here.
  • the display device provided by the embodiment of the present disclosure is a liquid crystal display device, and the liquid crystal display device includes a liquid crystal display panel, or the display device provided by the embodiment of the present disclosure is an organic light emitting diode display device, and the organic light emitting diode display The device includes an organic light emitting diode display panel.
  • the display device provided by the embodiments of the present disclosure may be: liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator and other products or components with display function. There is no limit to this publicly.
  • the use of the gate driving circuit of the present disclosure can increase the voltage of the scan signal, thereby improving the charging efficiency; based on this, the actual production of liquid crystal display panels can correspondingly reduce the thin film transistors in the sub-pixels.
  • the size (W/L, that is, the width-to-length ratio of the channel) can further increase the aperture ratio of the sub-pixels.
  • Some embodiments of the present disclosure also provide a driving method of a shift register, and the driving method is applied to the shift register provided in some embodiments of the present disclosure.
  • one frame period includes the charging phase S1 and the output Stage S2:
  • the charging stage S1 includes:
  • the output control sub-circuit 101 Under the control of the voltage of the pull-up node PU, the output control sub-circuit 101 is turned on, and the first clock signal ck1 received at the first clock signal terminal CK1 is transmitted to the first energy storage sub-circuit 201. At this time, the level of the first clock signal ck1 is low.
  • the first energy storage sub-circuit 201 stores the voltage of the pull-up node PU.
  • the first transistor T1 is turned on under the control of the voltage of the pull-up node PU, and transmits the first clock signal ck1 received at the first clock signal terminal CK1 to the second terminal of the first capacitor C1.
  • the potential of the second terminal of the first capacitor C1 is the low-level potential of the first clock signal ck1, for example, 0V.
  • the first capacitor C1 stores the voltage of the pull-up node PU.
  • the potential of the first terminal of the first capacitor C1 is the voltage of the pull-up node PU, for example, 22V.
  • the output stage S2 includes:
  • the output control sub-circuit 101 Under the voltage control of the pull-up node PU, the output control sub-circuit 101 is turned on, and the first clock signal ck1 received at the first clock signal terminal CK1 is transmitted to the first energy storage sub-circuit 201. At this time, the level of the first clock signal ck1 is high.
  • the first energy storage sub-circuit 201 raises the voltage of the pull-up node PU.
  • the output sub-circuit 102 transmits the raised voltage of the pull-up node PU to the signal output terminal Output.
  • the output control sub-circuit 101 includes a first transistor T1
  • the first energy storage sub-circuit 201 includes a first capacitor C1
  • the output sub-circuit 102 includes a second transistor T2:
  • the first transistor T1 is turned on under the control of the voltage of the pull-up node PU, and transmits the first clock signal ck1 received at the first clock signal terminal CK1 to the second terminal of the first capacitor C1.
  • the potential of the second terminal of the first capacitor C1 is the high-level potential of the first clock signal ck1, for example, 22V. Since the potential of the second terminal of the first capacitor C1 rises, according to the bootstrap effect of the capacitor, the potential of the first terminal of the first capacitor C1 also rises accordingly. In theory, the potential of the first terminal of the first capacitor C1 can be 22V is changed to 44V, and the voltage of the pull-up node PU is raised.
  • the voltage of the pull-up node PU is raised to 30V.
  • the second transistor T2 is turned on under the control of the voltage of the pull-up node PU, and transmits the raised voltage (30V) of the pull-up node PU to the signal output terminal Output.
  • the signal output terminal Output only outputs the scanning signal in the output stage S2, and the signal output terminal Output does not output the scanning signal in the charging stage.
  • the threshold voltage of the second transistor T2 included in the output sub-circuit 102 is relatively high.
  • pulling up the voltage of the node PU cannot turn on the second transistor T2 and cannot pull up the voltage of the node PU. Transmitted to the signal output terminal.
  • the charging phase S1 further includes: under the control of the second clock signal ck2 transmitted by the second clock signal terminal CK2, the pull-down sub-circuit 103 is turned on , The first voltage signal vgl received at the first voltage terminal VGL is transmitted to the signal output terminal Output. This can also ensure that the shift register does not output a scan signal during the charging phase S1.
  • the output sub-circuit 102 outputs the voltage of the lifted pull-up node PU to the signal output terminal Output, and the voltage of the lifted pull-up node PU is used as a scan signal to realize In this way, the voltage of the scan signal is increased without increasing the high level of the clock signal clk and the power consumption of the display device, thereby increasing the charging rate of the sub-pixels, which is more conducive to the high resolution and high resolution of the gate drive circuit.
  • the output sub-circuit 102 outputs the voltage of the lifted pull-up node PU to the signal output terminal Output, and the voltage of the lifted pull-up node PU is used as a scan signal to realize In this way, the voltage of the scan signal is increased without increasing the high level of the clock signal clk and the power consumption of the display device, thereby increasing the charging rate of the sub-pixels, which is more conducive to the high resolution and high resolution of the gate drive circuit.
  • the output stage S2 further includes:
  • the second energy storage sub-circuit 202 keeps the voltage of the pull-up node PU stable during the process of outputting the voltage of the raised pull-up node PU to the signal output terminal Output.
  • the signal output terminal Output outputs the raised voltage of the pull-up node PU, so that the end of the second capacitor C2 coupled to the signal output terminal Output (the second end of the second capacitor C2 can be raised) ), under the bootstrap action of the second capacitor C2 and the first capacitor C1, the voltage of the pull-up node PU is further raised, so that the voltage of the pull-up node PU is reduced due to the leakage phenomenon and the pull-up node PU The further rise of the voltage can reach a balance, so that the voltage of the pull-up node PU remains stable, thereby making the scan signal output by the signal output terminal Output more stable.
  • the shift register further includes a pull-down sub-circuit 104, a pull-down node PD, an input sub-circuit 104, a reset sub-circuit 105, and a node control sub-circuit 106.
  • the entire process of the driving method of the shift register includes a charging phase S1, an output phase S2, a reset phase S3, and a noise reduction phase S4.
  • the charging stage S1 includes:
  • the input sub-circuit 104 Under the control of the input signal input transmitted by the signal input terminal Input, the input sub-circuit 104 is turned on and transmits the second voltage signal vgh received at the second voltage terminal VGH to the pull-up node PU.
  • the input signal input at the signal input terminal Input is an STV signal (Start Vertical, the start signal of the gate).
  • STV signal Start Vertical, the start signal of the gate
  • the output control sub-circuit 101 Under the control of the voltage of the pull-up node PU, the output control sub-circuit 101 is turned on, and the first clock signal ck1 received at the first clock signal terminal CK1 is transmitted to the first energy storage sub-circuit 201. At this time, the level of the first clock signal ck1 is low.
  • the first energy storage sub-circuit 201 stores the voltage of the pull-up node PU.
  • the pull-down sub-circuit 103 Under the control of the second clock signal ck2 transmitted from the second clock signal terminal CK2, the pull-down sub-circuit 103 is turned on and transmits the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output.
  • the node control sub-circuit 106 transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-down node PD, So that the voltage of the pull-down node PD is low at this time.
  • the first noise reduction sub-circuit 107 and the second noise reduction sub-circuit 108 are closed under the control of the voltage of the pull-down node PD, and the reset sub-circuit 105 is closed under the control of the reset signal reset.
  • the output control sub-circuit 101 includes a first transistor T1
  • the output sub-circuit 102 includes a second transistor T2
  • the pull-down sub-circuit 103 includes a third transistor T3
  • the input sub-circuit 104 includes The fourth transistor T4, the reset sub-circuit 105 includes a fifth transistor T5, the node control sub-circuit 106 includes a sixth transistor T6 and a seventh transistor T7, the first noise reduction sub-circuit 107 includes an eighth transistor T8, and the second noise reduction sub-circuit
  • the charging stage S1 includes:
  • the fourth transistor T4 is turned on under the control of the input signal input, and transmits the second voltage signal vgh received at the second voltage terminal VGH to the pull-up node PU and to the first terminal of the first capacitor C1.
  • the first transistor T1 is turned on under the control of the voltage of the pull-up node PU, and transmits the first clock signal ck1 to the second end of the first capacitor C1. At this time, the level of the first clock signal ck1 is low.
  • the seventh transistor T7 is turned on under the control of the high level of the pull-up node PU, and outputs the first level signal vgl received at the first voltage terminal VGL to the pull-down node PD. It should be noted that since the size of the seventh transistor T7 is larger than the size of the sixth transistor T6, even if the sixth transistor T6 is in the on state under the control of the second voltage signal vgh, the first voltage terminal VGL has a first level The signal vgl (low level) can still ensure that the pull-down node PD maintains a low level.
  • the second transistor T2 is turned on under the control of the voltage of the pull-up node PU; at the same time, the third transistor T3 is turned on under the control of the high level of the second clock signal terminal CK2, and will be turned on at the first voltage.
  • the first level signal vgl received at the terminal VGL is transmitted to the signal output terminal Output.
  • the size of the third transistor T3 is larger than the size of the second transistor T2
  • the first level signal vgl (low) of the first voltage terminal VGL Level) can still ensure that the signal output terminal Output maintains a low level, thereby ensuring that the signal output terminal Output outputs the first level signal vgl (low level) during the charging stage S1.
  • the threshold voltage of the second transistor T2 is relatively high.
  • the voltage of the pull-up node PU cannot turn on the second transistor T2, that is, the second transistor T2 is turned off.
  • the third transistor T3 is turned on under the control of the high level of the second clock signal terminal CK2, and transmits the first level signal vgl received at the first voltage terminal VGL to the signal output terminal Output.
  • the fifth transistor T5, the eighth transistor T8 and the ninth transistor T9 are all turned off during the charging stage S1.
  • the output stage S2 includes:
  • the output control sub-circuit 101 Under the voltage control of the pull-up node PU, the output control sub-circuit 101 is turned on, and the first clock signal ck1 received at the first clock signal terminal CK1 is transmitted to the first energy storage sub-circuit 201. Since the first energy storage sub-circuit 201 stores the voltage of the pull-up node PU during the charging phase S1, the first energy storage sub-circuit 201 discharges the pull-up node PU during the output phase S2, so that the voltage of the pull-up node PU remains high. The voltage can make the output control sub-circuit 101 open. At this stage, the level of the first clock signal ck1 is high.
  • the first energy storage sub-circuit 201 raises the voltage of the pull-up node PU.
  • the output sub-circuit 102 is turned on to transmit the raised voltage of the pull-up node PU to the signal output terminal Output.
  • the node control sub-circuit 106 transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-down node PD, At this time, the voltage of the pull-down node PD is low.
  • the pull-down sub-circuit 103 is closed; the input sub-circuit 104 is closed under the control of the input signal input , The first noise reduction sub-circuit 107 and the second noise reduction sub-circuit 108 are closed under the control of the voltage of the pull-down node PD, and the reset sub-circuit 105 is closed under the control of the reset signal reset.
  • the output control sub-circuit 101 includes a first transistor T1
  • the output sub-circuit 102 includes a second transistor T2
  • the pull-down sub-circuit 103 includes a third transistor T3
  • the input sub-circuit 104 includes The fourth transistor T4, the reset sub-circuit 105 includes a fifth transistor T5, the node control sub-circuit 106 includes a sixth transistor T6 and a seventh transistor T7, the first noise reduction sub-circuit 107 includes an eighth transistor T8, and the second noise reduction sub-circuit
  • the output stage S2 includes:
  • the first capacitor C1 discharges the voltage stored in the charging stage S1 to the pull-up node PU.
  • the third transistor T3 Under the control of the voltage of the pull-up node PU, the third transistor T3 is turned on, and the first clock signal received at the first clock signal terminal CK1 The signal (high level signal) is output to the second terminal of the first capacitor C1.
  • the potential of the first terminal of the first capacitor C1 rises, thereby raising the voltage of the pull-up node PU.
  • the second transistor T2 is turned on and outputs the raised voltage of the pull-up node PU (as a scan signal) to the signal output terminal Output.
  • the sixth transistor T6 and the fifth transistor T7 are kept in a conducting state (same as the charging stage S1), so that the potential of the pull-down node PD is kept low.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are all in an off state.
  • the potential of the pull-up node PU is raised, when the level of the first voltage signal vgh is equal to the high level of the first clock signal ck1 In the case of, for example, 22V, the potential of the pull-up node PU can theoretically rise to twice the high level of the first clock signal terminal CK1; in actual simulation, it is not absolutely possible to reach the first clock signal terminal CK1 2 times the high level. For example, when the high level of the first clock signal terminal CK1 is 22V, the voltage of the pull-up node PU rises to 30V through the bootstrap action of the first capacitor C1. It can be seen that the use of the shift register in the present disclosure can raise the voltage of the pull-up node PU, thereby increasing the voltage of the scan signal at the signal output terminal Output.
  • the driving method further includes: a reset stage S3 after the output stage S2, and the reset stage S3 includes:
  • the reset sub-circuit 105 Under the control of the reset signal reset transmitted from the reset signal terminal Reset, the reset sub-circuit 105 is turned on and outputs the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU. At this time, the voltage of the pull-up node PU is low, and the output sub-circuit 102 is closed under the control of the voltage of the pull-up node PU, and stops outputting the voltage of the pull-up node PU to the signal output terminal Output.
  • the node control sub-circuit 106 transmits the second voltage signal vgh received at the second voltage terminal VGH to the pulled-down node PD.
  • the voltage of the pull-down node PD is a high voltage.
  • the first noise reduction sub-circuit 107 Under the control of the voltage of the pull-down node PD, the first noise reduction sub-circuit 107 is turned on, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU.
  • the second noise reduction sub-circuit 108 Under the control of the voltage of the pull-down node PD, the second noise reduction sub-circuit 108 is turned on, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output.
  • the pull-down sub-circuit 103 Under the control of the second clock signal ck2 transmitted from the second clock signal terminal CK2, the pull-down sub-circuit 103 is turned on and transmits the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output.
  • the output control sub-circuit 101 and the output sub-circuit 102 are both closed under the control of the voltage of the pull-up node PU.
  • the output control sub-circuit 101 includes a first transistor T1
  • the output sub-circuit 102 includes a second transistor T2
  • the pull-down sub-circuit 103 includes a third transistor T3
  • the input sub-circuit 104 includes The fourth transistor T4, the reset sub-circuit 105 includes a fifth transistor T5, the node control sub-circuit 106 includes a sixth transistor T6 and a seventh transistor T7, the first noise reduction sub-circuit 107 includes an eighth transistor T8, and the second noise reduction sub-circuit
  • the reset stage S3 includes:
  • the fifth transistor T5 is turned on under the control of the high-level reset signal reset transmitted from the reset signal terminal Reset, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU, so that the pull-up node PU The voltage drops to achieve reset.
  • the seventh transistor T7 is turned off, and the sixth transistor T6 is turned on under the control of the second voltage signal vgh transmitted by the second voltage terminal VGH, and outputs the second voltage signal vgh to the pull-down node PD, so that the voltage of the pull-down node PD increases.
  • the eighth transistor T8 Under the control of the voltage of the pull-down node PD, the eighth transistor T8 is turned on and transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU for reset; at the same time, the voltage of the pull-down node PD is controlled Next, the ninth transistor T9 is turned on, and outputs the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output for reset.
  • the third transistor T3 is turned on, and the third transistor T3 is turned on at the first voltage terminal VGL
  • the first voltage signal vgl received at is output to the signal output terminal Output.
  • the first transistor T1, the second transistor T2, and the fourth transistor T4 are all in the cut-off state during the reset phase S3.
  • the noise reduction stage S4 includes:
  • the second noise reduction sub-circuit 108 Under the control of the voltage of the pull-down node PD, the second noise reduction sub-circuit 108 is turned on, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output, and continuously reduces noise on the signal output terminal Output .
  • the pull-down sub-circuit 103 is periodically turned on and off under the control of the second clock signal ck2. When the pull-down sub-circuit 103 is turned on, it can output the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output can also reduce noise.
  • the node control sub-circuit 106 outputs the second voltage signal vgh received at the second voltage terminal VGH to the pull-down node PD in response to the voltage of the pull-up node PU and the second voltage signal vgh received at the second voltage terminal VGH. , So that the potential of the pull-down node PD rises. Under the control of the voltage of the pull-down node PD, the first noise reduction sub-circuit 107 is turned on to output the voltage of the first voltage terminal VGL to the pull-up node PU.
  • the output sub-circuit 102, the output control sub-circuit 101, and the input sub-circuit 104 are all in the closed state during the noise reduction stage S4.
  • the output control sub-circuit 101 includes a first transistor T1
  • the output sub-circuit 102 includes a second transistor T2
  • the pull-down sub-circuit 103 includes a third transistor T3
  • the input sub-circuit 104 includes The fourth transistor T4, the reset sub-circuit 105 includes a fifth transistor T5, the node control sub-circuit 106 includes a sixth transistor T6 and a seventh transistor T7, the first noise reduction sub-circuit 107 includes an eighth transistor T8, and the second noise reduction sub-circuit
  • the noise reduction stage S4 includes:
  • the ninth transistor T9 is turned on under the control of the voltage of the pull-down node PD, and outputs the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output for noise reduction.
  • the third transistor T3 is periodically turned on and off under the control of the second clock signal terminal CK2 (high and low level). When the third transistor T3 is turned on, it will receive the first voltage at the first voltage terminal VGL. The voltage signal vgl is output to the signal output terminal Output for noise reduction.
  • the sixth transistor T6 is turned on under the control of the second voltage signal vgh
  • the seventh transistor T7 is turned off under the control of the pull-up node PU
  • the signal vgh is transmitted to the pull-down node PD.
  • the eighth transistor T8 is in a conductive state under the control of the pull-down node PD.
  • the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all in an off state.
  • the turn-on and turn-off processes of the transistors in the above embodiments are all transistors are N-type transistors, the first voltage terminal VGL is a low-level voltage terminal, the second voltage terminal VGH is a high-level voltage terminal, and the first clock signal
  • the duty ratios of the ck1 and the second clock signal ck2 are both 50%, and the high and low level changes of the first clock signal ck1 and the second clock signal ck2 are completely opposite.
  • all the transistors are P-type, it is necessary to invert each control signal, the first voltage terminal, and the second voltage terminal in FIG. 5.
  • Some embodiments of the present disclosure also provide another driving method of the above-mentioned shift register.
  • the driving method is based on the situation that the duty ratios of the first clock signal ck1 and the second clock signal ck2 are both less than 50%, that is, In a period of level change, the proportion of time occupied by the high level is less than the proportion of time occupied by the low level.
  • the following takes the shift register shown in Figures 4 and 5 as an example, and all transistors included in all shift registers are N-type transistors, the first voltage terminal VGL is a low-level voltage terminal, and the second voltage terminal VGH is The high-level voltage terminal will exemplify the driving method.
  • the specific circuit structure included in the shift register can be referred to the above description, which will not be repeated here.
  • the driving method includes: a charging stage S1', an output stage S2', a first reset stage S3', and a second reset stage S4'.
  • the charging stage S1’ includes:
  • the level of the input signal input transmitted by the input signal terminal Input is high, and the fourth transistor T4 is turned on under the control of the input signal input to transmit the second voltage signal vgh received at the second voltage terminal VGH to the pull-up node PU, make the voltage of the pull-up node PU the voltage of the second voltage signal vgh, for example, 22V.
  • the first transistor is turned on under the control of the voltage of the pull-up node PU, and the first clock signal ck1 received at the first clock signal terminal CK1 (at this time, the level of the first clock signal ck1 is low, for example, 0V) is transmitted to the second end of the first capacitor C1.
  • the first capacitor C1 stores the voltage of the pull-up node PU, and the voltage of the first terminal of the first capacitor C1 is the voltage of the pull-up node PU.
  • the second transistor T2 is turned on under the control of the voltage of the pull-up node PU, and transmits the voltage of the pull-up node PU to the signal output terminal Output. Since the gate drive circuit opens the gate line several rows in advance, Even if the second transistor T2 is turned on, the pixel driving circuit included in the pixel will not receive the data signal, and the pixel will not be charged. Therefore, the voltage transmitted to the signal output terminal Output in the charging stage S1' has no effect on the pixel charging.
  • the level of the second clock signal ck2 at the second clock signal terminal CK2 is low, and the third transistor T3 is turned off under the control of the second clock signal ck2.
  • the level of the reset signal reset at the reset signal terminal Reset is low, and the fifth transistor T5 is turned off under the control of the reset signal reset.
  • the sixth transistor is turned on under the control of the second voltage signal vgh
  • the seventh transistor T7 is turned on under the control of the voltage of the pull-up node PU
  • the seventh transistor T7 will receive the first voltage signal at the first voltage terminal VGL
  • the vgl is transmitted to the pull-down node PD. Since the size of the seventh transistor T7 is larger than the size of the sixth transistor, the potential of the pull-down node PD is low (for the principle here, please refer to the above description).
  • Both the eighth transistor T8 and the ninth transistor T9 are turned off under the control of the voltage of the pull-down node PD.
  • the output stage S2’ includes:
  • the voltage of the pull-up node PU still maintains a high level (for example, 22V)
  • the first transistor T1 is turned on under the control of the voltage of the pull-up node PU, and will be at the first clock signal terminal
  • the first clock signal ck1 received at CK1 (the level of the first clock signal ck1 is high at this time, for example, 22V) is transmitted to the second end of the first capacitor C1, and under the bootstrap action of the first capacitor C1 ,
  • the voltage of the first terminal of the first capacitor C1 rises, thereby raising the voltage of the pull-up node PU.
  • the voltage of the pull-up node PU can be raised to 44V.
  • the second transistor T2 is turned on under the control of the voltage of the pull-up node PU, and transmits the raised voltage of the pull-up node PU to the signal output terminal Output, which is output as a scan signal.
  • the voltage of the pull-up node PU can be further increased, so that the voltage of the pull-up node PU and the further increase of the voltage of the pull-up node PU caused by the leakage phenomenon can reach Balance, so that the voltage of the pull-up node PU remains stable.
  • the level of the second clock signal ck2 at the second clock signal terminal CK2 is low, and the third transistor T3 is turned off under the control of the second clock signal ck2.
  • the reset signal reset transmitted by the reset signal terminal Reset has a low level, and the fifth transistor T5 is turned off under the control of the reset signal reset.
  • the sixth transistor is turned on under the control of the second voltage signal vgh
  • the seventh transistor T7 is turned on under the control of the voltage of the pull-up node PU
  • the seventh transistor T7 will receive the first voltage signal at the first voltage terminal VGL vgl is transmitted to the pull-down node PD, so that the potential of the pull-down node PD remains low.
  • Both the eighth transistor T8 and the ninth transistor T9 are turned off under the control of the voltage of the pull-down node PD.
  • the first reset stage S3' includes:
  • the level of the first clock signal ck1 transmitted by the first clock signal terminal CK1 is low, the voltage of the pull-up node PU is still high, and the first transistor T1 is turned on under the control of the voltage of the pull-up node PU, turning on The first clock signal ck1 is transmitted to the second terminal of the first capacitor C1. Under the bootstrap action of the capacitor, the potential of the first terminal of the first capacitor C1 is pulled down, thereby pulling down the voltage of the pull-up node PU. Simultaneously. The first transistor T1 transmits the first clock signal ck1 to the first terminal of the second capacitor C1. Under the bootstrap action of the capacitor, the potential of the second terminal of the second capacitor C2 is pulled down, so that the potential of the signal output terminal Output is also reduce.
  • the level of the second clock signal ck2 transmitted by the second clock signal terminal CK2 is still low, and the third transistor T3 is turned off under the control of the second clock signal ck2.
  • the level of the reset signal reset at the reset signal terminal Reset rises, but the potential is not enough to turn on the fifth transistor T5, and the fifth transistor T5 is still turned off under the control of the reset signal reset.
  • the sixth transistor is turned on under the control of the second voltage signal vgh
  • the seventh transistor T7 is turned on under the control of the voltage of the pull-up node PU
  • the seventh transistor T7 will receive the first voltage signal at the first voltage terminal VGL vgl is transmitted to the pull-down node PD, so that the potential of the pull-down node PD remains low.
  • Both the eighth transistor T8 and the ninth transistor T9 are turned off under the control of the voltage of the pull-down node PD.
  • the second reset stage S4' includes:
  • the level of the reset signal reset transmitted by the reset signal terminal Reset is further raised, and the fifth transistor T5 is turned on under the control of the reset signal reset, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU,
  • the voltage of the pull-up node PU is pulled down, so that under the control of the voltage of the pull-up node PU, the first transistor T1 is turned off, the second transistor T2 is turned off, and the seventh transistor T7 is turned off.
  • the sixth transistor is kept on under the control of the second voltage signal vgh, and transmits the second voltage signal vgh received at the second voltage terminal VGH to the pull-down node PD, so that the potential of the pull-down node PD increases.
  • the eighth transistor T8 is turned on under the control of the voltage of the pull-down node PD, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the pull-up node PU.
  • the ninth transistor T9 is turned on under the control of the voltage of the pull-down node PD, and transmits the first voltage signal vgl received at the first voltage terminal VGL to the signal output terminal Output.
  • the level of the second clock signal ck2 transmitted by the second clock signal terminal CK2 is high, the third transistor T3 is turned on under the control of the second clock signal ck2, and will receive the first voltage at the first voltage terminal VGL The signal vgl is transmitted to the signal output terminal Output.

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Abstract

一种移位寄存器，包括：上拉节点、输出控制子电路（101）、第一储能子电路（201）和输出子电路（102）；输出控制子电路（101）与上拉节点、第一时钟信号端和第一储能子电路（201）耦接；输出控制子电路（101）被配置为，在上拉节点的电压的控制下，将在第一时钟信号端处接收的第一时钟信号传输至第一储能子电路（201）；第一储能子电路（201）与上拉节点和输出控制子电路（101）耦接；第一储能子电路（201）被配置为，存储上拉节点的电压，及在第一时钟信号的作用下，抬升上拉节点的电压；输出子电路（102）与上拉节点和信号输出端耦接；输出子电路（102）被配置为，在上拉节点的电压的控制下，将被抬升的上拉节点的电压输出至信号输出端。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2019年01月18日提交的、申请号为201910049433.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
GOA(Gate Driver on Array，阵列基板行驱动)是一种将栅极驱动电路集成于阵列基板上的技术，其中，GOA电路的每一级(即移位寄存器)与一行栅线电连接，被配置为向该栅线输出栅极扫描信号，从而实现对显示装置中的多条栅线的逐行扫描(驱动)。
发明内容
一方面，提供一种移位寄存器，包括：上拉节点、输出控制子电路、第一储能子电路和输出子电路。其中，所述输出控制子电路与所述上拉节点、第一时钟信号端和所述第一储能子电路耦接；所述输出控制子电路被配置为，在所述上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一储能子电路。所述第一储能子电路与所述上拉节点和所述输出控制子电路耦接；所述第一储能子电路被配置为，存储所述上拉节点的电压，及在所述第一时钟信号的作用下，抬升所述上拉节点的电压。所述输出子电路与所述上拉节点和信号输出端耦接；所述输出子电路被配置为，在所述上拉节点的电压的控制下，将被抬升的所述上拉节点的电压输出至所述信号输出端。
在一些实施例中，所述输出控制子电路包括第一晶体管，所述第一晶体管的控制极与所述上拉节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第一储能子电路耦接。所述第一储能子电路包括第一电容，所述第一电容的第一端与所述上拉节点耦接，所述第一电容的第二端与所述第一晶体管的第二极耦接。所述输出子电路包括第二晶体管，所述第二晶体管的控制极与所述上拉节点耦接，所述第二晶体管的第一极与所述上拉节点耦接，所述第二晶体管的第二极与所述信号输出端耦接。
在一些实施例中，移位寄存器还包括下拉子电路；所述下拉子电路与第二时钟信号端、所述信号输出端和第一电压端耦接，被配置为响应 于在所述第二时钟信号端处接收的第二时钟信号，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
在一些实施例中，所述下拉子电路包括第三晶体管，所述第三晶体管的控制极与所述第二时钟信号端耦接，所述第三晶体管的第一极与所述第一电压端耦接，所述第三晶体管的第二极与所述信号输出端耦接。
在一些实施例中，移位寄存器还包括第二储能子电路；所述第二储能子电路耦接于所述第一储能子电路和所述信号输出端之间，被配置为在被抬升的所述上拉节点的电压输出至所述信号输出端的过程中，使所述上拉节点的电压保持稳定。
在一些实施例中，所述第二储能子电路包括第二电容，所述第二电容的第一端与所述信号输出端耦接；在所述第一储能子电路包括第一电容的情况下，所述第二电容的第二端与所述第一电容的第二端耦接。
在一些实施例中，移位寄存器还包括输入子电路和复位子电路。所述输入子电路与信号输入端、第二电压端和所述上拉节点耦接，被配置为响应于在所述信号输入端处接收的输入信号，将在所述第二电压端处接收的第二电压信号传输至所述上拉节点。所述复位子电路与复位信号端、第一电压端和所述上拉节点耦接，被配置为响应于在所述复位信号端处接收的复位信号，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点。
在一些实施例中，所述输入子电路包括第四晶体管，所述第四晶体管的控制极与所述信号输入端耦接，所述第四晶体管的第一极与所述第二电压端耦接，所述第四晶体管的第二极与所述上拉节点耦接。所述复位子电路包括第五晶体管，所述第五晶体管的控制极与所述复位信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述上拉节点耦接。
在一些实施例中，移位寄存器还包括：下拉节点、节点控制子电路、第一降噪子电路和第二降噪子电路。所述节点控制子电路与所述第二电压端、所述上拉节点、所述第一电压端和所述下拉节点耦接。所述节点控制子电路被配置为响应于所述上拉节点的电压和在所述第二电压端处接收的第二电压信号，将在所述第一电压端处接收的第一电压信号传输至所述下拉节点；及，响应于所述上拉节点的电压和在所述第二电压端处接收的第二电压信号，将在所述第二电压端处接收的第二电压信号传输至所述下拉节点。所述第一降噪子电路与所述上拉节点、所述下拉节 点和所述第一电压端耦接，被配置为在所述下拉节点的电压的控制下，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点。所述第二降噪子电路与所述下拉节点、所述第一电压端和所述信号输出端耦接，被配置为在所述下拉节点的电压的控制下，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
在一些实施例中，所述节点控制子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二电压端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述下拉节点耦接；所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第二电压端耦接，所述第七晶体管的第二极与所述下拉节点耦接。所述第一降噪子电路包括第八晶体管，所述第八晶体管的控制极与所述下拉节点耦接，所述第八晶体管的第一极与所述第二电压端耦接，所述第八晶体管的第二极与所述上拉节点耦接。所述第二降噪子电路包括第九晶体管，所述第九晶体管的控制极与所述下拉节点耦接，所述第九晶体管的第一极与所述第二电压端耦接，所述第九晶体管的第二极与所述信号输出端耦接。
在一些实施例中，所述第七晶体管的尺寸大于所述第六晶体管的尺寸。
在一些实施例中，移位寄存器包括：上拉节点、输出控制子电路、第一储能子电路、输出子电路、下拉子电路、输入子电路、复位子电路、下拉节点、节点控制子电路、第一降噪子电路和第二降噪子电路；其中，所述输出控制子电路包括第一晶体管，所述第一储能子电路包括第一电容，所述输出子电路包括第二晶体管，所述下拉子电路包括第三子电路，所述输入子电路包括第四晶体管，所述复位子电路包括第五晶体管，所述节点控制子电路包括第六晶体管和第七晶体管，所述第一降噪子电路包括第八晶体管，所述第二降噪子电路包括第九晶体管。
所述第一晶体管的控制极与所述上拉节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第一电容的第二端耦接。所述第一电容的第一端与所述上拉节点耦接，还与所述第一晶体管的控制极耦接。所述第二晶体管的控制极与所述上拉节点耦接，所述第二晶体管的第一极与所述上拉节点耦接，所述第二晶体管的第二极与所述信号输出端耦接。所述第三晶体管的控制极与第二时钟信号端耦接，所述第三晶体管的第一极与第一电压端耦接，所述第三 晶体管的第二极与所述信号输出端耦接。所述第四晶体管的控制极与信号输入端耦接，所述第四晶体管的第一极与第二电压端耦接，所述第四晶体管的第二极与所述上拉节点耦接。所述第五晶体管的控制极与复位信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述上拉节点耦接。
所述第六晶体管的控制极与所述第二电压端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述下拉节点耦接。所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第一电压端耦接，所述第七晶体管的第二极与所述下拉节点耦接。所述第八晶体管的控制极与所述下拉节点耦接，所述第八晶体管的第一极与所述第一电压端耦接，所述第八晶体管的第二极与所述上拉节点耦接。所述第九晶体管的控制极与所述下拉节点耦接，所述第九晶体管的第一极与所述第一电压端耦接，所述第九晶体管的第二级与所述信号输出端耦接。
在一些实施例中，移位寄存器还包括：第二电容；所述第二电容的第一端与所述第一晶体管的第二极耦接，所述第二电容的第二端与所述信号输出端耦接。
另一方面，提供一种栅极驱动电路，包括至少两个级联的如上一方面所述的移位寄存器。第一级移位寄存器的信号输入端耦接起始信号端。除了所述第一级移位寄存器以外，任一级移位寄存器的信号输入端与该级移位寄存器的上一级移位寄存器的信号输出端耦接。除了最后一级移位寄存器以外，任一级移位寄存器的复位信号端与该级移位寄存器的下一级移位寄存器的信号输出端耦接。所述最后一级移位寄存器的复位信号端与单独设置的用于输出复位信号的信号端耦接，或者，与所述起始信号端耦接。
再一方面，提供一种显示装置，包括如上所述的栅极驱动电路。
又一方面，提供一种移位寄存器的驱动方法，应用于如上所述的移位寄存器，该驱动方法包括：一个帧周期包括充电阶段和输出阶段。
所述充电阶段包括：在上拉节点的电压控制下，输出控制子电路开启，将在第一时钟信号端处接收的第一时钟信号传输至所述第一储能子电路。所述第一储能子电路存储所述上拉节点的电压。
所述输出阶段包括：在所述上拉节点的电压控制下，输出控制子电路开启，将所述第一时钟信号传输至所述第一储能子电路。所述第一储能子电路响应于所述第一时钟信号，抬升所述上拉节点的电压。输出子 电路在所述上拉节点的电压的控制下，将被抬升的所述上拉节点的电压传输至所述信号输出端。
在一些实施例中，在所述移位寄存器还包括下拉子电路的情况下，所述充电阶段还包括：在第二时钟信号端传输的第二时钟信号的控制下，所述下拉子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
在一些实施例中，在所述移位寄存器还包括第二储能子电路的情况下，所述输出阶段还包括：所述第二储能子电路在被抬升的所述上拉节点的电压输出至所述信号输出端的过程中，使所述上拉节点的电压保持稳定。
在一些实施例中，在所述移位寄存器还包括下拉节点、输入子电路、复位子电路、节点控制子电路、第一降噪子电路和第二降噪子电路的情况下，所述充电阶段还包括：在信号输入端传输的输入信号的控制下，所述输入子电路开启，将在第二电压端处接收的第二电压信号传输至所述上拉节点。所述节点控制子电路响应于所述上拉节点的电压及在所述第二电压端处接收的第二电压信号，将在所述第一电压端处接收的第一电压信号传输至所述下拉节点。
所述驱动方法还包括：位于所述输出阶段之后的复位阶段，所述复位阶段包括：在复位信号端传输的复位信号的控制下，所述复位子电路开启，将在所述第一电压端处接收的第一电压信号输出至所述上拉节点。所述节点控制子电路响应于所述上拉节点的电压及在所述第二电压端处接收的第二电压信号，将在所述第二电压端处接收的第二电压信号传输至所述下拉节点。在所述下拉节点的电压的控制下，所述第一降噪子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点。在所述下拉节点的电压的控制下，所述第二降噪子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。在所述第二时钟信号端传输的第二时钟信号的控制下，所述下拉子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
所述驱动方法还包括：位于所述复位阶段之后、下一个帧周期之前的降噪阶段，所述降噪阶段包括：在所述下拉节点的电压的控制下，所述第二降噪子电路保持开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术中的移位寄存器的结构图；
图2为根据本公开的一些实施例的移位寄存器的一种结构图；
图3为根据本公开的一些实施例的移位寄存器的另一种结构图；
图4为根据本公开的一些实施例的移位寄存器的又一种结构图；
图5为根据本公开的一些实施例的移位寄存器的再一种结构图；
图6为根据本公开的一些实施例的栅极驱动电路的结构图；
图7为根据本公开的一些实施例的移位寄存器的一种驱动方法的时序图；
图8为根据本公开的一些实施例的移位寄存器的驱动方法的流程图；
图9为根据本公开的一些实施例的移位寄存器的另一种驱动方法的时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第 一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
除非另外定义，本公开实施例中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示装置中，GOA电路包括多个移位寄存器，GOA电路的每一级(即移位寄存器)与一行栅线电连接，即GOA电路所包括的移位寄存器的数目与显示装置的分辨率相当，每个移位寄存器被配置为向与其电连接的栅线提供扫描信号，从而实现对显示面板中的多条栅线的逐行扫描(驱动)。每条栅线对应一行亚像素，在扫描信号的控制下，该行亚像素中的每个亚像素所对应的像素驱动电路中的开关晶体管导通，从而接收数据线所传输的数据信号，为亚像素充电。
相关技术中，如图1所示，移位寄存器包括上拉节点PU和下拉节点PD，一般的，在同一时段，上拉节点PU和下拉节点PD的电位相反，通过控制上拉节点PU和下拉节点PD的电位，来控制信号输出端Output输出扫描信号以及停止输出扫描信号。
示例性地，在扫描信号的输出阶段，上拉节点PU的电位为高电位，下拉节点PD的电位为低电位，晶体管M3在上拉节点PU的控制下导通，将在时钟信号端CLK处接收的时钟信号clk(此时时钟信号clk的电平为高电平)作 为扫描信号通过信号输出端Output输出。
也就是说，在相关技术中，是将时钟信号clk的高电平(例如可以为22V)作为扫描信号，输出至信号输出端Output。然而，随着高分辨率、大尺寸显示装置的普及，每一行亚像素充电的时间越来越少，这样就可能会造成亚像素充电不足的问题。一般情况下，像素驱动电路中的开关晶体管的栅极电压越高，该开关晶体管的导通程度越高，则该亚像素充电越充分。在一些实施例中，通过提高扫描信号的电压，提高亚像素的充电率，例如可以提高时钟信号clk的高电平(例如可以由原来的22V提高至30V)来解决该问题，但这样一来，会大大增加显示装置的功耗，与目前的低功耗理念不符。
基于此，本公开实施例提供一种低功耗、高输出电压的移位寄存器(或者说栅极驱动电路)；如图2～图5所示，该移位寄存器包括：上拉节点PU、输出控制子电路101、第一储能子电路201和输出子电路102。
其中，输出控制子电路101与上拉节点PU、第一时钟信号端CK1和所述第一储能子电路201耦接。输出控制子电路101被配置为，在上拉节点的电压的控制下，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。其中，第一时钟信号端CK1被配置为接收第一时钟信号ck1，并将第一时钟信号ck1输入该输出控制子电路101。
第一储能子电路201与上拉节点PU和输出控制子电路101耦接。第一储能子电路201被配置为，存储上拉节点PU的电压，及在第一时钟信号ck1的作用下，抬升上拉节点PU的电压。
输出子电路102与上拉节点PU和信号输出端Output耦接；输出子电路102被配置为，在上拉节点PU的电压的控制下，将被抬升的上拉节点PU的电压输出至信号输出端Output。
在本公开的一些实施例中所提供的移位寄存器中，通过设置输出子电路102与上拉节点PU和信号输出端Output耦接，使得输出子电路课102在上拉节点PU的电压的控制下，能够直接将上拉节点PU的电压输出至信号输出端Output，因此输出至信号输出端Output的电压为上拉节点PU的电压，而非相关技术中的输出至信号输出端Output的电压为时钟信号clk的高电平。并在此基础上，本公开所提供的移位寄存器中，在充电阶段通过输出控制子电路101将第一时钟信号ck1的低电平传输至第一储能子电路201，并通过第一储能子电路201存储上拉节点PU的电压，在输出阶段通过输出控制子电路101将第一时钟信号ck1的高电平传输至第一储能子电路201，使得第一储能子电路201在第一时钟信号ck1的作用下，将上拉节点PU的电压抬升，并通过输 出子电路102，将被抬升的上拉节点PU的电压输出至信号输出端Output，即将被抬升的上拉节点PU的电压作为扫描信号。
由此可见，相比于相关技术中将时钟信号端CK1的高电平信号作为扫描信号通过信号输出端Output输出，(示例性地，时钟信号端的高电平信号(扫描信号)与本公开所提供的移位寄存器中的充电阶段的上拉节点PU的电位基本相同)，本公开中的移位寄存器，能够在第一时钟信号ck1的作用下，将上拉节点PU的电压抬升，并将被抬升的上拉节点PU的电压作为扫描信号输出至信号输出端Output，因此，采用本公开的一些实施例所提供的移位寄存器所输出的扫描信号的电压高于相关技术中的移位寄存器所输出的扫描信号的电压(时钟信号的高电平)。这样，能够在不提高时钟信号clk的高电平，不增大显示装置的功耗的前提下，提高扫描信号的电压，从而提高亚像素的充电率，更利于栅极驱动电路在高分辨率、大尺寸显示装置领域的应用。同时，在该移位寄存器所应用的显示装置的分辨率一定的情况下，由于扫描信号的电压得以提高，能够保证亚像素的充电率，亚像素中的像素驱动电路所包括的晶体管的尺寸可以减小，例如晶体管的宽长比可以降低，这样可以提高亚像素的开口率，提高显示效果。
示例性地，如图4和图5所示，输出控制子电路101包括第一晶体管T1，第一晶体管T1的控制极与上拉节点PU耦接，第一晶体管T1的第一极与第一时钟信号端CK1耦接，第一晶体管T1的第二极与第一储能子电路201耦接。第一晶体管T1被配置为在上拉节点的电压的控制下导通，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。
第一储能子电路201包括第一电容C1，第一电容C1的第一端与上拉节点PU耦接，第一电容C1的第二端与第一晶体管T1的第二极耦接。第一电容C1被配置为存储上拉节点PU的电压。
输出子电路102包括第二晶体管T2，第二晶体管T2的控制极与上拉节点PU耦接，第二晶体管T2的第一极与上拉节点PU耦接，第二晶体管T2的第二极与信号输出端Output耦接。第二晶体管T2被配置为在上拉节点的电压的控制下导通，并将被抬升的上拉节点PU的电压输出至信号输出端Output。
在一些实施例中，如图3～图5所示，移位寄存器还包括：下拉子电路103。
下拉子电路103与第二时钟信号端CK2、信号输出端Output和第一电压端VGL耦接，被配置为响应于在所述第二时钟信号端CK2处接收的第二时钟信号ck2，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。示例性地，第一电压信号vgl为低电平信号。
在上述移位寄存器中，在上拉节点PU的电压未被抬升的阶段，通过下拉子电路103将第一电压信号vgl输出至信号输出端Output，保证了移位寄存器在该阶段不输出扫描信号。
示例性地，如图4和图5所示，下拉子电路103包括第三晶体管T3，第三晶体管T3的控制极与第二时钟信号端CK2耦接，第三晶体管T3的第一极与第一电压端VGL耦接，第三晶体管T3的第二极与信号输出端Output耦接。第三晶体管T3被配置为在第二时钟信号ck2的控制下导通，将第一电压信号vgl传输至信号输出端Output。
在一些实施例中，如图3～图5所示，该移位寄存器还包括：第二储能子电路202；第二储能子电路202耦接于第一储能子电路201和信号输出端Output之间，被配置为在被抬升的上拉节点PU的电压输出至信号输出端Output的过程中，使上拉节点PU的电压保持稳定。
可以理解的是的，在被抬升的上拉节点PU的电压输出至信号输出端Output的过程中，由于漏电现象上拉节点PU的电压会缓慢降低，而信号输出端Output输出的扫描信号能够通过第二储能子电路202的与信号输出端耦接的一端，抬升第一储能子电路201的与第二储能子电路202耦接的一端的电压，进而通过第一储能子电路201进一步的提高了上拉节点PU的电压，从而使得漏电现象造成的上拉节点PU的电压的降低与上拉节点PU的电压的进一步抬升能够达到平衡，从而使得上拉节点PU的电压保持稳定，进而使得信号输出端Output输出的扫描信号更加稳定。
示例性地，如图4和图5所示，第二储能子电路包括第二电容C2，第二电容C2的第一端与信号输出端Output耦接；在第一储能子电路201包括第一电容C1的情况下，第二电容C2的第二端与第一电容C1的第二端耦接。
另外，本领域的技术人员可以理解的是，对于移位寄存器而言，除了上述提及的子电路以外，往往还包括其他的子电路，例如：输入子电路、多个控制子电路、复位子电路、降噪子电路等等，本公开对于其他子电路的具体设置情况不做具体限定，在满足移位寄存器正常工作的前提下，可以根据实际的需要选择设置。
在一些实施例中，该移位寄存器在包括前述的全部子电路或者部分子电路的基础上，如图3～图5所示，该移位寄存器还包括：输入子电路104和复位子电路105。
其中，上述输入子电路104与信号输入端Input、第二电压端VGH和上拉节点PU耦接。该输入子电路104被配置为在响应于在信号输入端Input处 接收的输入信号input，将在第二电压端VGH处接收的第二电压信号vgh传输至上拉节点PU。
上述复位子电路105与复位信号端Reset、第一电压端VGL和上拉节点PU耦接。该复位子电路105被配置为响应于在复位信号端Reset处接收的复位信号reset，将在第一电压端VGL处接收的第一电压信号vgl输出至上拉节点PU。
示例性地，如图4或图5所示，该输入子电路104包括第四晶体管T4。其中，第四晶体管T4的控制极与信号输入端Input耦接，第四晶体管T4的第一极与第二电压端VGH耦接，第四晶体管T4的第二极与上拉节点PU耦接。第四晶体管T4被配置为在输入信号input的控制下，将第二电压信号vgh传输至上拉节点PU。
该复位子电路105包括第五晶体管T5。其中，第五晶体管T5的控制极与复位信号端Reset耦接，第五晶体管T5的第一极与第一电压端VGL耦接，第五晶体管T5的第二极与上拉节点PU耦接。第五晶体管T5被配置为在复位信号reset的控制下，将第一电压信号vgl输出至上拉节点PU。
在一些实施例中，如图3～图5所示，移位寄存器还包括：下拉节点PD、节点控制子电路106、第一降噪子电路107和第二降噪子电路108。
在一些示例中，上述节点控制子电路106与第二电压端VGH、上拉节点PU、第一电压端VGL和下拉节点PD耦接。该节点控制子电路106被配置为响应于上拉节点PU的电压和在第二电压端VGH处接收的第二电压信号vgh，将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD；及，响应于上拉节点PU的电压和在第二电压端VGH处接收的第二电压信号vgh，将在第二电压端VGH处接收的第二电压信号vgh传输至下拉节点PD。
示例性地，如图4或图5所示，该第一控制子电路106包括第六晶体管T6和第七晶体管T7。
其中，第六晶体管T6的控制极与第二电压端VGH耦接，第六晶体管T6的第一极与第二电压端VGH耦接，第六晶体管T6的第二极与下拉节点PD耦接。第六晶体管T6被配置为在第二电压信号vgh的控制下导通，将第二电压信号vgh传输至下拉节点PD。
第七晶体管T7的控制极与上拉节点PU耦接，第七晶体管T7的第一极与第一电压端VGL耦接，第七晶体管T7的第二极与下拉节点PD耦接。第七晶体管T7被配置为在上拉节点PU的电压的控制下导通，将第一电压信号vgl传输至下拉节点PD。
在第一控制子电路106包括第六晶体管T6和第七晶体管T7的情况下，第一控制子电路106的功能实现过程为：第六晶体管T6在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的电压的控制下导通，第七晶体管T7将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD。以及，第六晶体管T6在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的电压的控制下关闭，第六晶体管T6将在第二电压端VGH处接收的第二电压信号vgh传输至下拉节点PD。
在本公开实施例中，“晶体管的尺寸”表示晶体管的沟道的宽长比。本领域技术人员了解，晶体管一般包括栅极、有源层、源极和漏极，此处，“沟道”是指晶体管的有源层在工作状态下，在其源极和漏极之间，有源层中所形成的载流子的流通通道。“沟道的宽长比”是指沟道的宽度与长度之比，其中沟道的长度指在从源极指向漏极(或漏极指向源极)的方向X上沟道的尺寸，沟道的宽度指在上述方向X的垂直方向上沟道的尺寸。
以第一电压端VGL为低电压端，第二电压端VGH为高电压端，且第六晶体管和第七晶体管均为NMOS为例，在上拉节点PU的电压为高电平的情况下，第六晶体管和第七晶体管均导通。可以通过设置第七晶体管T7的尺寸大于第六晶体管T6的尺寸，即第七晶体管T7的沟道的宽长比大于第六晶体管T6的沟道的宽长比，来实现控制下拉节点PD的电位。由于第七晶体管T7的沟道的宽长比大于第六晶体管T6的沟道的宽长比，可以视作第六晶体管T6的电阻大于第六晶体管T6的电阻，这样在第六晶体管T6在第二电压信号vgh的控制下导通，且第七晶体管T7被配置为在上拉节点PU的电压的控制下导通的情况下，第六晶体管T6的分压更大，使得下拉节点PD的电压降低，也即保证了在第六晶体管T6和第七晶体管T7均导通的情况下，下拉节点PD仍能维持在低电平，可以视作将第二电压信号vgl传输至下拉节点PD。
在一些示例中，上述第一降噪子电路107与上拉节点PU、下拉节点PD和第一电压端VGL耦接。该第一降噪子电路107被配置为在下拉节点PD的电压的控制下，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU，以实现对上拉节点PU进行降噪处理。
示例性地，如图4或图5所示，第一降噪子电路107包括第八晶体管T8。其中，第八晶体管T8的控制极与下拉节点PD连接，第八晶体管T8的第一极与第一电压端VGL耦接，第八晶体管T8的第二极与上拉节点PU耦接。第八晶体管T8被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至上拉节点PU。
在一些示例中，上述第二降噪子电路108与第一电压端VGL、下拉节点PD和信号输出端Output连接。该第二降噪子电路108被配置为在下拉节点PD的电压的控制下，将第一电压端VGL的第一电压信号vgl输出至信号输出端Output。
示例性地，如图4或图5所示，该第二降噪子电路108包括第九晶体管T9。其中，第九晶体管T9的控制极与下拉节点PD耦接，第九晶体管T9的第一极与第一电压端VGL耦接，第九晶体管T9的第二极与信号输出端Output耦接。第九晶体管T9被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至信号输出端Output。
在此基础上，下面对本公开实施例所提供的移位寄存器的具体电路结构进行整体性的、示例性的介绍。
如图4或图5所示，移位寄存器包括：上拉节点PU、输出控制子电路101、第一储能子电路201、输出子电路102、下拉子电路103、输入子电路104、复位子电路105、下拉节点PD、节点控制子电路106、第一降噪子电路107和第二降噪子电路108；其中，输出控制子电路101包括第一晶体管T1，输出子电路102包括第二晶体管T2，下拉子电路103包括第三晶体管T3，输入子电路104包括第四晶体管T4，复位子电路105包括第五晶体管T5，节点控制子电路106包括第六晶体管T6和第七晶体管T7，第一降噪子电路107包括第八晶体管T8，第二降噪子电路108包括第九晶体管T9，第一储能子电路201包括第一电容C1。
第一晶体管T1的控制极与上拉节点PU耦接，第一晶体管T1的第一极与第一时钟信号端CK1耦接，第一晶体管T1的第二极与第一电容C1的第二端耦接。第一晶体管T1被配置为在上拉节点PU的电压的控制下导通，将第一时钟信号ck1传输至第一电容C1的第二端。
第一电容C1的第一端与上拉节点PU耦接，还与第一晶体管T1的控制极耦接。第一电容C1被配置为存储上拉节点PU的电压。
第二晶体管T2的控制极与上拉节点PU耦接，第二晶体管T2的第一极与上拉节点PU耦接，第二晶体管T2的第二极与信号输出端Output耦接。第一晶体管T1被配置为在上拉节点PU的电压的控制下导通，将被抬升的上拉节点PU的电压输出至信号输出端Output。
第三晶体管T3的控制极与第二时钟信号端CK2耦接，第三晶体管T3的第一极与第一电压端VGL耦接，第三晶体管T3的第二极与信号输出端Output耦接。第三晶体管T3被配置为在第二时钟信号ck2的控制下导通，将第一电 压信号vgl输出至信号输出端Output。
第四晶体管T4的控制极与信号输入端Input耦接，第四晶体管T4的第一极与第二电压端VGH耦接，第四晶体管T4的第二极与上拉节点PU耦接。第四晶体管T4被配置为在输入信号input的控制下导通，将第二电压信号vgh传输至上拉节点PU。
第五晶体管T5的控制极与复位信号端Reset耦接，第五晶体管T5的第一极与第一电压端VGL耦接，所述第五晶体管T5的第二极与上拉节点PU耦接。第五晶体管T5被配置为在复位信号reset的控制下导通，将第一电压信号vgl传输至上拉节点PU。
第六晶体管T6的控制极与第二电压端VGH耦接，所述第六晶体管T6的第一极与第二电压端VGH耦接，所述第六晶体管T6的第二极与下拉节点PD耦接。第六晶体管T6被配置为在第二电压信号vgh的控制下导通，将第二电压信号vgh传输至下拉节点PD。
第七晶体管T7的控制极与上拉节点PU耦接，第七晶体管T7的第一极与第一电压端VGL耦接，第七晶体管T7的第二极与下拉节点PD耦接。第七晶体管T7被配置为在上拉节点PU的控制下导通，将第一电压信号vgl传输至下拉节点PD。
第八晶体管T8的控制极与下拉节点PD耦接，所述第八晶体管T8的第一极与第一电压端VGL耦接，第八晶体管T8的第二极与上拉节点PU耦接。第八晶体管T8被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至上拉节点PU。
第九晶体管T9的控制极与下拉节点PD耦接，第九晶体管T9的第一极与第一电压端VGL耦接，第九晶体管T9的第二级与信号输出端Output耦接。第八晶体管T8被配置为在下拉节点PD的电压的控制下导通，将第一电压信号vgl传输至信号输出端Output。
需要说明的是，本公开实施例中所提供的移位寄存器中所采用的晶体管可以为N型晶体管，也可以为P型晶体管，示例性地，本公开实施例中所提供的移位寄存器中的晶体管均的用N型晶体管。本公开实施例中所提供的移位寄存器中所采用的晶体管可以为增强型晶体管，也可以为耗尽型晶体管或者其他特性相同的开关器件。上述晶体管还可以采用非晶硅薄膜晶体管、多晶硅薄膜晶体管或非晶-氧化铟镓锌薄膜晶体管，本公开对此并不设限。
并且，上述移位寄存器中所采用的晶体管的控制极为晶体管的栅极，第一极可以为源极，第二极可以为漏极，或者上述晶体管的第一极可以为漏极， 第二极为源极，本公开对此均不作限定。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的一些实施例还提供一种栅极驱动电路，如图6所示，该栅极驱动电路包括至少两个级联的如前述的移位寄存器RS。示例性地，该栅极驱动电路包括n个级联的如前述的移位寄存器RS，分别为RS1～RSn。
具体的，该栅极驱动电路中，第一级移位寄存器RS1的信号输入端Input耦接起始信号端STV。
除了第一级移位寄存器RS1以外，任一级移位寄存器RS的信号输入端Input与该级移位寄存器RS的上一级移位寄存器RS的信号输出端Output耦接。例如，第二级移位寄存器RS2的信号输入端Input与第一级移位寄存器RS1的信号输出端Output耦接。第三级移位寄存器RS3的信号输入端Input与第二级移位寄存器RS2的信号输出端Output耦接。
除了最后一级移位寄存器RSn以外，任一级移位寄存器RS的复位信号端Reset与该级移位寄存器RS的下一级移位寄存器RS的信号输出端Output耦接。例如，第二级移位寄存器RS2的与第三级移位寄存器RS3的信号输出端Output耦接。第三级移位寄存器RS3的复位信号端Reset与第四级移位寄存器RS4的信号输出端Outpu耦接。
最后一级移位寄存器RSn的复位信号端Reset与单独设置的用于输出复位信号的信号端耦接，或者，与起始信号端耦接。(图6仅示意的以最后一级移位寄存器RSn的复位信号端Reset与单独设置的用于输出复位信号的信号端耦接为例进行说明)。
此处可以理解的是，每一级移位寄存器RS分别与显示面板中的一条栅线G耦接；示例性地，如图4所示，显示面板中包括n条栅线(n为正整数，例如n＝2000)。在此情况下，栅极驱动电路中也包括n级移位寄存器。一般的，第i级移位寄存器RSi与显示面板中第i条栅线Gi耦接，其中i为大于或等于1，且小于或等于n的正整数。
由于该栅极驱动电路包括如上所述的移位寄存器，具有与前述实施例提供的移位寄存器相同的结构和有益效果。由于前述实施例已经对移位寄存器的结构和有益效果进行了详细的描述，此处不再赘述。
本公开的一些实施例还提供一种显示装置，包括本公开所提供的上述栅极驱动电路，同样包括前述的移位寄存器，具有与前述实施例提供的移位寄存器相同的结构和有益效果。由于前述实施例已经对移位寄存器的结构和有益效果进行了详细的描述，此处不再赘述。
在一些示例中，本公开实施例所提供的显示装置为液晶显示装置，该液晶显示装置包括液晶显示面板，或者，本公开实施例所提供的显示装置有机发光二极管显示装置，该有机发光二极管显示装置包括有机发光二极管显示面板。本公开实施例所提供的显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开对此并不设限。
针对液晶显示装置而言，由于采用本公开的栅极驱动电路可以提高扫描信号的电压，从而提高了充电效率；基于此，实际在制作液晶显示面板时可以相应的减小亚像素内薄膜晶体管的尺寸(W/L，也即沟道的宽长比)，进而可以提高亚像素的开口率。
本公开的一些实施例还提供一种移位寄存器的驱动方法，该驱动方法应用于如本公开的一些实施例所提供的移位寄存器。
在移位寄存器包括上拉节点PU、输出控制子电路101、输出子电路102、和第一存储子电路201的情况下，如图7和图8所示，一个帧周期包括充电阶段S1和输出阶段S2：
充电阶段S1包括：
在上拉节点PU的电压的控制下，输出控制子电路101开启，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。此时，第一时钟信号ck1的电平为低电平。
第一储能子电路201存储上拉节点PU的电压。
示例性地，如图2所示，在输出控制子电路101包括第一晶体管T1，第一储能子电路201包括第一电容C1的情况下：
在充电阶段S1，第一晶体管T1在上拉节点PU的电压的控制下导通，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一电容C1的第二端，此时第一电容C1的第二端的电位为第一时钟信号ck1的低电平电位，例如为0V。第一电容C1存储上拉节点PU的电压，此时第一电容C1的第一端的电位为上拉节点PU的电压，例如为22V。
输出阶段S2包括：
在上拉节点PU的电压控制下，输出控制子电路101开启，将在第一时钟 信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。此时，第一时钟信号ck1的电平为高电平。
第一储能子电路201响应于第一时钟信号ck1，抬升上拉节点PU的电压。
输出子电路102在上拉节点PU的电压的控制下，将被抬升的上拉节点PU的电压传输至信号输出端Output。
示例性地，如图2所示，在输出控制子电路101包括第一晶体管T1，第一储能子电路201包括第一电容C1，输出子电路102包括第二晶体管T2的情况下：
在输出阶段S2，第一晶体管T1在上拉节点PU的电压的控制下导通，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一电容C1的第二端，此时第一电容C1的第二端的电位为第一时钟信号ck1的高电平电位，例如为22V。由于第一电容C1的第二端的电位升高，根据电容的自举作用，第一电容C1的第一端的电位也随之升高，理论上第一电容C1的第一端的电位由可以22V变为44V，实现了抬升上拉节点PU的电压。需要说明的是，在实际电路结构中，示例性地，上拉节点PU的电压被抬升至30V。第二晶体管T2在上拉节点PU的电压的控制下导通，将被抬升的上拉节点PU的电压(30V)传输至信号输出端Output。
需要说明的是，信号输出端Output仅在输出阶段S2输出扫描信号，在充电阶段，信号输出端Output不输出扫描信号。
在一些实施例中，输出子电路102所包括的第二晶体管T2的阈值电压较高，在充电阶段S1上拉节点PU的电压不能使得第二晶体管T2导通，无法将上拉节点PU的电压传输至信号输出端。
在另一些实施例中，在移位寄存器还包括下拉子电路103的情况下，充电阶段S1还包括：在第二时钟信号端CK2传输的第二时钟信号ck2的控制下，下拉子电路103开启，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。这样同样能够保证移位寄存器在充电阶段S1不输出扫描信号。
采用上述移位寄存器的驱动方法，在输出阶段S2，输出子电路102将被抬升的上拉节点PU的电压输出至信号输出端Output，即将被抬升的上拉节点PU的电压作为扫描信号，实现了在不提高时钟信号clk的高电平，不增大显示装置的功耗的前提下，提高了扫描信号的电压，从而提高亚像素的充电率，更利于栅极驱动电路在高分辨率、大尺寸显示装置领域的应用。
在一些实施例中，在移位寄存器还包括第二储能子电路202的情况下， 输出阶段S2还包括：
第二储能子电路202在被抬升的上拉节点PU的电压输出至信号输出端Output的过程中，使上拉节点PU的电压保持稳定。
示例性地，在该输出阶段S2，信号输出端Output输出抬升后的上拉节点PU的电压，从而可以抬升第二电容C2与信号输出端Output耦接的一端(第二电容C2的第二端)的电压，在第二电容C2和第一电容C1的自举作用下，进一步的抬升了上拉节点PU的电压，从而使得漏电现象造成的上拉节点PU的电压的降低与上拉节点PU的电压的进一步抬升能够达到平衡，从而使得上拉节点PU的电压保持稳定，进而使得信号输出端Output输出的扫描信号更加稳定。
在一些实施例中，如图4、图5、图7以及图8所示，在移位寄存器还包括下拉子电路104、下拉节点PD、输入子电路104、复位子电路105、节点控制子电路106、第一降噪子电路107和第二降噪子电路108的情况下，该移位寄存器的驱动方法的整个流程包括充电阶段S1、输出阶段S2、复位阶段S3和降噪阶段S4。
充电阶段S1包括：
在信号输入端Input传输的输入信号input的控制下，输入子电路104开启，将在第二电压端VGH处接收的第二电压信号vgh传输至上拉节点PU。
在一些示例中，对于第一级移位寄存器而言，信号输入端Input处的输入信号input为STV信号(Start Vertical，栅的启动信号)，对于第一级以外的移位寄存器而言，该输入信号input为前一级移位寄存器的输出信号output。
在上拉节点PU的电压的控制下，输出控制子电路101开启，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。此时，第一时钟信号ck1的电平为低电平。
第一储能子电路201存储上拉节点PU的电压。
在第二时钟信号端CK2传输的第二时钟信号ck2的控制下，下拉子电路103开启，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。
节点控制子电路106响应于上拉节点PU的电压和在第二电压端处VGH接收的第二电压信号vgh，将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD，使得此时下拉节点PD的电压为低电平。
第一降噪子电路107和第二降噪子电路108在下拉节点PD的电压的控制下关闭，复位子电路105在复位信号reset的控制下关闭。
示例性地，如图4或图5所示，在输出控制子电路101包括第一晶体管T1，输出子电路102包括第二晶体管T2，下拉子电路103包括第三晶体管T3，输入子电路104包括第四晶体管T4，复位子电路105包括第五晶体管T5，节点控制子电路106包括第六晶体管T6和第七晶体管T7，第一降噪子电路107包括第八晶体管T8，第二降噪子电路108包括第九晶体管T9，第一储能子电路201包括第一电容C1的情况下，充电阶段S1包括：
第四晶体管T4在输入信号input的控制下导通，将在第二电压端VGH处接收的第二电压信号vgh传输至上拉节点PU，并传输至第一电容C1的第一端。第一晶体管T1在上拉节点PU的电压的控制下导通，将第一时钟信号ck1传输至第一电容C1的第二端，此时第一时钟信号ck1的电平为低电平。
第七晶体管T7在上拉节点PU的高电平的控制下导通，将在第一电压端VGL处接收的第一电平信号vgl输出至下拉节点PD。需要说明的是，由于第七晶体管T7的尺寸大于第六晶体管T6的尺寸，因此即使第六晶体管T6在第二电压信号vgh的控制下处于导通状态，第一电压端VGL的第一电平信号vgl(低电平)仍然能够保证下拉节点PD维持低电位。
在一些示例中，在上拉节点PU的电压的控制下，第二晶体管T2导通；同时第三晶体管T3在第二时钟信号端CK2的高电平的控制下导通，将在第一电压端VGL处接收的第一电平信号vgl传输至信号输出端Output，在第三晶体管T3的尺寸大于第二晶体管T2的尺寸的情况下，第一电压端VGL的第一电平信号vgl(低电平)仍然能够保证信号输出端Output维持低电位，从而保证信号输出端Output在该充电阶段S1输出第一电平信号vgl(低电平)。
在另一些示例中，第二晶体管T2的阈值电压较高，在充电阶段S1，上拉节点PU的电压的不能使第二晶体管T2导通，即第二晶体管T2截止。第三晶体管T3在第二时钟信号端CK2的高电平的控制下导通，将在第一电压端VGL处接收的第一电平信号vgl传输至信号输出端Output。
第五晶体管T5、第八晶体管T8和第九晶体管T9在该充电阶段S1均截止。
输出阶段S2包括：
上拉节点PU的电压控制下，输出控制子电路101开启，将在第一时钟信号端CK1处接收的第一时钟信号ck1传输至第一储能子电路201。由于在充电阶段S1第一储能子电路201存储上拉节点PU的电压，因此在输出阶段S2第一储能子电路201对上拉节点PU进行放电，使得上拉节点PU的电压仍然为高电压，能够使得输出控制子电路101打开。此阶段，第一时钟信号ck1 的电平为高电平。
第一储能子电路201响应于第一时钟信号ck1，抬升上拉节点PU的电压。
在上拉节点PU的电压的控制下，输出子电路102开启，将被抬升的上拉节点PU的电压传输至信号输出端Output。
节点控制子电路106响应于上拉节点PU的电压和在第二电压端处VGH接收的第二电压信号vgh，将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD，此时下拉节点PD的电压为低电平。
在该输出阶段S2，在第二时钟信号ck2(该阶段第二时钟信号ck2的电平为低电平)的控制下，下拉子电路103关闭；输入子电路104在输入信号input的控制下关闭，第一降噪子电路107和第二降噪子电路108在下拉节点PD的电压的控制下关闭，复位子电路105在复位信号reset的控制下关闭。
示例性地，如图4或图5所示，在输出控制子电路101包括第一晶体管T1，输出子电路102包括第二晶体管T2，下拉子电路103包括第三晶体管T3，输入子电路104包括第四晶体管T4，复位子电路105包括第五晶体管T5，节点控制子电路106包括第六晶体管T6和第七晶体管T7，第一降噪子电路107包括第八晶体管T8，第二降噪子电路108包括第九晶体管T9，第一储能子电路201包括第一电容C1的情况下，输出阶段S2包括：
第一电容C1将充电阶段S1存储的电压放电至上拉节点PU，在上拉节点PU的电压的控制下，第三晶体管T3导通，将在第一时钟信号端CK1处接收的第一时钟信号信号(高电平信号)输出至第一电容C1的第二端，在第一电容C1的自举作用下，第一电容C1的第一端的电位抬升，从而抬升上拉节点PU的电压。在此情况下，在抬升后的上拉节点PU的电压的控制下，第二晶体管T2导通，并将该抬升后的上拉节点PU的电压(作为扫描信号)输出至信号输出端Output。
另外，在该输出阶段S2，第六晶体管T6和第五晶体管T7保持导通状态(同充电阶段S1)，使得下拉节点PD的电位维持低电位。第三晶体管T3、第四晶体管T4、第五晶体管T5、第八晶体管T8和第九晶体管T9均处于截止状态。
此处需要说明的是，对于上述第一电容C1的自举作用下，使得上拉节点PU的电位抬升而言，在第一电压信号vgh的电平与第一时钟信号ck1的高电平相等的情况下，例如均为22V，理论上上拉节点PU的电位可以抬升至第一时钟信号端CK1的高电平的2倍；在实际模拟中，并不绝对可以达到第一时钟信号端CK1的高电平的2倍。例如，以第一时钟信号端CK1的高电平为 22V时，通过第一电容C1的自举作用，上拉节点PU的电压抬升到30V。可以看出，采用本公开中的移位寄存器可以抬升上拉节点PU的电压，进而可以提高信号输出端Output的扫描信号的电压。
如图7所示，所述驱动方法还包括：位于输出阶段S2之后的复位阶段S3，复位阶段S3包括：
在复位信号端Reset传输的复位信号reset的控制下，复位子电路105开启，将在第一电压端VGL处接收的第一电压信号vgl输出至上拉节点PU。此时上拉节点PU的电压为低电平，输出子电路102在上拉节点PU的电压的控制下关闭，停止将上拉节点PU的电压输出至信号输出端Output。
节点控制子电路106响应于上拉节点PU的电压和在第二电压端VGH处接收的第二电压信号vgh，将在所第二电压端VGH处接收的第二电压信号vgh传输至所下拉节点PD。此时下拉节点PD的电压为高电压。
在下拉节点PD的电压的控制下，第一降噪子电路107开启，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU。
在下拉节点PD的电压的控制下，第二降噪子电路108开启，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。
在第二时钟信号端CK2传输的第二时钟信号ck2的控制下，下拉子电路103开启，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。
输出控制子电路101和输出子电路102在上拉节点PU的电压的控制下均关闭。
示例性地，如图4或图5所示，在输出控制子电路101包括第一晶体管T1，输出子电路102包括第二晶体管T2，下拉子电路103包括第三晶体管T3，输入子电路104包括第四晶体管T4，复位子电路105包括第五晶体管T5，节点控制子电路106包括第六晶体管T6和第七晶体管T7，第一降噪子电路107包括第八晶体管T8，第二降噪子电路108包括第九晶体管T9，第一储能子电路201包括第一电容C1的情况下，复位阶段S3包括：
第五晶体管T5在复位信号端Reset传输的高电平的复位信号reset的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU，使得上拉节点PU的电压降低，实现复位。在上拉节点PU的电压的控制下，第七晶体管T7截止，第六晶体管T6在第二电压端VGH传输的第二电压信号vgh的控制下导通，将第二电压信号vgh输出至下拉节点PD，使得下拉节点PD的电压升高。在下拉节点PD的电压的控制下，第八晶体管T8导通，将 在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU进行复位；同时，在下拉节点PD的电压的控制下，第九晶体管T9导通，将在第一电压端VGL处接收的第一电压信号vgl输出至信号输出端Output进行复位。
另外，在该复位阶段S3，中，在第二时钟信号端CK2传输的第二时钟信号ck2(此阶段为高电平)的控制下，第三晶体管T3导通，将在第一电压端VGL处接收的第一电压信号vgl输出至信号输出端Output。
第一晶体管T1、第二晶体管T2和第四晶体管T4在该复位阶段S3均处于截止状态。
在复位阶段S3之后、下一个帧周期之前，移位寄存器进入降噪阶段S4，在该降噪阶段S4包括：
在下拉节点PD的电压的控制下，第二降噪子电路108开启，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output，对信号输出端Output进行持续降噪。
下拉子电路103在第二时钟信号ck2的控制下，周期性的开启和关闭，在下拉子电路103开启时，能够将在第一电压端VGL处接收的第一电压信号vgl输出至信号输出端Output，同样可以起到降噪的作用。
另外，节点控制子电路106响应于上拉节点PU的电压和在第二电压端VGH处接收的第二电压信号vgh，将第二电压端VGH处接收的第二电压信号vgh输出至下拉节点PD，使得下拉节点PD的电位升高。在下拉节点PD的电压的控制下，第一降噪子电路107开启，将第一电压端VGL的电压输出上拉节点PU。
输出子电路102、输出控制子电路101、输入子电路104在该降噪阶段S4均处于关闭状态。
示例性地，如图4或图5所示，在输出控制子电路101包括第一晶体管T1，输出子电路102包括第二晶体管T2，下拉子电路103包括第三晶体管T3，输入子电路104包括第四晶体管T4，复位子电路105包括第五晶体管T5，节点控制子电路106包括第六晶体管T6和第七晶体管T7，第一降噪子电路107包括第八晶体管T8，第二降噪子电路108包括第九晶体管T9，第一储能子电路201包括第一电容C1的情况下，降噪阶段S4包括：
第九晶体管T9在下拉节点PD的电压的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl输出至信号输出端Output进行降噪。第三晶体管T3在第二时钟信号端CK2(高、低电平)的控制下，周期性导通和截止，在第三晶体管T3导通时，将在第一电压端VGL处接收的第一电压信号vgl 输出至信号输出端Output进行降噪。
在降噪阶段S4中，第六晶体管T6在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的控制下关闭，将在第二电压端VGH处接收的第二电压信号vgh传输至下拉节点PD。第八晶体管T8在下拉节点PD的控制下处于导通状态。第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第七晶体管T7均处于截止状态。
以上实施例中晶体管的导通与截止过程均是以所有晶体管为N型晶体管，第一电压端VGL为低电平电压端，第二电压端VGH为高电平电压端，且第一时钟信号ck1和第二时钟信号ck2的占空比均为百分之五十，第一时钟信号ck1和第二时钟信号ck2的高低电平变化完全相反为例进行的说明。当所有晶体管均为P型时，需要对图5中各个控制信号、第一电压端、第二电压端进行翻转即可。
本公开的一些实施例还提供了上述移位寄存器的另一种驱动方法，该驱动方法基于第一时钟信号ck1和第二时钟信号ck2的占空比均小于百分之五十的情况，即在电平变化的一个周期内，高电平所占的时间比例小于低电平所占的时间比例。下面以图4和图5所示出的移位寄存器为例，且所有移位寄存器中包括的所有晶体管为N型晶体管，第一电压端VGL为低电平电压端，第二电压端VGH为高电平电压端对该驱动方法进行示例性说明。移位寄存器所包括的具体电路结构可参见上面的说明，此处不再赘述。
如图9所示，该驱动方法包括：充电阶段S1’、输出阶段S2’、第一复位阶段S3’和第二复位阶段S4’。
充电阶段S1’包括：
输入信号端Input传输的输入信号input的电平为高电平，第四晶体管T4在输入信号input的控制下导通，将在第二电压端VGH处接收的第二电压信号vgh传输至上拉节点PU，使上拉节点PU的电压为第二电压信号vgh的电压，例如为22V。
第一晶体管在上拉节点PU的电压的控制下导通，将在第一时钟信号端CK1处接收的第一时钟信号ck1(此时第一时钟信号ck1的电平为低电平，例如为0V)传输至第一电容C1的第二端。同时第一电容C1存储上拉节点PU的电压，第一电容C1的第一端的电压为上拉节点PU的电压。
在一些示例中，第二晶体管T2在上拉节点PU的电压的控制下导通，将上拉节点PU的电压传输至信号输出端Output，由于栅极驱动电路是提前几行打开栅线，因此即使第二晶体管T2导通，像素中所包括的像素驱动电路也不 会接收数据信号，像素不会进行充电，因此在充电阶段S1’传输至信号输出端Output的电压对像素充电没有影响。
第二时钟信号端CK2处的第二时钟信号ck2的电平为低电平，第三晶体管T3在第二时钟信号ck2的控制下截止。复位信号端Reset处的复位信号reset的电平为低电平，第五晶体管T5在复位信号reset的控制下截止。
第六晶体管在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的电压的控制下导通，第七晶体管T7将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD，由于第七晶体管T7的尺寸大于第六晶体管的尺寸，因此下拉节点PD的电位为低电位(此处的原理可参见上面的描述)。
第八晶体管T8和第九晶体管T9均在下拉节点PD的电压的控制下截止。
输出阶段S2’包括：
在第一电容C1的作用下，上拉节点PU的电压依旧维持高电平(例如为22V)，第一晶体管T1在上拉节点PU的电压的控制下导通，将在第一时钟信号端CK1处接收的第一时钟信号ck1(此时第一时钟信号ck1的电平为高电平，例如为22V)传输至第一电容C1的第二端，在第一电容C1的自举作用下，第一电容C1的第一端的电压抬升，从而抬升上拉节点PU的电压，例如理论上上拉节点PU的电压可以抬升为44V。
第二晶体管T2在上拉节点PU的电压的控制下导通，将抬升后的上拉节点PU的电压传输至信号输出端Output，作为扫描信号输出。
同时，参见图5，由于第二电容C2的第二端与信号输出端Output耦接，在第二晶体管T2将抬升后的上拉节点PU的电压传输至信号输出端Output的过程中，在第二电容C2和第一电容C1的自举作用下，上拉节点PU的电压能够进一步抬升，从而使得漏电现象造成的上拉节点PU的电压的降低与上拉节点PU的电压的进一步抬升能够达到平衡，从而使得上拉节点PU的电压保持稳定。
第二时钟信号端CK2处的第二时钟信号ck2的电平为低电平，第三晶体管T3在第二时钟信号ck2的控制下截止。复位信号端Reset传输的复位信号reset的电平为低电平，第五晶体管T5在复位信号reset的控制下截止。
第六晶体管在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的电压的控制下导通，第七晶体管T7将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD，使得下拉节点PD的电位保持低电位。
第八晶体管T8和第九晶体管T9均在下拉节点PD的电压的控制下截止。
第一复位阶段S3’包括：
第一时钟信号端CK1传输的第一时钟信号ck1的电平为低电平，上拉节点PU的电压仍然为高电压，第一晶体管T1在上拉节点PU的电压的控制下导通，将第一时钟信号ck1传输至第一电容C1的第二端，在电容的自举作用下，第一电容C1的第一端的电位拉低，从而拉低上拉节点PU的电压。同时。第一晶体管T1将第一时钟信号ck1传输至第二电容C1的第一端，在电容的自举作用下，第二电容C2的第二端的电位拉低，从而信号输出端Output的电位也会降低。
另外，在该阶段，第二时钟信号端CK2传输的第二时钟信号ck2的电平仍为低电平，第三晶体管T3在第二时钟信号ck2的控制下截止。复位信号端Reset处的复位信号reset的电平抬升，但是该电位不足以使第五晶体管T5导通，第五晶体管T5在复位信号reset的控制下依旧截止。
第六晶体管在第二电压信号vgh的控制下导通，第七晶体管T7在上拉节点PU的电压的控制下导通，第七晶体管T7将在第一电压端VGL处接收的第一电压信号vgl传输至下拉节点PD，使得下拉节点PD的电位保持低电位。
第八晶体管T8和第九晶体管T9均在下拉节点PD的电压的控制下截止。
第二复位阶段S4’包括：
复位信号端Reset传输的复位信号reset的电平进一步抬升，第五晶体管T5在复位信号reset的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU，使上拉节点PU的电压拉低，从而在上拉节点PU的电压的控制下，第一晶体管T1截止，第二晶体管T2截止，第七晶体管T7截止。
第六晶体管在第二电压信号vgh的控制下保持导通，将在第二电压端VGH处接收的第二电压信号vgh传输至下拉节点PD，使下拉节点PD的电位升高。第八晶体管T8在下拉节点PD的电压的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl传输至上拉节点PU。第九晶体管T9在下拉节点PD的电压的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。
第二时钟信号端CK2传输的第二时钟信号ck2的电平为高电平，第三晶体管T3在第二时钟信号ck2的控制下导通，将在第一电压端VGL处接收的第一电压信号vgl传输至信号输出端Output。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读 取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种移位寄存器，包括：上拉节点、输出控制子电路、第一储能子电路和输出子电路；其中，
    所述输出控制子电路与所述上拉节点、第一时钟信号端和所述第一储能子电路耦接；所述输出控制子电路被配置为，在所述上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一储能子电路；
    所述第一储能子电路与所述上拉节点和所述输出控制子电路耦接；所述第一储能子电路被配置为，存储所述上拉节点的电压，及在所述第一时钟信号的作用下，抬升所述上拉节点的电压；
    所述输出子电路与所述上拉节点和信号输出端耦接；所述输出子电路被配置为，在所述上拉节点的电压的控制下，将被抬升的所述上拉节点的电压输出至所述信号输出端。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述输出控制子电路包括第一晶体管，所述第一晶体管的控制极与所述上拉节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第一储能子电路耦接；
    所述第一储能子电路包括第一电容，所述第一电容的第一端与所述上拉节点耦接，所述第一电容的第二端与所述第一晶体管的第二极耦接；
    所述输出子电路包括第二晶体管，所述第二晶体管的控制极与所述上拉节点耦接，所述第二晶体管的第一极与所述上拉节点耦接，所述第二晶体管的第二极与所述信号输出端耦接。
  3. 根据权利要求1或2所述的移位寄存器，还包括：下拉子电路；
    所述下拉子电路与第二时钟信号端、所述信号输出端和第一电压端耦接，被配置为响应于在所述第二时钟信号端处接收的第二时钟信号，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
  4. 根据权利要求3所述的移位寄存器，其中，所述下拉子电路包括第三晶体管，所述第三晶体管的控制极与所述第二时钟信号端耦接，所述第三晶体管的第一极与所述第一电压端耦接，所述第三晶体管的第二极与所述信号输出端耦接。
  5. 根据权利要求1～3中任一项所述的移位寄存器，还包括：第二储能子电路；
    所述第二储能子电路耦接于所述第一储能子电路和所述信号输出端之间，被配置为在被抬升的所述上拉节点的电压输出至所述信号输出端的过程 中，使所述上拉节点的电压保持稳定。
  6. 根据权利要求5所述的移位寄存器，其中，所述第二储能子电路包括第二电容，所述第二电容的第一端与所述信号输出端耦接；在所述第一储能子电路包括第一电容的情况下，所述第二电容的第二端与所述第一电容的第二端耦接。
  7. 根据权利要求1～6中任一项所述的移位寄存器，还包括：输入子电路和复位子电路；
    所述输入子电路与信号输入端、第二电压端和所述上拉节点耦接，被配置为响应于在所述信号输入端处接收的输入信号，将在所述第二电压端处接收的第二电压信号传输至所述上拉节点；
    所述复位子电路与复位信号端、第一电压端和所述上拉节点耦接，被配置为响应于在所述复位信号端处接收的复位信号，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点。
  8. 根据权利要求7所述的移位寄存器，其中，
    所述输入子电路包括第四晶体管，所述第四晶体管的控制极与所述信号输入端耦接，所述第四晶体管的第一极与所述第二电压端耦接，所述第四晶体管的第二极与所述上拉节点耦接；
    所述复位子电路包括第五晶体管，所述第五晶体管的控制极与所述复位信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述上拉节点耦接。
  9. 根据权利要求7或8所述的移位寄存器，还包括：下拉节点、
    节点控制子电路、第一降噪子电路和第二降噪子电路；
    所述节点控制子电路与所述第二电压端、所述上拉节点、所述第一电压端和所述下拉节点耦接；
    所述节点控制子电路被配置为响应于所述上拉节点的电压和在所述第二电压端处接收的第二电压信号，将在所述第一电压端处接收的第一电压信号传输至所述下拉节点；及，响应于所述上拉节点的电压和在所述第二电压端处接收的第二电压信号，将在所述第二电压端处接收的第二电压信号传输至所述下拉节点；
    所述第一降噪子电路与所述上拉节点、所述下拉节点和所述第一电压端耦接，被配置为在所述下拉节点的电压的控制下，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点；
    所述第二降噪子电路与所述下拉节点、所述第一电压端和所述信号输出 端耦接，被配置为在所述下拉节点的电压的控制下，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
  10. 根据权利要求9所述的移位寄存器，其中，
    所述节点控制子电路包括第六晶体管和第七晶体管；所述第六晶体管的控制极与所述第二电压端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述下拉节点耦接；所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第二电压端耦接，所述第七晶体管的第二极与所述下拉节点耦接；
    所述第一降噪子电路包括第八晶体管，所述第八晶体管的控制极与所述下拉节点耦接，所述第八晶体管的第一极与所述第二电压端耦接，所述第八晶体管的第二极与所述上拉节点耦接；
    所述第二降噪子电路包括第九晶体管，所述第九晶体管的控制极与所述下拉节点耦接，所述第九晶体管的第一极与所述第二电压端耦接，所述第九晶体管的第二极与所述信号输出端耦接。
  11. 根据权利要求10所述的移位寄存器，其中，所述第七晶体管的尺寸大于所述第六晶体管的尺寸。
  12. 根据权利要求1～11中任一项所述的移位寄存器，包括：上拉节点、输出控制子电路、第一储能子电路、输出子电路、下拉子电路、输入子电路、复位子电路、下拉节点、节点控制子电路、第一降噪子电路和第二降噪子电路；其中，
    所述输出控制子电路包括第一晶体管，所述第一储能子电路包括第一电容，所述输出子电路包括第二晶体管，所述下拉子电路包括第三子电路，所述输入子电路包括第四晶体管，所述复位子电路包括第五晶体管，所述节点控制子电路包括第六晶体管和第七晶体管，所述第一降噪子电路包括第八晶体管，所述第二降噪子电路包括第九晶体管；
    所述第一晶体管的控制极与所述上拉节点耦接，所述第一晶体管的第一极与所述第一时钟信号端耦接，所述第一晶体管的第二极与所述第一电容的第二端耦接；
    所述第一电容的第一端与所述上拉节点耦接，还与所述第一晶体管的控制极耦接；
    所述第二晶体管的控制极与所述上拉节点耦接，所述第二晶体管的第一极与所述上拉节点耦接，所述第二晶体管的第二极与所述信号输出端耦接；
    所述第三晶体管的控制极与第二时钟信号端耦接，所述第三晶体管的第 一极与第一电压端耦接，所述第三晶体管的第二极与所述信号输出端耦接；
    所述第四晶体管的控制极与信号输入端耦接，所述第四晶体管的第一极与第二电压端耦接，所述第四晶体管的第二极与所述上拉节点耦接；
    所述第五晶体管的控制极与复位信号端耦接，所述第五晶体管的第一极与所述第一电压端耦接，所述第五晶体管的第二极与所述上拉节点耦接；
    所述第六晶体管的控制极与所述第二电压端耦接，所述第六晶体管的第一极与所述第二电压端耦接，所述第六晶体管的第二极与所述下拉节点耦接；
    所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第一电压端耦接，所述第七晶体管的第二极与所述下拉节点耦接；
    所述第八晶体管的控制极与所述下拉节点耦接，所述第八晶体管的第一极与所述第一电压端耦接，所述第八晶体管的第二极与所述上拉节点耦接；
    所述第九晶体管的控制极与所述下拉节点耦接，所述第九晶体管的第一极与所述第一电压端耦接，所述第九晶体管的第二级与所述信号输出端耦接。
  13. 一种栅极驱动电路，包括至少两个级联的如权利要求1～12中任一项所述的移位寄存器；
    第一级移位寄存器的信号输入端耦接起始信号端；
    除了所述第一级移位寄存器以外，任一级移位寄存器的信号输入端与该级移位寄存器的上一级移位寄存器的信号输出端耦接；
    除了最后一级移位寄存器以外，任一级移位寄存器的复位信号端与该级移位寄存器的下一级移位寄存器的信号输出端耦接；
    所述最后一级移位寄存器的复位信号端与单独设置的用于输出复位信号的信号端耦接，或者，与所述起始信号端耦接。
  14. 一种显示装置，包括如权利要求13所述的栅极驱动电路。
  15. 一种移位寄存器的驱动方法，应用于如权利要求1～12中任一项所述的移位寄存器，所述驱动方法包括：一个帧周期包括充电阶段和输出阶段，
    所述充电阶段包括：
    在上拉节点的电压的控制下，输出控制子电路开启，将在第一时钟信号端处接收的第一时钟信号传输至第一储能子电路；
    所述第一储能子电路存储所述上拉节点的电压；
    所述输出阶段包括：
    在所述上拉节点的电压控制下，输出控制子电路开启，将所述第一时钟信号传输至所述第一储能子电路；
    所述第一储能子电路响应于所述第一时钟信号，抬升所述上拉节点的电 压；
    输出子电路在所述上拉节点的电压的控制下，将被抬升的所述上拉节点的电压传输至信号输出端。
  16. 根据权利要求15所述的驱动方法，其中，在所述移位寄存器还包括下拉子电路的情况下，所述充电阶段还包括：
    在第二时钟信号端传输的第二时钟信号的控制下，所述下拉子电路开启，将在第一电压端处接收的第一电压信号传输至所述信号输出端。
  17. 根据权利要求15或16所述的驱动方法，其中，在所述移位寄存器还包括第二储能子电路的情况下，所述输出阶段还包括：
    所述第二储能子电路在被抬升的所述上拉节点的电压输出至所述信号输出端的过程中，使所述上拉节点的电压保持稳定。
  18. 根据权利要求16所述的驱动方法，其中，在所述移位寄存器还包括下拉节点、输入子电路、复位子电路、节点控制子电路、第一降噪子电路和第二降噪子电路的情况下，
    所述充电阶段还包括：
    在信号输入端传输的输入信号的控制下，所述输入子电路开启，将在第二电压端处接收的第二电压信号传输至所述上拉节点；
    所述节点控制子电路响应于所述上拉节点的电压及在所述第二电压端处接收的第二电压信号，将在所述第一电压端处接收的第一电压信号传输至所述下拉节点；
    所述驱动方法还包括：位于所述输出阶段之后的复位阶段，所述复位阶段包括：
    在复位信号端传输的复位信号的控制下，所述复位子电路开启，将在所述第一电压端处接收的第一电压信号输出至所述上拉节点；
    所述节点控制子电路响应于所述上拉节点的电压及在所述第二电压端处接收的第二电压信号，将在所述第二电压端处接收的第二电压信号传输至所述下拉节点；
    在所述下拉节点的电压的控制下，所述第一降噪子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述上拉节点；
    在所述下拉节点的电压的控制下，所述第二降噪子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端；
    在所述第二时钟信号端传输的第二时钟信号的控制下，所述下拉子电路开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端；
    所述驱动方法还包括：位于所述复位阶段之后、下一个帧周期之前的降噪阶段，所述降噪阶段包括：
    在所述下拉节点的电压的控制下，所述第二降噪子电路保持开启，将在所述第一电压端处接收的第一电压信号传输至所述信号输出端。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109584832B (zh) * 2019-01-18 2020-10-27 重庆京东方光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110910853B (zh) * 2019-12-19 2021-10-29 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111223452B (zh) * 2020-03-18 2021-07-23 深圳市华星光电半导体显示技术有限公司 Goa电路
CN111508433B (zh) * 2020-05-28 2021-08-31 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
CN113035258B (zh) * 2021-03-09 2024-08-09 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示面板
CN114283746B (zh) * 2021-12-29 2023-05-23 上海中航光电子有限公司 一种显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103093825A (zh) * 2013-01-14 2013-05-08 北京京东方光电科技有限公司 一种移位寄存器及阵列基板栅极驱动装置
CN105632446A (zh) * 2016-03-30 2016-06-01 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN105976755A (zh) * 2016-07-19 2016-09-28 京东方科技集团股份有限公司 一种显示驱动电路及其控制方法、显示装置
CN106409207A (zh) * 2016-10-27 2017-02-15 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
KR20170105173A (ko) * 2016-03-08 2017-09-19 엘지디스플레이 주식회사 공통전압 보상회로를 구비한 액정 표시장치
CN107578741A (zh) * 2017-09-28 2018-01-12 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN109584832A (zh) * 2019-01-18 2019-04-05 重庆京东方光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103208263B (zh) * 2013-03-14 2015-03-04 京东方科技集团股份有限公司 移位寄存器、显示装置、栅极驱动电路及驱动方法
CN104376826B (zh) * 2014-11-20 2017-02-01 深圳市华星光电技术有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104392704A (zh) * 2014-12-15 2015-03-04 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
KR102276866B1 (ko) * 2014-12-31 2021-07-12 엘지디스플레이 주식회사 게이트 구동회로와 이를 포함하는 터치 스크린 일체형 표시장치
CN105654991B (zh) * 2016-01-19 2019-08-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、goa电路以及显示装置
CN108564908B (zh) * 2018-01-31 2021-05-11 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103093825A (zh) * 2013-01-14 2013-05-08 北京京东方光电科技有限公司 一种移位寄存器及阵列基板栅极驱动装置
KR20170105173A (ko) * 2016-03-08 2017-09-19 엘지디스플레이 주식회사 공통전압 보상회로를 구비한 액정 표시장치
CN105632446A (zh) * 2016-03-30 2016-06-01 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN105976755A (zh) * 2016-07-19 2016-09-28 京东方科技集团股份有限公司 一种显示驱动电路及其控制方法、显示装置
CN106409207A (zh) * 2016-10-27 2017-02-15 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN107578741A (zh) * 2017-09-28 2018-01-12 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN109584832A (zh) * 2019-01-18 2019-04-05 重庆京东方光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

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