WO2018037530A1

WO2018037530A1 - Semiconductor device and production method therefor

Info

Publication number: WO2018037530A1
Application number: PCT/JP2016/074818
Authority: WO
Inventors: 南條　拓真; 哲郎林田; 古川　彰彦
Original assignee: 三菱電機株式会社
Priority date: 2016-08-25
Filing date: 2016-08-25
Publication date: 2018-03-01
Also published as: JPWO2018037530A1

Abstract

The objective of the invention is to provide a technique allowing a sufficiently large drain current to be obtained for a semiconductor device in normally-OFF operation. This semiconductor device comprises: a channel layer 3a containing Al_x1In_y1Ga_1-x1-y1N (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1); a source electrode 5 and a drain electrode 6 formed in such a manner as to be separated from one another on the surface side of the channel layer 3a; high-concentration n-type impurity regions 7, 8 formed in such a manner as to be separated from one another and oriented from the surface of the channel layer 3a to the interior of the channel layer 3, at least in the portions that are under the source electrode 5 and the drain electrode 6, respectively; a gate insulation film layer 9a formed in such a manner as to cover the surface of the channel layer 3a between the high-concentration n-type impurity regions 7, 8; and a gate electrode 10 formed on the surface of the gate insulation film layer 9a. During the ON state, the current density between the source electrode 5 and the drain electrode 6 is 10 mA/mm or higher.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a structure of a semiconductor device such as a field effect transistor made of a semiconductor containing nitride, and a manufacturing method thereof.

In a conventional field effect transistor made of a semiconductor containing a nitride, a GaN channel layer and an AlGaN barrier layer are sequentially formed on a substrate, and a source electrode, a drain electrode, and a gate electrode are formed thereon. High-concentration n-type impurity regions are formed in the channel layer and the barrier layer located below the source electrode and the drain electrode. A gate insulating film made of AlGa _x O _y is formed on the AlN barrier layer sandwiched between the high-concentration n-type impurity regions where the high-concentration n-type impurity regions are not formed so as to cover the regions. A gate electrode is formed on the film. For example, a heterojunction field effect transistor made of a nitride semiconductor described in Patent Document 1 has the above structure.

JP 2008-305816 A

When a heterojunction field effect transistor made of a nitride semiconductor is used for a switching element or the like, it is desirable to perform a normally-off operation. Even in the structure described in Patent Document 1, if the two-dimensional electron gas can be prevented from being generated at the heterointerface between the AlGaN barrier layer and the GaN channel layer on the lower side of the gate electrode, sufficient drain current can be obtained in the normally-off operation. Can be obtained. That is, after designing the energy at the bottom of the conduction band at the heterointerface between the channel layer below the gate electrode and the barrier layer to be higher than the Fermi energy, the gate insulating film made of AlGa _x O _y or the like If an ideal interface having no interface trap exists at the interface with the AlGaN barrier layer, a sufficient drain current can be obtained in the normally-off operation.

However, as described in Patent Document 1, when a transistor is manufactured by a simple process in which a gate insulating film is deposited on an AlGaN barrier layer, a high concentration is formed at the interface between the gate insulating film and the barrier layer. An interface trap level is formed. As a result, the controllability of the drain current by the gate voltage is lowered, and there is a problem that a sufficient drain current cannot be obtained in the normally-off operation.

Therefore, an object of the present invention is to provide a technique capable of obtaining a sufficiently large drain current in a normally-off operation in a semiconductor device.

A semiconductor device according to the present invention is formed with a channel layer made of Al _x1 In _y1 Ga _{1 -x1-y1} N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1) and spaced from each other on the surface side of the channel layer. The first and second n-type electrodes are formed so as to be spaced apart from each other toward the inside of the channel layer from at least the lower part of the first and second electrodes on the surface of the channel layer. From the band gap of Al _x1 In _y1 Ga _{1 -x1-y1} N that is formed so as to cover the surface of the channel layer between the impurity region and the first and second n-type impurity regions and that constitutes the channel layer A gate insulating film layer made of an insulator or a semiconductor having a large band gap and a gate electrode formed on the surface of the gate insulating film layer, and the current density between the first and second electrodes when turned on is 10 mA / mm or more.

According to the present invention, since the current density between the first and second electrodes when turned on is 10 mA / mm or more, the controllability of the drain current by the gate electrode is improved, and a sufficient drain current is obtained in the normally-off operation. It becomes possible.

The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

1 is a diagram illustrating an example of a structure of a semiconductor device according to a first embodiment. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device fabricated without performing heat treatment. 6 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured by performing heat treatment at a temperature of 700 ° C. after depositing a gate insulating film. 4 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured by performing heat treatment at a temperature of 700 ° C. after forming a gate electrode. 4 is a graph showing the heat treatment temperature dependence of drain current in a semiconductor device fabricated by performing heat treatment at a temperature of 0 ° C. to 800 ° C. FIG. A graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured without performing heat treatment after depositing AlO _x by atomic deposition using ozone as an oxygen supply source It is. Drain current-gate measured at a drain voltage of 5 V in a semiconductor device fabricated by depositing AlO _x by atomic deposition using ozone as an oxygen source and then performing heat treatment at a temperature of 500 ° C. It is a graph which shows a voltage characteristic. After draining AlO _x by an atomic deposition method using ozone as an oxygen supply source, a drain voltage is set to 5 V in a semiconductor device fabricated by performing heat treatment at a temperature of 500 ° C. after forming a gate electrode. It is a graph which shows the measured drain current-gate voltage characteristic. Shows the heat treatment temperature dependence of the drain current in a semiconductor device fabricated by depositing AlO _x by atomic deposition using ozone as an oxygen source and then performing heat treatment at a temperature of 0 ° C. to 800 ° C. It is a graph. 6 is a diagram illustrating an example of a structure of a semiconductor device according to a second embodiment. FIG. 6 is a diagram illustrating an example of a structure of a semiconductor device according to a third embodiment. FIG. FIG. 6 is a diagram illustrating an example of a structure of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram showing an example of a structure of a semiconductor device according to a sixth embodiment. It is a figure which shows the other example of the structure of the semiconductor device which concerns on Embodiment 6. FIG. FIG. 10 is a diagram illustrating an example of a structure of a semiconductor device according to a seventh embodiment. FIG. 20 is a diagram showing another example of the structure of the semiconductor device according to the seventh embodiment. FIG. 20 is a diagram showing an example of a structure of a semiconductor device according to an eighth embodiment. FIG. 20 is a diagram showing another example of the structure of the semiconductor device according to the eighth embodiment. FIG. 20 is a diagram showing another example of the structure of the semiconductor device according to the eighth embodiment. FIG. 20 illustrates an example of a structure of a semiconductor device according to a ninth embodiment. FIG. 38 shows an example of a structure of a semiconductor device according to a tenth embodiment. FIG. 38 shows another example of the structure of the semiconductor device according to the tenth embodiment. It is a figure which shows an example of the structure of the semiconductor device which concerns on Embodiment 11. FIG. FIG. 38 shows another example of the structure of the semiconductor device according to the eleventh embodiment. FIG. 38 shows another example of the structure of the semiconductor device according to the eleventh embodiment. It is a figure which shows an example of the structure of the semiconductor device which concerns on Embodiment 12. FIG. FIG. 38 shows another example of the structure of the semiconductor device according to the twelfth embodiment. FIG. 38 shows another example of the structure of the semiconductor device according to the twelfth embodiment. It is a figure which shows an example of the structure of the semiconductor device which concerns on a modification.

<Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an example of the structure of the semiconductor device according to the first embodiment. The semiconductor device is, for example, a heterojunction field effect transistor made of a nitride semiconductor.

As shown in FIG. 1, the semiconductor device includes a substrate 1, a buffer layer 2, a channel layer 3a made of Al _x1 In _y1 Ga _{1 -x1-y1} N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1), Al _x2 Barrier layer 4a made of In _y2 Ga _1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1), source electrode 5 as the first electrode, drain electrode 6 as the second electrode, first n-type impurity A high-concentration n-type impurity region 7 as a region, a high-concentration n-type impurity region 8 as a second n-type impurity region, a gate insulating film layer 9a, a gate electrode 10, and an element isolation region 11 are provided.

The lowermost layer is the substrate 1, and a channel layer 3 a made of non-doped GaN and a barrier layer 4 a made of non-doped AlN that forms a heterojunction with the channel layer 3 a are formed on the surface of the substrate 1 through the buffer layer 2. ing. GaN is Al _x1 Ga _1-x1 N with x1 = 0 and y1 = 0. AlN is Al _x2 In _y2 Ga _{1 -x2-y2} N with x2 = 1 and y2 = 0.

A source electrode 5 and a drain electrode 6 are formed on the surface side of the channel layer 3a so as to be separated from each other. More specifically, the source electrode 5 is formed on the left side of the surface of the channel layer 3a toward the paper surface of FIG. A drain electrode 6 is formed on the right side of the surface of the channel layer 3a as viewed in FIG. Further, a gate electrode 10 is formed at the central portion toward the paper surface of FIG.

Under the source electrode 5 and the drain electrode 6, a high-concentration n-type impurity region 7 and a high-concentration n-type impurity region 8 containing Si at a high concentration are formed to a position deeper than the barrier layer 4a. That is, the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 are separated from each other toward the inside of the channel layer 3a from at least a portion below the source electrode 5 and the drain electrode 6 on the surface of the channel layer 3a. Is formed. Barrier layer 4 a is formed on the surface of channel layer 3 a between high-concentration n-type impurity region 7 and high-concentration n-type impurity region 8.

The element isolation regions 11 are formed on the left and right ends of the surface of the substrate 1 through the buffer layer 2 with respect to the paper surface of FIG. The gate insulating film layer 9 a is made of AlO _a and is formed so as to cover the surface of the channel layer 3 a between the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8. In this structure, the gate insulating film layer 9 a is formed so as to cover the entire surface of the channel layer 3 a and the surface of the element isolation region 11. The gate electrode 10 is formed so as to cover the entire surface of the barrier layer 4 a sandwiched between the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8.

In the equilibrium state, the energy at the lower end of the conduction band at the heterointerface between the channel layer 3a on the lower side of the gate electrode 10 and the barrier layer 4a is higher than the Fermi energy. Here, the equilibrium state is a state in which no voltage is applied to each electrode. The electrodes are the source electrode 5, the drain electrode 6, and the gate electrode 10. In the structure shown in FIG. 1, for example, if the thickness of the barrier layer 4a made of non-doped AlN is 1 nm, the conduction at the heterointerface between the channel layer 3a below the gate electrode 10 and the barrier layer 4a in an equilibrium state. The energy at the lower end of the belt is higher than the Fermi energy.

In this structure, in the ideal state where the concentration of the interface trap level at the interface between the barrier layer 4a and the gate insulating film layer 9a in the channel region is low, such a structure allows the normally-off operation to be performed. Realized. As the concentration of the interface trap level is lower, the controllability of the drain current by the gate voltage is improved, and a larger drain current can be obtained. Here, the channel region is a region sandwiched between the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 below the gate electrode 10.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2 to 7 are views showing a method of manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 2, by using an epitaxial growth method such as MOCVD method or MBE method on the surface of the substrate 1, the buffer layer 2, the channel layer 3a, and the barrier layer 4a are grown in order from the bottom. Note that the step of growing the channel layer 3a shown in FIG. 2 is called a channel layer generation step, and the step of growing the barrier layer 4a is called a barrier layer generation step.

As shown in FIG. 3, using a resist pattern or the like as a mask, Si ions are implanted in a desired region under the conditions of an implantation dose of 1 × 10 ¹⁵ (cm ⁻² ) and an implantation energy of 50 (keV). Type in. Thereafter, heat treatment is performed at a temperature of 1150 ° C. using a rapid thermal annealing (RTA) method to activate the doped Si ions, thereby forming the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8. The process shown in FIG. 3 is referred to as a first and second n-type impurity region forming process.

As shown in FIG. 4, a source electrode 5 and a drain electrode 6 made of a metal multilayer film are formed on the surfaces of the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8, respectively, using a vapor deposition / lift-off method. In addition, the process shown in FIG. 4 is called the 1st, 2nd electrode production | generation process.

As shown in FIG. 5, the element isolation region 11 is formed in the channel layer 3a and the barrier layer 4a outside the region where the transistor is manufactured using an ion implantation method.

As shown in FIG. 6, a gate insulating film layer 9a made of AlO _a is deposited using an atomic layer deposition method using oxygen plasma as an oxygen supply source. Note that the process shown in FIG. 6 is referred to as a gate insulating film layer forming process.

As shown in FIG. 7, a gate electrode 10 made of a metal film is formed using a vapor deposition / lift-off method. Note that the process shown in FIG. 7 is referred to as a gate electrode generation process. In the above description, only the minimum necessary elements that operate as a transistor are described, but the element is finally used as a device through a formation process of a protective film, a field plate electrode, a wiring, an air bridge, a via hole, and the like. . Further, heat treatment is further performed in order to manufacture the semiconductor device shown in FIG. 1, and details thereof will be described later.

Next, the drain current-gate voltage characteristics and the heat treatment temperature dependence of the drain current in the semiconductor device manufactured when the heat treatment is not performed and when the heat treatment is performed will be described. FIG. 8 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured without performing heat treatment. The manufactured element is a single finger type, and the gate electrode width and the channel length are 100 μm and 1 μm, respectively. The channel length is the distance between the high concentration n-type impurity region 7 and the high concentration n-type impurity region 8.

As shown in FIG. 8, in the semiconductor device manufactured by this manufacturing process, although the normally-off type operation was performed, the obtained drain current was a very small value less than 50 μA / mm. This is thought to be because the controllability of the drain current by a sufficiently high gate voltage is not obtained because a high concentration interface trap level is formed at the interface between the barrier layer 4a and the gate insulating film layer 9a. It is done.

The manufacturing method of the semiconductor device according to the present embodiment is characterized in that a heat treatment such as an RTA method is performed after depositing the gate insulating film layer 9a shown in FIG. That is, heat treatment is performed after the gate insulating film layer 9a is deposited or after the gate electrode 10 is formed. This process is called a heat treatment process. Hereinafter, details of the heat treatment step will be described.

FIG. 9 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured by performing heat treatment at a temperature of 700 ° C. after depositing the gate insulating film layer 9a. . Note that the gate electrode width and the channel length are the same as those in FIG.

As shown in FIG. 9, a drain current exceeding 10 mA / mm was obtained by performing a heat treatment at 700 ° C. after the deposition of the gate insulating film layer 9a. In this case, normally-off operation is performed. The cause of the increase in the drain current is that the interface trap level formed at the interface between the barrier layer 4a and the gate insulating film layer 9a in the channel region is reduced by the heat treatment. If it is assumed that the interface trap level is formed by the dangling bond at the interface, it can be explained that the dangling bond is recombined by the heat treatment, thereby reducing the interface trap level.

FIG. 10 is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5 V in a semiconductor device manufactured by performing heat treatment at a temperature of 700 ° C. after forming the gate electrode 10. FIG. 11 is a graph showing the heat treatment temperature dependence of the drain current in a semiconductor device fabricated by performing heat treatment at a temperature of 0 ° C. to 800 ° C. 10 and 11, the gate electrode width and channel length are the same as those in FIG.

As shown in FIG. 10, by performing a heat treatment at 700 ° C. after forming the gate electrode 10, the drain current further increased, and a sufficiently high current value of 0.4 A / mm was obtained. In this case, normally-off operation is performed. Further, a sufficiently high drain current can be obtained in the case of heat treatment at a temperature higher than 650 ° C., and a sufficiently high drain current cannot be obtained at a temperature higher than 750 ° C. The cause of the increase in the drain current due to the heat treatment at 650 ° C. to 750 ° C. can be explained by the decrease in the interface trap level as in the case of the heat treatment after the gate insulating film layer 9a is deposited. It can be said that the amount of increase in the drain current is larger in the heat treatment after the formation of the gate electrode 10 because the amount of the reduced interface trap level is larger.

By forming the gate electrode 10, the energy band structure of the barrier layer 4a and the gate insulating film layer 9a on the lower side of the gate electrode 10 is changed, and the recombination of dangling bonds is promoted. It is thought that the amount of decrease increased. Note that the cause of the decrease in the drain current when heat-treated at a temperature higher than 750 ° C. is not only due to the interaction between these bulks but also the interface between the gate insulating film layer 9a and the barrier layer 4a. It is thought that the trap levels in the interface and bulk increased. In general, in a semiconductor device using Si or GaAs, when a structure in which an insulating film is sandwiched between a gate electrode and a semiconductor layer as shown in FIG. When implemented, the insulating film and the semiconductor layer react with each other, thereby causing adverse effects such as an increase in gate leakage current. Therefore, heat treatment at a high temperature exceeding 500 ° C. is rarely performed after depositing the insulating film.

However, in this structure, the heat treatment at 650 ° C. to 750 ° C. did not show any significant changes in other characteristics except that the drain current was improved. This is because wide-gap semiconductors such as nitride semiconductors have strong interatomic bonding forces, and the change in state due to heat treatment occurs only near the interface between the insulating film where the interface states are formed and the semiconductor. It is done. In other words, it can be said that the effect of such heat treatment is unique to the nitride semiconductor.

In the above description, the heat treatment is performed either after the gate insulating film layer 9a is deposited or after the gate electrode 10 is formed. However, both after the gate insulating film layer 9a is deposited and after the gate electrode 10 is formed. Heat treatment may be performed.

The increase in drain current due to the heat treatment was also obtained as shown below when AlO _x was deposited using an atomic deposition method using ozone as an oxygen supply source. FIG. 12 shows a drain current-gate voltage measured at a drain voltage of 5 V in a semiconductor device manufactured without performing a heat treatment after depositing AlO _x by an atomic deposition method using ozone as an oxygen supply source. It is a graph which shows a characteristic. Note that the gate electrode width and the channel length are the same as those in FIG. As shown in FIG. 12, compared with the characteristics shown in FIG. 8, although the current value was large, the obtained current value was a small value less than 3 mA / mm.

FIG. 13 shows a drain voltage measured at 5 V in a semiconductor device manufactured by performing AlO _x deposition by atomic deposition using ozone as an oxygen supply source and then performing heat treatment at a temperature of 500 ° C. It is a graph which shows a drain current-gate voltage characteristic. Note that the gate electrode width and the channel length are the same as those in FIG. As in the case where oxygen plasma was used as the oxygen supply source, the drain current increased by performing the heat treatment, and a value of about 60 mA / mm was obtained.

Further, FIG. 14 shows a semiconductor device manufactured by performing AlO _x deposition by an atomic deposition method using ozone as an oxygen supply source, and then performing heat treatment at a temperature of 500 ° C. after forming the gate electrode 10. Is a graph showing drain current-gate voltage characteristics measured at a drain voltage of 5V. FIG. 15 shows the drain current in a semiconductor device manufactured by depositing AlO _x by atomic deposition using ozone as an oxygen supply source and then performing heat treatment at a temperature of 0 ° C. to 800 ° C. It is a graph which shows heat processing temperature dependence. 14 and 15, the gate electrode width and channel length are the same as those in FIG.

As shown in FIGS. 14 and 15, as in the case where oxygen plasma is used as the oxygen supply source, the drain current is further increased by performing the heat treatment after the formation of the gate electrode 10, and a sufficient current of about 0.3 A / mm is obtained. A high value was obtained. Further, although the temperature range in which the drain current increases is different, even when ozone is used as the oxygen supply source, the drain current increases as a result of heat treatment at a temperature of 400 ° C. to 500 ° C. In two types of semiconductor devices manufactured by two different deposition methods, the drain current is increased by a heat treatment at a high temperature of 400 ° C. or higher. Therefore, the effect of this heat treatment is a universal effect independent of the deposition method. .

In the normally-on structure in which the energy at the lower end of the conduction band at the heterointerface between the channel layer 3a below the gate electrode 10 and the barrier layer 4a in the equilibrium state is lower than the Fermi energy, the drain current is There is a high concentration of the two-dimensional electron gas generated at the hetero interface to be carried. Therefore, the drain current amount hardly depends on the amount of the interface trap level between the barrier layer 4a and the gate insulating film layer 9. Therefore, the heat treatment performed after the gate insulating film layer 9 is deposited or after the gate electrode 10 is formed is a conduction band at the heterointerface between the channel layer 3a below the gate electrode 10 and the barrier layer 4a in an equilibrium state. It can be said that the energy at the lower end is extremely effective for increasing the drain current in the structure in which the normally-off operation is higher than the Fermi energy.

As described above, the manufacturing method of the semiconductor device according to the first embodiment includes the channel layer generation step, the first and second n-type impurity region formation steps, the first and second electrode generation steps, and the gate insulating film layer. After the forming step, the gate electrode generating step, and the gate insulating film layer forming step or the gate electrode generating step, a heat treatment step of performing a heat treatment on the gate insulating film layer is provided. In the semiconductor device according to the first embodiment obtained through the above steps, the current density between the source electrode 5 and the drain electrode 6 when turned on is 10 mA / mm or more.

As described above, since the interface trap level formed between the channel layer 3a and the gate insulating film layer 9 is reduced, the controllability of the drain current by the gate electrode 10 is improved, and a sufficient drain can be obtained by the normally-off operation. A current can be obtained.

In addition, since the semiconductor device is configured using a wide gap semiconductor, it is possible to reduce the size of the semiconductor device and reduce energy consumption.

In a state where no voltage is applied to the source electrode 5, the drain electrode 6, and the gate electrode 10, the heterogeneity of the channel layer 3a and the barrier layer 4a between the high concentration n-type impurity region 7 and the high concentration n-type impurity region 8 is achieved. Since the energy at the lower end of the conduction band at the interface is higher than the Fermi energy, the semiconductor device can be normally-off operated.

Since the channel layer 3a is made of GaN, the barrier layer 4a is made of AlN, and the gate insulating film layer 9 is made of AlO, the semiconductor device can be operated at a high voltage and the drain current can be increased.

In the first and second n-type impurity region forming steps, the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 are formed by ion implantation, so that the surface of the channel layer 3a can be easily formed with a uniform high thickness. The concentration n-type impurity region 7 and the high concentration n-type impurity region 8 can be formed.

<Embodiment 2>
Next, a semiconductor device according to the second embodiment will be described. FIG. 16 is a diagram illustrating an example of the structure of the semiconductor device according to the second embodiment. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

The effect of the heat treatment performed after deposition of the gate insulating film layer 9a or after formation of the gate electrode 10 shown in the first embodiment is not limited to the semiconductor device shown in FIG. A structure in which an interface between a film and a layer made of a nitride semiconductor is formed is considered to be obtained similarly.

As shown in FIG. 16, the semiconductor device according to the second embodiment is replaced with Al _x1 In _y1 Ga _{1 -x1-y1} N in place of the channel layer 3a made of GaN and the barrier layer 4a made of AlN shown in FIG. and a channel layer 3 and the Al _x2 in _y2 Ga barrier layer 4 made of _1-x2-y2 N consisting of. It is assumed that Al _x2 In _y2 Ga _1-x2-y2 N constituting the barrier layer 4 has a larger band gap than Al _x1 In _y1 Ga _1-x1-y1 N constituting the channel layer 3.

Further, in the semiconductor device according to the second embodiment, Al _x1 In _y1 Ga _{1 -x1-y1} N which is a material constituting the barrier layer 4 is used instead of the gate insulating film layer 9a made of AlO _a shown in FIG. A gate insulating film layer 9 made of an insulator or a semiconductor having a band gap larger than the band gap is provided.

Also in the structure of the semiconductor device according to the second embodiment, the energy at the lower end of the conduction band at the heterointerface between the channel layer 3 below the gate electrode 10 and the barrier layer 4 in the equilibrium state is higher than the Fermi energy. If normally, a normally-off operation is realized, and if the interface trap level between the barrier layer 4 and the gate insulating film layer 9 is sufficiently low, a sufficiently large drain current can be obtained.

Also in such a structure, since it is considered that an interface trap level is formed between the barrier layer 4 and the gate insulating film layer 9, the deposition of the gate insulating film layer 9 described in the first embodiment is performed. The effect of heat treatment performed after or after the formation of the gate electrode 10 can be obtained.

In the semiconductor device according to the second embodiment, when the buffer layer 2, the channel layer 3, and the barrier layer 4 shown in FIG. 2 of the first embodiment are grown, In _z Al _x Ga _1-xz N (0 <x ≦ The growth conditions such as flow rate, pressure, and temperature of trimethylindium, trimethylaluminum, trimethylgallium, ammonia, etc., which are source gases of 1, 0 <z ≦ 1), are adjusted, and buffer layer 2, channel layer 3, and barrier The layer 4 can be produced with a desired composition.

As described above, the semiconductor device according to the second embodiment is formed on the surface of channel layer 3a between high-concentration n-type impurity region 7 and high-concentration n-type impurity region 8, and constitutes channel layer 3a. _{_{_{Al x1 in y1 Ga 1-x1}}} -y1 N Al x2 in y2 Ga 1-x2-y2 further comprising a barrier layer 4a made of N, the gate insulating film layer 9 having a larger band gap than the band gap of the a barrier The surface of the channel layer 3a is covered via the layer 4a and is made of an insulator or a semiconductor having a band gap larger than the band gap of the barrier layer 4a. Therefore, the interface trap level formed between the channel layer 3a and the gate insulating film layer 9 is reduced, and a sufficiently large drain current can be obtained.

<Embodiment 3>
Next, a semiconductor device according to the third embodiment will be described. FIG. 17 is a diagram illustrating an example of the structure of the semiconductor device according to the third embodiment. In the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 17, the semiconductor device according to the third embodiment has a structure that does not include the barrier layer 4 made of Al _x2 In _y2 Ga _{1 -x2-y2} N shown in FIG.

Also in the structure of the semiconductor device according to the third embodiment, the normally-off operation is realized if electrons are not generated at the interface between the channel layer 3 and the gate insulating film layer 9 in an equilibrium state, and the channel layer 3 and the gate insulating film layer 9 are realized. If the interface trap level between and is sufficiently low, a sufficiently large drain current can be obtained. Even in such a structure, since it is considered that an interface trap level is formed between the channel layer 3 and the gate insulating film layer 9, after the deposition of the gate insulating film layer 9 shown in the first embodiment, Or the effect of the heat processing implemented after formation of the gate electrode 10 is acquired.

However, compared with the case where the barrier layer 4 made of Al _x2 In _y2 Ga _1-x2-y2 N is formed, there is a concern that the mobility of electrons in the channel formed at the heterointerface is lowered and the drain current is reduced. Is done. Therefore, it can be said that the structure in which the barrier layers 4 and 4a shown in FIGS. 1 to 7 and FIG. 16 are formed is more suitable because a large drain current is easily obtained. The semiconductor device according to the third embodiment can be manufactured unless the barrier layer 4 shown in FIG. 2 of the first embodiment is grown.

<Embodiment 4>
Next, a semiconductor device according to the fourth embodiment will be described. FIG. 18 is a diagram illustrating an example of the structure of the semiconductor device according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 18, the semiconductor device according to the fourth embodiment has a barrier layer below gate electrode 10 in place of high concentration n-type impurity region 7 and high concentration n-type impurity region 8 shown in FIG. From Al _x3 In _y3 Ga _1-x3-y3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1) having a band gap smaller than the band gap of Al _x2 In _y2 Ga _1-x2-y2 N constituting 4 The high concentration n-type impurity region 7a and the high concentration n-type impurity region 8a are provided.

With such a structure, the nitride semiconductor constituting the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 is a band of Al _x2 In _y2 Ga _{1 -x2-y2} N constituting the barrier layer 4. The resistance between the channel layer 3 and the source electrode 5 and the drain electrode 6 is reduced as compared with the case where the gap is equal to or larger than the gap, and a sufficiently large drain current can be obtained even in the normally-off operation.

It should be noted that in a normally operated structure in which the energy at the lower end of the conduction band at the heterointerface between the channel layer 3 and the barrier layer 4 below the gate electrode 10 is lower than the Fermi energy in an equilibrium state, this heterointerface Since a high-concentration two-dimensional electron gas is generated in the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 at the heterointerface between the channel layer 3 and the barrier layer 4 in the same manner as the lower side of the gate electrode 10 Even if the structure is left as it is, a high-concentration two-dimensional electron gas is generated at the heterointerface in this region. Accordingly, in the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8, in addition to the doped n-type impurity, the two-dimensional electron gas also acts as a carrier, and therefore, between the channel region and the source and drain electrodes. Is not so high that a sufficiently large drain current cannot be obtained.

However, in the structure of the semiconductor device according to the first to fourth embodiments in which the energy at the lower end of the conduction band at the heterointerface between the channel layer 3 and the barrier layer 4 is normally off in an equilibrium state, the state is higher than the Fermi energy. No two-dimensional electron gas is generated at this hetero interface. Therefore, even if the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 have a structure in which the heterointerface consisting of the channel layer 3 and the barrier layer 4 is left as it is, as described above, No two-dimensional electron gas is generated at the heterointerface in this region. Therefore, in the high concentration n-type impurity region 7 and the high concentration n-type impurity region 8, only the doped n-type impurity works as a carrier. Therefore, compared with the structure in which the two-dimensional electron gas is generated at the hetero interface, it is difficult to reduce the resistance between this region, that is, between the channel layer 3 and the source electrode 5 and the drain electrode 6, and a sufficiently large drain current is generated. It is difficult to obtain. Therefore, the high-concentration n-type impurity region 7a and the high-concentration n-type impurity region 8a have a band smaller than the band gap of Al _x2 In _y2 Ga _{1 -x2-y2} N constituting the lower barrier layer 4 of the gate electrode 10. The effect of reducing the resistance by the semiconductor device according to the fourth embodiment, which is composed of Al _x3 In _y3 Ga _1-x3-y3 N having a gap, is obtained at the heterointerface between the channel layer 3 and the barrier layer 4 in an equilibrium state. In the case of normally-off operation in which the energy at the lower end of the conduction band is higher than the Fermi energy, the energy is further increased.

Further, the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 are formed in a band smaller than the band gap of Al _x2 In _y2 Ga _{1 -x2-y2} N constituting the lower barrier layer 4 of the gate electrode 10. The effect of reducing the resistance by the semiconductor device according to the fourth embodiment, which is composed of Al _x3 In _y3 Ga _1-x3-y3 N having a gap, is that Al _x2 In _y2 Ga _1-x2-y2 constituting the barrier layer 4 The larger the band gap of N, the larger. This is because the larger the band gap, the lower the activation rate of the doped n-type impurity, and the more difficult it is to make the region resistant.

Of the high-concentration n-type impurity region 7 a and the high-concentration n-type impurity region 8 a, at least the region on the surface side thicker than the barrier layer 4 is Al _x2 In _y2 Ga _{1 -x2-y2} N constituting the barrier layer 4. The above effect can be obtained if it is made of Al _x3 In _y3 Ga _1-x3-y3 N having a band gap smaller than that of the high-concentration n-type in a region deeper than the thickness of the barrier layer 4. In the impurity region 7a and the high-concentration n-type impurity region 8a, a nitride semiconductor having a band gap larger than the band gap of Al _x2 In _y2 Ga _{1 -x2-y2} N constituting the barrier layer 4 may exist. Absent. Thereby, the resistance of the high concentration n-type impurity region 7a and the high concentration n-type impurity region 8a is reduced, and a large drain current is obtained.

<Embodiment 5>
Next, a semiconductor device according to the fifth embodiment will be described. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals and description thereof is omitted.

In the fifth embodiment, the regions on the surface side of the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 are composed of an interdiffusion layer of the barrier layer 4 and the channel layer 3. This will be described in detail.

In the semiconductor device shown in FIG. 18 of the fourth embodiment, the thickness of the barrier layer 4 in the manufacturing method shown in FIGS. 2 to 7 of the first embodiment is such that the ion implantation energy in the ion implantation step of FIG. Can be produced when it is thin enough to disappear. For example, a layer made of a nitride semiconductor having a thickness of 1 nm is extinguished by ion implantation as described in Non-Patent Documents Jpn. J. Appl. Phys. 50, 064101 (2011). Actually, the barrier layer 4 is not completely extinguished, but the ion-implanted region is formed by interdiffusion of constituent elements between the barrier layer 4 and the channel layer 3 by the implantation energy during ion implantation. That is, an interdiffusion layer is formed on the high concentration n-type impurity region 7 and the high concentration n-type impurity region 8 on the barrier layer 3 side. The interdiffusion layer is also called a mixing layer. As a result, the band gap of the nitride semiconductor in this region, that is, the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 on the barrier layer 3 side constitutes the nitridation constituting the barrier layer 4 below the gate electrode. The band gap is smaller than that of a physical semiconductor, and a semiconductor device similar to the structure shown in FIG. 18 is manufactured. Therefore, the thickness of the barrier layer 4 that can produce a semiconductor device similar to the structure shown in FIG. 18 by ion implantation is determined by the energy at the time of ion implantation and the binding energy of the elements constituting the barrier layer 4 and the channel layer 3. 3 can be said to be thinner than 2 nm.

The thickness of the barrier layer 4 is 2 nm or less, and the regions on the surface side of the high-concentration n-type impurity region 7 and the high-concentration n-type impurity region 8 are composed of interdiffusion layers of the barrier layer 4 and the channel layer 3. Therefore, the resistance of the high concentration n-type impurity region 7 and the high concentration n-type impurity region 8 is reduced, and a large drain current is obtained.

In this interdiffusion layer, the band gap is distributed so that the band gap is large on the surface side, and the band gap becomes smaller as the depth increases in the depth direction. For example, when the barrier layer 4 is made of AlN and the channel layer 3 is made of GaN, the surface side is made of AlGaN having a relatively high Al composition, and the Al composition decreases as the depth increases. Thus, the Al composition is distributed.

<Embodiment 6>
Next, a semiconductor device according to the sixth embodiment will be described. FIG. 19 is a diagram illustrating an example of the structure of the semiconductor device according to the sixth embodiment. FIG. 20 is a diagram illustrating another example of the structure of the semiconductor device according to the sixth embodiment. Note that in the sixth embodiment, the same components as those described in the first to fifth embodiments are denoted by the same reference numerals and description thereof is omitted.

In the semiconductor device shown in FIG. 16, a part of the high-concentration n-type impurity region 7 on the lower side of the source electrode 5 has a structure overlapping with the gate electrode 10, but as shown in FIG. In the semiconductor device according to the sixth embodiment, the high-concentration n-type impurity region 7 below the source electrode 5 has a structure that does not overlap the gate electrode 10.

Even in such a structure, if the energy at the lower end of the conduction band at the heterointerface between the channel layer 3 below the gate electrode 10 and the barrier layer 4 in an equilibrium state is higher than the Fermi energy, it is normally off. If the operation is realized and the interface trap level between the barrier layer 4 and the gate insulating film layer 9 is sufficiently low, a drain current can be obtained. Therefore, even in such a structure, the effect of heat treatment performed after the deposition of the gate insulating film layer 9 or the formation of the gate electrode 10 shown in the first embodiment can be obtained.

Also in such a structure, the high-concentration n-type impurity region 7 below the source electrode 5 is formed of Al _x2 constituting the barrier layer 4 below the gate electrode 10 as shown in the fourth embodiment. If it is made of Al _x3 In _y3 Ga _1-x3-y3 N having a band gap smaller than that of In _y2 Ga _1-x2-y2 N, Al _x2 In _y2 Ga _1-x2 constituting the barrier layer 4 The resistance of the high-concentration n-type impurity region 7 is reduced and a large drain current can be obtained as compared with the case where the band gap is equal to or larger than the band gap of _-y2N .

However, in this case, the region between the high-concentration n-type impurity region 7 on the lower side of the source electrode 5 and the gate electrode 10 becomes a high resistance region because no carrier exists, and the longer this distance, the higher the resistance. As a result, the drain current decreases. Therefore, a larger drain current can be obtained in the structure shown in FIG. 16 than in the structure shown in FIG.

In the structure shown in FIG. 16, the gate electrode 10 has a structure that covers a part of the high-concentration n-type impurity region 7, and the high-concentration n-type impurity region 7 and the gate electrode 10 overlap in this way. In this case, parasitic capacitance is generated in this region, which hinders high-frequency operation. Therefore, it is preferable to reduce the overlapping region as much as possible. The optimum structure is the structure shown in FIG. 20 in which the end of the gate electrode 10 coincides with the end of the high-concentration n-type impurity region 7. The semiconductor device shown in FIGS. 19 and 20 can be manufactured by changing the mask pattern at the time of ion implantation shown in FIG. 3 of the first embodiment.

<Embodiment 7>
Next, a semiconductor device according to the seventh embodiment will be described. FIG. 21 is a diagram illustrating an example of the structure of the semiconductor device according to the seventh embodiment. FIG. 22 shows another example of the structure of the semiconductor device according to the seventh embodiment. Note that in the seventh embodiment, the same components as those described in the first to sixth embodiments are denoted by the same reference numerals, and description thereof is omitted.

In the semiconductor device shown in FIG. 16, a part of the high-concentration n-type impurity region 8 on the lower side of the drain electrode 6 has a structure overlapping the gate electrode 10, but as shown in FIG. In the semiconductor device according to Embodiment 7, the high-concentration n-type impurity region 8 below the drain electrode 6 has a structure that does not overlap the gate electrode 10.

However, in this case, the region between the high concentration n-type impurity region 8 on the lower side of the drain electrode 6 and the gate electrode 10 becomes a high resistance region because no carrier exists, and the longer this distance is, the higher the resistance is. Increased, drain current decreases. Therefore, a larger drain current can be obtained in the structure shown in FIG. 16 than in the structure shown in FIG.

In the structure shown in FIG. 16, the gate electrode 10 has a structure that covers a part of the high-concentration n-type impurity region 8, and the high-concentration n-type impurity region 8 and the gate electrode 10 overlap in this way. In this case, parasitic capacitance is generated in this region, which hinders high-frequency operation. Therefore, it is preferable to reduce the overlapping region as much as possible. The optimum structure is the structure shown in FIG. 22 in which the end of the gate electrode 10 coincides with the end of the high-concentration n-type impurity region 8.

The semiconductor device having the structure shown in FIGS. 21 and 22 can be manufactured by changing the mask pattern at the time of ion implantation shown in FIG. 3 of the first embodiment.

<Eighth embodiment>
Next, a semiconductor device according to the eighth embodiment will be described. FIG. 23 shows an example of the structure of the semiconductor device according to the eighth embodiment. FIG. 24 shows another example of the structure of the semiconductor device according to the eighth embodiment. FIG. 25 is a diagram illustrating another example of the structure of the semiconductor device according to the eighth embodiment. Note that in the eighth embodiment, the same components as those described in the first to seventh embodiments are denoted by the same reference numerals and description thereof is omitted.

As shown in FIGS. 23 to 25, the semiconductor device according to the eighth embodiment is different from the structure shown in FIGS. 16, 21, and 22 in the high-concentration n-type impurity region 8 below the drain electrode 6. And a structure in which a low-concentration n-type impurity region 12 having an n-type impurity concentration lower than that of the high-concentration n-type impurity region 8 is formed between the channel layer 3 and the barrier layer 4 below the gate electrode 10. It has become. With such a structure, when a high voltage is applied to the drain electrode 6, the electric field generated between the gate electrode 10 and the high-concentration n-type impurity region 8 below the drain electrode 6 is relaxed. A higher voltage can be applied to the drain electrode 6.

Also in such a structure, the high-concentration n-type impurity region 7 below the source electrode 5 is formed of Al _x2 constituting the barrier layer 4 below the gate electrode 10 as shown in the fourth embodiment. If it is made of Al _x3 In _y3 Ga _1-x3-y3 N having a band gap smaller than that of In _y2 Ga _1-x2-y2 N, Al _x2 In _y2 Ga _1-x2 constituting the barrier layer 4 The resistance of the high-concentration n-type impurity region 7 is reduced and a large drain current can be obtained compared to the case where the band gap is equal to or larger than the band gap of _-y2N .

In the structure shown in FIG. 24, there is no region where the low-concentration n-type impurity region 12 and the gate electrode 10 overlap. In this case, since the parasitic resistance of the region where the gate electrode 10 and the low-concentration n-type impurity region do not overlap with each other increases, the gate electrode 10 and the low-concentration n-type impurity region 12 must be connected to obtain a sufficiently large drain current. The overlapping structure shown in FIG. 23 is preferable because parasitic resistance can be reduced. Further, in the structure shown in FIG. 23, the gate electrode 10 covers a part of the low-concentration n-type impurity region 12, but when the low-concentration n-type impurity region 12 and the gate electrode 10 overlap in this way, Since parasitic capacitance is generated in this region and hinders high-frequency operation, it is preferable to reduce the overlapping region as much as possible. Therefore, the optimum structure is the structure shown in FIG. 25 where the end of the gate electrode 10 coincides with the end of the low-concentration n-type impurity region 12.

The semiconductor device having the structure shown in FIGS. 23 to 25 can be manufactured by performing the ion implantation shown in FIG. 3 of the first embodiment twice with changing the ion implantation conditions and the mask pattern.

<Embodiment 9>
Next, a semiconductor device according to the ninth embodiment will be described. FIG. 26 is a diagram illustrating an example of the structure of the semiconductor device according to the ninth embodiment. Note that in the ninth embodiment, the same components as those described in the first to eighth embodiments are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 26, the semiconductor device according to the ninth embodiment includes a substrate 1a made of n-type Al _x3 In _y3 Ga _1-x3-y3 N, instead of the substrate 1. On the surface of the substrate 1a, a drift layer 13 made of n-type low concentration than the substrate _{_{_{1a Al x4 In y4 Ga 1-}}} x4-y4 N (0 ≦ x4 ≦ 1,0 ≦ y4 ≦ 1) is formed Yes. On the surface of the drift layer 13, a constriction layer 14 made of p-type Al _x5 In _y5 Ga _1-x5-y5 N (0 ≦ x5 ≦ 1, 0 ≦ y5 ≦ 1) having a lower concentration than the substrate 1 a is formed. ing.

The drain electrode 6 is formed on the lower side of the substrate 1a. That is, the drain electrode 6 is formed on the back side of the channel layer 3. Further, a p-type impurity region 15 containing a p-type impurity with respect to the nitride semiconductor is formed below the source electrode 5 to a depth reaching the constriction layer 14. In this structure, the low-concentration n-type impurity region 12 is formed to a depth from the barrier layer 4 to the drift layer 13. The gate insulating film layer 9 and the gate electrode 10 are formed so as to cover a channel region sandwiched between the high-concentration n-type impurity region 7 and the low-concentration n-type impurity region 12.

In this structure, the drain current flows from the source electrode 5 to the high-concentration n-type impurity region 7, the channel region sandwiched between the high-concentration n-type impurity region 7 and the low-concentration n-type impurity region 12, the low-concentration n-type impurity region 12, It flows to the drain electrode 6 through the drift layer 13 and the substrate 1a. Therefore, this structure can be said to be a vertical transistor. With such a vertical transistor structure, the drain current per area can be increased by devising the arrangement of each component.

Also in such a vertical transistor, the channel region sandwiched between the high-concentration n-type impurity region 7 and the low-concentration n-type impurity region 12 is equivalent to the structure shown in the first to eighth embodiments, and these are the same. The effect of can be obtained.

Also in the structure of the semiconductor device according to the ninth embodiment shown in FIG. 26, the positional relationship between the high-concentration n-type impurity region 7 and the gate electrode 10 is the same as in FIG. 16 of the second embodiment, FIG. 19 of the sixth embodiment, and FIG. The positional relationship between the low-concentration n-type impurity region 12 and the gate electrode 10 is the same as the positional relationship shown in FIGS. 23 to 25 of the eighth embodiment. Any positional relationship is acceptable.

<Embodiment 10>
Next, a semiconductor device according to the tenth embodiment will be described. FIG. 27 is a diagram illustrating an example of the structure of the semiconductor device according to the tenth embodiment. FIG. 28 shows another example of the structure of the semiconductor device according to the tenth embodiment. In the tenth embodiment, the same components as those described in the first to ninth embodiments are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 27, the semiconductor device according to the tenth embodiment has a channel made of Al _x1 Ga _{1 -x1} N instead of the channel layer 3 made of Al _x1 In _y1 Ga _{1 -x1-y1} N in FIG. The layer 3b is provided. Al _x1 Ga _{1 -x1} N is obtained by setting y1 = 0 in Al _x1 In _y1 Ga _{1 -x1-y1} N. By adopting the channel layer 3b made of Al _x1 Ga _1-x1 N in this way, the alloy scattering is suppressed as compared with Al _x1 In _y1 Ga _1-x1-y1 N made of 4 elements. Thus, the mobility of electrons in the channel formed in the channel is improved, and the drain current can be increased. Furthermore, if a material having a relatively large Al composition is used, the band gap becomes large, so that even when a high voltage is applied, it is difficult to break, and a high voltage operation is possible.

Furthermore, the semiconductor device shown in FIG. 28 includes a channel layer 3a made of GaN instead of the channel layer 3b made of Al _x1 Ga _1-x1 N shown in FIG. GaN is Al _x1 Ga _1-x1 N with x1 = 0 and y1 = 0. By using GaN as the channel layer 3a in this way, since the alloy scattering is further suppressed as compared with Al _x1 Ga _1-x1 N composed of three elements, the mobility of electrons in the channel formed at the heterointerface is reduced. Thus, the drain current can be further increased. Furthermore, crystal growth is facilitated, and impurities that are unintentionally mixed into the channel layer 3a can be reduced, so that current collapse caused by electron traps caused by these impurities can be suppressed.

In the present embodiment, the materials constituting the channel layers 3a and 3b are described so as to compare FIG. 23 with FIG. 27 and FIG. 28, but the same effects as the contents described in the present embodiment are obtained. This extends to all structures described in other embodiments.

In the semiconductor device having such a structure, a source material of In _z Al _x Ga _{1 -xz} N (0 <x ≦ 1, 0 <z ≦ 1) is obtained when the channel layer 3 shown in FIG. The channel layer 3 can be made to have a desired composition by adjusting the growth conditions such as the flow rate, pressure, and temperature of gases such as trimethylindium, trimethylaluminum, trimethylgallium, and ammonia.

<Embodiment 11>
Next, a semiconductor device according to the eleventh embodiment will be described. FIG. 29 shows an example of the structure of the semiconductor device according to the eleventh embodiment. FIG. 30 shows another example of the structure of the semiconductor device according to the eleventh embodiment. FIG. 31 is a diagram showing another example of the structure of the semiconductor device according to the eleventh embodiment. In the eleventh embodiment, the same components as those described in the first to tenth embodiments are denoted by the same reference numerals, and the description thereof is omitted.

As shown in FIG. 29, the semiconductor device according to the eleventh embodiment is made of Al _x2 Ga _1-x2 N instead of the barrier layer 4 made of Al _x2 In _y2 Ga _1-x2-y2 N shown in FIG. The barrier layer 4b is provided. Al _x2 Ga _{1 -x2} N is obtained by setting y2 = 0 in Al _x2 In _y2 Ga _{1 -x2-y2} N. Thus, by making the barrier layer 4b and the Al _{_x2} Ga _1-x2 N, the electron alloy scattering receive running the hetero-interface as a carrier between the channel layer 3 and the barrier layer 4b is reduced, the mobility As a result, the drain current can be increased.

The semiconductor device shown in FIG. 30 includes a barrier layer 4c made of In _y2 Al _y2 N in place of the barrier layer 4 made of Al _x2 In _y2 Ga _{1 -x2-y2} N shown in FIG. In _y2 Al _y2 N is obtained by _setting x2 + y2 = 1 in Al _x2 In _y2 Ga _{1 -x2-y2} N. As described above, even when the barrier layer 4c is made of In _y2 Al _y2 N, the alloy scattering received by electrons traveling as carriers at the heterointerface between the channel layer 3 and the barrier layer 4c is reduced, so that the mobility is increased. The drain current can be increased.

Further, the semiconductor device shown in FIG. 31 includes a barrier layer 4a made of AlN instead of the barrier layer 4 made of Al _x2 In _y2 Ga _{1 -x2-y2} N shown in FIG. AlN is Al _x2 In _y2 Ga _{1 -x2-y2} N with x2 = 1 and y2 = 0. Thus, by using AlN as the barrier layer 4a, the alloy scattering received by electrons traveling as carriers at the heterointerface between the channel layer 3 and the barrier layer 4a is further reduced, so that the mobility is further improved. The drain current can be further increased.

In the present embodiment, the materials constituting the barrier layers 4a, 4b, and 4c are described so as to compare FIG. 23 with FIGS. 29 to 31, but the same contents as described in the present embodiment are described. The effect extends to all the structures described in the other embodiments.

In the semiconductor device having such a structure, a source material of In _z Al _x Ga _1-xz N (0 <x ≦ 1, 0 <z ≦ 1) is obtained when the barrier layer 4 shown in FIG. The barrier layer 4 can be made to have a desired composition by adjusting the growth conditions such as the flow rate, pressure, and temperature of gases such as trimethylindium, trimethylaluminum, trimethylgallium, and ammonia.

<Embodiment 12>
Next, a semiconductor device according to Embodiment 12 will be described. FIG. 32 shows an example of the structure of the semiconductor device according to the twelfth embodiment. FIG. 33 shows another example of the structure of the semiconductor device according to the twelfth embodiment. FIG. 34 shows another example of the structure of the semiconductor device according to the twelfth embodiment. Note that in the twelfth embodiment, the same components as those described in the first to eleventh embodiments are denoted by the same reference numerals and the description thereof is omitted.

As shown in FIG. 32, the semiconductor device according to the twelfth embodiment is a gate made of an insulator or a semiconductor having a band gap larger than the band gap of Al _x1 In _y1 Ga _1-x1-y1 N shown in FIG. instead of the insulating film layer 9, and a gate insulating film layer 9b made of AlGa _c O _a N _b. Since AlGa _c O _a N _b is the same as the constituent elements of the semiconductor constituting the barrier layer 4 except for oxygen, the barrier layer 4 and the gate insulating film layer 9b are compared with materials such as SiO ₂ having different constituent elements. It is easy to reduce the interface trap level generated at the interface with and to obtain a large drain current.

Furthermore, the semiconductor device shown in FIG. 33, instead of the gate insulating film layer 9b made of AlGa _c O _a N _b shown in FIG. 32, a gate insulating layer 9c formed of AlO _a N _b. Since AlO _a N _b has _a larger band gap than AlGa _c O _a N _b , such a structure makes it possible to apply a larger positive voltage to the gate electrode and obtain a larger drain current. It becomes like this.

Furthermore, the semiconductor device shown in FIG. 34, instead of the gate insulating layer 9c formed of AlO _a N _b shown in FIG. 33, a gate insulating film layer 9a made of AlO _a. Since AlO _a has _a larger band gap than AlO _a N _b , such a structure makes it possible to apply a larger positive voltage to the gate electrode and obtain a larger drain current. .

In the present embodiment, the materials constituting the gate insulating

film layers

9a, 9b, and 9c are described so as to compare FIG. 23 with FIGS. 32 to 34. However, the contents described in the present embodiment The same effect extends to all the structures described in the other embodiments.

In the semiconductor device having such a structure, trimethylaluminum, trimethylgallium, oxygen, ozone, nitrogen, or the like, which becomes a source gas of the gate insulating film when the gate insulating film layer 9 shown in FIG. The gate insulating film layer 9 can be made to have a desired composition by adjusting growth conditions such as flow rate, pressure, and temperature.

<Other variations>
The structure of the semiconductor device according to the first to twelfth embodiments may be the following structure, and is not necessarily the same as the structure of the semiconductor device according to the first to twelfth embodiments.

When SiC or Si different from the channel layer is used as the substrate, the buffer layer 2 is required. However, when GaN, AlGaN, or InAlGaN of the same material as the channel layer is used as the substrate, the buffer layer 2 is not necessarily provided. Not necessary. Further, it is not always necessary to be non-doped. However, in the case of a vertical structure as shown in Embodiment 9, the substrate is preferably n-type.

Further, if three layers of a channel layer, a barrier layer, and a gate insulating film layer are formed on the substrate, a channel for operating the transistor is formed at the interface between the channel layer and the barrier layer, and the transistor operates. . Although only the minimum semiconductor layer that operates as the transistor is described above, a plurality of other layers may be formed in addition to the above three layers as long as the transistor operates. For example, a nitride semiconductor layer having a composition different from that of the channel layer and the barrier layer may be formed below the channel layer. Further, these nitride semiconductor layers including the channel layer and the barrier layer do not necessarily need to be non-doped and contain impurities such as Si, Mg, Fe, C, or Ge as long as the amount does not hinder transistor operation. It does not matter.

Further, n-type impurities doped in the high-concentration n-type impurity region, the low-concentration n-type impurity region, the n-type drift layer, and the n-type substrate include n in a nitride semiconductor such as Si, Ge, oxygen, or a nitrogen vacancy. Any impurity that behaves as a type dopant may be used.

The p-type impurity doped in the p-type impurity region and the p-type constriction layer may be any impurity that acts as a p-type dopant in a nitride semiconductor such as Mg or Fe.

Further, in the above, the gate insulating film layer has a structure deposited on the entire surface of the semiconductor device. However, if the gate insulating film layer is formed at least between the barrier layer and the gate electrode, the above effect can be obtained. It is not necessary to have a structure deposited on the entire surface. For example, as shown in FIG. 35, the gate insulating film layer 9 may be structured not to be deposited between the gate electrode 10 and the source electrode 5 and between the gate electrode 10 and the drain electrode 6. Further, the gate insulating film layer 9 is not necessarily composed of one _{_{_{layer, AlGa c O a N b,}}} AlO a N b, AlO a, be composed of a plurality of layers such as SiO _2, Si ₃ N ₄ I do not care. FIG. 35 is a diagram illustrating an example of a structure of a semiconductor device according to a modification.

In Embodiments 1 to 12, only the minimum necessary elements that operate as a transistor are described, but finally, a protective film, a field plate electrode, a wiring, an air bridge, a via hole, and the like are formed. Used as a device.

Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

3, 3a channel layer, 4, 4a, 4b, 4c barrier layer, 5 source electrode, 6 drain electrode, 7, 7a, 8, 8a high concentration n-type impurity region, 9, 9a, 9b, 9c gate insulating film layer, 10 Gate electrode.

Claims

A channel layer made of Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1),
First and second electrodes formed on the surface side of the channel layer so as to be spaced apart from each other;
First and second n-type impurity regions formed at a distance from the lower part of the surface of the channel layer toward the inside of the channel layer from the lower part of the first and second electrodes;
A band gap that is formed so as to cover the surface of the channel layer between the first and second n-type impurity regions and is larger than the band gap of Al x1 In y1 Ga 1 -x1-y1 N constituting the channel layer A gate insulating film layer made of an insulator or semiconductor having
A gate electrode formed on the surface of the gate insulating layer;
With
A semiconductor device, wherein a current density between the first and second electrodes when turned on is 10 mA / mm or more.
A channel layer made of Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1),
First and second electrodes formed spaced apart from each other on the front surface side and the back surface side of the channel layer;
A first n-type impurity region formed from at least a portion of the surface of the channel layer toward the inside of the channel layer from a lower portion of the first electrode;
The surface of the channel layer is formed so as to cover a portion adjacent to the first n-type impurity region, and is larger than the band gap of Al x1 In y1 Ga 1 -x1-y1 N constituting the channel layer. A gate insulating film layer made of an insulator or semiconductor having a band gap; and
A gate electrode formed on the surface of the gate insulating layer;
With
A semiconductor device, wherein a current density between the first and second electrodes when turned on is 10 mA / mm or more.
Al formed on the surface of the channel layer between the first and second n-type impurity regions and having a band gap larger than the band gap of Al x1 In y1 Ga 1 -x1-y1 N constituting the channel layer x2 In y2 Ga 1-x2- y2 N (0 ≦ x2 ≦ 1,0 ≦ y2 ≦ 1) further comprising a barrier layer consisting of,
The semiconductor device according to claim 1, wherein the gate insulating film layer is made of an insulator or a semiconductor that covers a surface of the channel layer through the barrier layer and has a band gap larger than a band gap of the barrier layer. .
4. The semiconductor according to claim 3, wherein at least a region on a surface side thicker than the barrier layer of the first and second n-type impurity regions is made of a nitride semiconductor having a band gap smaller than a band gap of the barrier layer. apparatus.
The semiconductor device according to claim 3 or 4, wherein the thickness of the barrier layer is 2 nm or less.
4. The semiconductor device according to claim 3, wherein a region on the surface side of the first and second n-type impurity regions is composed of an interdiffusion layer of the barrier layer and the channel layer.
In a state where no voltage is applied to the first and second electrodes and the gate electrode, the energy at the lower end of the conduction band at the heterointerface between the channel layer and the barrier layer between the first and second n-type impurity regions is The semiconductor device according to claim 3, wherein the semiconductor device is in a state higher than Fermi energy.
The channel layer is made of GaN;
The barrier layer is made of AlN,
The semiconductor device according to claim 3, wherein the gate insulating film layer is made of AlO.
A channel layer generating step for generating a channel layer made of Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1) on the substrate;
Forming first and second n-type impurity regions spaced apart from each other from the surface of the channel layer toward the inside of the channel layer; and
First and second electrode generation steps for forming first and second electrodes on the surfaces of the first and second n-type impurity regions, respectively;
A band gap that is formed so as to cover the surface of the channel layer between the first and second n-type impurity regions and is larger than the band gap of Al x1 In y1 Ga 1 -x1-y1 N constituting the channel layer A gate insulating film layer forming step of forming a gate insulating film layer made of an insulator or a semiconductor having
A gate electrode generation step of generating a gate electrode on the surface of the gate insulating film layer;
A heat treatment step of performing a heat treatment on the gate insulating film layer after the gate insulating film layer forming step or the gate electrode generating step;
A method for manufacturing a semiconductor device, comprising:
The method for manufacturing the semiconductor device includes:
Al formed on the surface of the channel layer between the first and second n-type impurity regions and having a band gap larger than the band gap of Al x1 In y1 Ga 1 -x1-y1 N constituting the channel layer further comprising a barrier layer forming step of generating a barrier layer made of x2 In y2 Ga 1-x2- y2 N,
The semiconductor device according to claim 9, wherein the gate insulating film layer is made of an insulator or a semiconductor that covers a surface of the channel layer through the barrier layer and has a band gap larger than a band gap of the barrier layer. Manufacturing method.
The channel layer is made of GaN;
The barrier layer is made of AlN,
The method of manufacturing a semiconductor device according to claim 10, wherein the gate insulating film layer is made of AlO.
12. The manufacturing of a semiconductor device according to claim 9, wherein in the first and second n-type impurity region forming steps, the first and second n-type impurity regions are formed by an ion implantation method. Method.