JP2013149732A - Hetero junction field effect transistor and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hetero junction field effect transistor which improves entrapment of a two-dimensional electron gas and improves mobility to enable operation at high voltage and high frequency; and provide a manufacturing method of the hetero junction field effect transistor.SOLUTION: A hetero junction field effect transistor composed of a nitride semiconductor comprises: a first nitride semiconductor layer 2 which is a buffer layer formed on a substrate 1; a second nitride semiconductor layer 3 which is a barrier layer formed on the first nitride semiconductor layer; and a third nitride semiconductor layer 4 which is a channel layer formed on the second nitride semiconductor layer. The second nitride semiconductor layer 3 is AlN, and the third nitride semiconductor layer 4 is composed of AlInGaN(0≤a<1, 0≤b≤1, 0≤a+b≤1).

Description

  The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride and a method for manufacturing the same.

  A HEMT (High Electron Mobility Transistor) using a nitride semiconductor has features of a high breakdown electric field and high electron mobility, and is expected as a device that operates at a high frequency and a high output. In a conventional heterojunction field effect transistor made of a semiconductor containing nitride, if the gate length needs to be reduced as the frequency increases, the modulation effect of the two-dimensional electron gas (2DEG) by the gate is reduced. The so-called short channel effect occurs (see, for example, Non-Patent Document 1).

In order to suppress the short channel effect, an epitaxial structure that enhances confinement of the two-dimensional electron gas is effective, and a heterojunction including a nitride semiconductor composed of an Al _x1 Ga _{1 -x1} N barrier layer / GaN channel layer In a field effect transistor, a barrier layer made of Al _X2 Ga _{1 -X2} N (1 ≧ X1>X2> 0) having a band gap energy smaller than that of the Al _X1 Ga _{1 -X1} N barrier layer is formed as a GaN channel. A structure that improves confinement of a two-dimensional electron gas by providing it under the layer has been proposed (see, for example, Patent Document 1).

Japanese Patent No. 3369464

L. Kley et al., “Short-channel effects in AlGAN / GaN HEMTs”, Materials Science and Engineering B82, 2001, p.p.238-240

In Patent Document 1, the structure of Al _X1 Ga _{1 -X1} N / GaN / Al _X2 Ga _{1 -X2} N (1 ≧ X1>X2> 0) improves the confinement of the two-dimensional electron gas and the short channel effect. Is suppressed. However, since the AlGaN layer formed as a carrier confinement barrier layer is ternary, the carrier is subjected to alloy scattering, so that the mobility is lowered and there is a problem that the current value is reduced and the high-frequency characteristics are lowered.

  The present invention has been made to solve such problems, and improves the confinement of the two-dimensional electron gas and improves the mobility, and the heterojunction field effect capable of operating at high voltage and high frequency. An object of the present invention is to provide a type transistor and a method for manufacturing the same.

In order to solve the above problems, a heterojunction field effect transistor according to the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and is a first nitride which is a buffer layer formed on a substrate. A semiconductor layer, a second nitride semiconductor layer that is a barrier layer formed on the first nitride semiconductor layer, and a third nitride that is a channel layer formed on the second nitride semiconductor layer And the second nitride semiconductor layer is AlN, and the third nitride semiconductor layer is Al _a In _b Ga _{1- (a + b)} N (0 ≦ a <1, 0 ≦ b ≦). 1, 0 ≦ a + b ≦ 1).

A method of manufacturing a heterojunction field effect transistor according to the present invention is a method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor, and (a) a first nitride semiconductor that is a buffer layer on a substrate. Forming a layer; (b) forming a second nitride semiconductor layer as a barrier layer on the first nitride semiconductor layer; and (c) a channel layer on the second nitride semiconductor layer. Forming a third nitride semiconductor layer, and (d) forming a fourth nitride semiconductor layer as a barrier layer on the third nitride semiconductor layer. sEMICONDUCTOR layer is _{1- Al e in f Ga (e} + f) N (0 ≦ e <1, 0 ≦ f ≦ 1,0 ≦ e + f ≦ 1), the second nitride semiconductor layer located in AlN The third nitride semiconductor layer is made of Al _a In _b Ga _{1- (a + b)} N (0 ≦ a <1, 0 ≦ b ≦ 1, 0 ≦ a + B ≦ 1), and the fourth nitride semiconductor layer is Al _c In _d Ga _{1− (c + d)} N (0 ≦ c <1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1), The first nitride semiconductor layer and the fourth nitride semiconductor layer have a band gap energy larger than that of the third nitride semiconductor layer.

According to the present invention, a first nitride semiconductor layer that is a buffer layer formed on a substrate, a second nitride semiconductor layer that is a barrier layer formed on the first nitride semiconductor layer, and And a third nitride semiconductor layer that is a channel layer formed on the nitride semiconductor layer, the second nitride semiconductor layer is AlN, and the third nitride semiconductor layer is Al _a In _b Since Ga _{1− (a + b)} N (0 ≦ a <1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), the confinement of the two-dimensional electron gas is improved and the mobility is improved. It is possible to improve and operate at high voltage and high frequency.

According to the present invention, there is also provided a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, wherein (a) a step of forming a first nitride semiconductor layer as a buffer layer on a substrate; ) Forming a second nitride semiconductor layer that is a barrier layer on the first nitride semiconductor layer; and (c) a third nitride semiconductor layer that is a channel layer on the second nitride semiconductor layer. And (d) forming a fourth nitride semiconductor layer as a barrier layer on the third nitride semiconductor layer, wherein the first nitride semiconductor layer is made of Al _e In _f Ga. _{1- (e + f)} N (0 ≦ e <1, 0 ≦ f ≦ 1, 0 ≦ e + f ≦ 1), the second nitride semiconductor layer is AlN, and the third nitride semiconductor layer is Al _a In _b Ga _{1− (a + b)} N (0 ≦ a <1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), and the fourth nitride semiconductor layer is A l _c In _d Ga _{1− (c + d)} N (0 ≦ c <1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1), and the first nitride semiconductor layer and the fourth nitride semiconductor layer Is characterized by a larger band gap energy than the third nitride semiconductor layer, which improves the confinement of the two-dimensional electron gas and improves the mobility, and can operate at high voltage and high frequency. Become.

It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows distribution of the carrier concentration by embodiment of this invention. It is a figure which shows distribution of the carrier concentration by embodiment of this invention. It is a figure which shows distribution of the two-dimensional electron gas concentration by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the structure of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention. It is a figure which shows an example of the manufacturing process of the heterojunction field effect transistor by embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment>
<Configuration>
First, the configuration of the heterojunction field effect transistor according to the embodiment of the present invention will be described.

  FIG. 1 is a diagram showing an example of the structure of a heterojunction field effect transistor according to an embodiment of the present invention.

As shown in FIG. 1, the heterojunction field effect transistor according to the present embodiment includes a first nitride semiconductor layer 2 (buffer layer) made of Al _0.05 Ga _0.95 N formed on a semi-insulating SiC substrate 1. A second nitride semiconductor layer 3 (barrier layer) made of AlN formed on the first nitride semiconductor layer 2, and a first nitride formed on the second nitride semiconductor layer 3. A third nitride semiconductor layer 4 (channel layer) made of GaN having a smaller band gap than the semiconductor layer 2 and the second nitride semiconductor layer 3, and the third nitride semiconductor layer 4; A fourth semiconductor layer 5 (barrier layer) made of Al _0.2 Ga _0.8 N having a larger band gap than the third nitride semiconductor layer 4 is provided.

  Further, on the surface of the fourth nitride semiconductor layer 5, an ohmic electrode was formed so as to face the gate electrode 8 made of Ni / Au formed as a Schottky electrode with the gate electrode 8 interposed therebetween. A source electrode 6 and a drain electrode 7 made of Ti / Al are provided. The element isolation region 9 is a region provided for isolating adjacent heterojunction field effect transistors. In addition to the source electrode 6, drain electrode 7, and gate electrode 8 on the surface of the fourth nitride semiconductor layer 5, an insulating film 10 is formed so as to cover.

2 shows the relationship between the band structure in the Al _0.2 Ga _0.8 N / GaN / AlN / Al _0.05 Ga _0.95 N structure, which is the epitaxial structure shown in FIG. 1, and the carrier distribution of the two-dimensional electron gas 11. The result calculated using the calculation simulator software is shown. Here, the first nitride semiconductor layer 2 is Al _0.05 Ga _0.95 N and has a thickness of 300 nm, the second nitride semiconductor layer 3 is AlN and has a thickness of 1 nm, and the third nitride semiconductor layer 4 is GaN and has a thickness. The thickness of the fourth nitride semiconductor layer 5 is 50 nm, Al _0.2 Ga _0.8 N, the thickness is 30 nm, the carrier concentration of each nitride semiconductor layer is 1 × 10 ¹⁶ cm ^−3, and the surface pinning energy of the fourth nitride semiconductor layer 5 is Was calculated as 1.42 eV.

  As shown in FIG. 2, the second nitride semiconductor layer 3 (AlN barrier layer) having the largest band gap among the nitride semiconductor layers shown in FIG. 1 is replaced with the third nitride semiconductor layer 4 (GaN channel layer). ), The distribution of the two-dimensional electron gas 11 is almost entirely confined near the interface between the fourth nitride semiconductor layer (AlGaN barrier layer) 5 and the third nitride semiconductor layer 4. It is done. By improving the confinement of the two-dimensional electron gas, even if the gate length of the gate electrode 8 is shortened, the modulation control of the two-dimensional electron gas 11 by the gate electrode 8 is possible (that is, the short channel effect is suppressed). Thus, it is possible to improve transistor characteristics in a high frequency region including efficiency improvement.

In FIG. 2, the first nitride semiconductor layer 2 has been described as being Al _0.05 Ga _0.95 N, but the carrier distribution of the two-dimensional electron gas in the case where the first nitride semiconductor layer 2 is GaN is illustrated in FIG. Shown in Each nitride semiconductor layer other than the first nitride semiconductor layer 2 is the same as that described in FIG.

  As shown in FIG. 3, the two-dimensional electron gas 11 distributed near the interface between the fourth nitride semiconductor layer 5 (AlGaN barrier layer) and the third nitride semiconductor layer 4 (GaN channel layer) is shown in FIG. The two-dimensional electron gas is also generated at the interface between the second nitride semiconductor layer 3 (AlN barrier layer) and the first nitride semiconductor layer 2 (GaN buffer layer). It has a channel structure. Therefore, the first nitride semiconductor is formed so that a double channel is not formed (that is, a two-dimensional electron gas is not generated at the interface between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2). The band gap of the layer 2 needs to be larger than the band gap of the third nitride semiconductor layer 4.

  2 and 3, the film thickness of the AlN layer, which is the second nitride semiconductor layer 3, is 1 nm. However, when the film thickness of the second nitride semiconductor layer 3 is increased (thicker). A channel is formed at the interface between the first nitride semiconductor layer 2 and the second nitride semiconductor layer 3 to form a double channel structure, which is not desirable because an increase in leakage current and a decrease in breakdown voltage occur. The second nitride semiconductor layer 3 has a large difference in band gap energy between the first nitride semiconductor layer 2 and the third nitride semiconductor layer 4 that are the upper and lower layers of the second nitride semiconductor layer 3. Therefore, a smaller (thin) film thickness of the second nitride semiconductor layer 3 is desirable because an abrupt band gap difference can be generated.

FIG. 4 shows the dependency of the two-dimensional electron gas concentration generated between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2 on the thickness of the AlN layer. Here, the first nitride semiconductor layer 2 is Al _0.05 Ga _0.95 N and has a thickness of 300 nm, the third nitride semiconductor layer 4 is GaN and has a thickness of 50 nm, and the fourth nitride semiconductor layer is Al _0.2 Ga _0.8 N. The film thickness was 30 nm, and the AlN film thickness of the second nitride semiconductor layer 3 was 1, 5, and 10 nm.

As shown in FIG. 4, when the thickness of the second nitride semiconductor layer 3 (AlN layer) increases, the conduction band level at the interface between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2 is increased. The level becomes lower than the Fermi level, and carriers are generated between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2 to increase the carrier concentration, thereby forming a double channel structure. End up. Therefore, it is desirable that the carrier concentration generated between the second nitride semiconductor layer 3 and the first nitride semiconductor layer 2 is lower than 1e ¹⁵ cm ^−3, which is the background level of the nitride semiconductor. In order not to form a double channel, the thickness of the second nitride semiconductor layer 3 is preferably 4 nm or less, and more preferably thinner, as shown in FIG. That is, the conductor level at the interface between the first nitride semiconductor layer 2 and the second nitride semiconductor layer 3 is preferably higher than the Fermi level.

  In the above description, the typical structure (see FIG. 1) of the heterojunction field effect transistor according to the present embodiment has been described. However, the same effects can be obtained even with the following structures. Hereinafter, each modification of the heterojunction field effect transistor according to the present embodiment will be described.

<Modification>
In FIG. 1 described above, the Al _0.2 Ga _0.8 N / GaN / AlN / Al _0.05 Ga _0.95 N structure has been described. However, the band gap of the fourth nitride semiconductor layer 5 is the band gap of the third nitride semiconductor layer 4. The first nitride semiconductor layer 2 and the third nitride semiconductor are larger and the band gap of the first nitride semiconductor layer 2 is larger than the band gap of the fourth nitride semiconductor layer 5. Even if the layer 4 and the fourth nitride semiconductor layer 5 have a structure in which the composition of Al, In, and Ga of AlxInyGa1- _{(x + y)} N is determined, the same effect as described above can be obtained. Further, the first nitride semiconductor layer 2 is made of Al _e In _f Ga _{1− (e + f} so that the band gap energy of the first nitride semiconductor layer 2 is larger than that of the third nitride semiconductor layer 4. ₎ Al of N (0 ≦ e <1, 0 ≦ f ≦ 1,0 ≦ e + f ≦ 1), in, have a structure decided the composition of Ga, the same effect as described above can be obtained.

A heterojunction field effect transistor made of a nitride semiconductor has a higher breakdown voltage as the breakdown electric field of the semiconductor material used for the channel layer is higher. Therefore, in the heterojunction field effect transistor according to the present embodiment, as described above, the band gap of the fourth nitride semiconductor layer 5 is larger than the band gap of the third nitride semiconductor layer 4, and the first After satisfying the condition that the band gap of the nitride semiconductor layer 2 is larger than the band gap of the fourth nitride semiconductor layer 5, the band gap energy of the third nitride semiconductor layer 4 is larger than the band gap energy of GaN. The third nitride semiconductor layer 4 has a structure in which the composition of Al, In, and Ga in AlxInyGa1- _{(x + y)} N is determined so that the third nitride semiconductor layer 4 becomes larger. In addition to the effect (when 4 is GaN), a higher breakdown voltage can be achieved.

  In the above (see FIG. 1), the second nitride semiconductor layer 3 is made of a binary alloy AlN layer, so that alloy scattering can be reduced. Further, the third nitride semiconductor layer 4 and the fourth nitride semiconductor layer 5 are formed with an AlN layer between them, alloy scattering can be further reduced, carrier mobility is improved, current value is increased, and transconductance is increased. By improving the improvement, it becomes possible to improve the high output and high frequency characteristics.

  Further, the semi-insulating SiC substrate 1 in FIG. 1 may be Si, sapphire, GaN, AlN, or the like.

  Further, in the semiconductor layer below the source electrode 6 and the drain electrode 7 shown in FIG. 1 and in at least a part of the semiconductor layer, the nitride semiconductor becomes an n-type impurity. A high-concentration n-type impurity region 11 that is a doped region may be formed. With such a structure, not only the contact resistance between the source electrode 6 and the drain electrode 7 and the fourth nitride semiconductor layer 5 in contact with each electrode is reduced, but also the third nitridation. The resistance between the two-dimensional electron gas 11 generated at the interface between the physical semiconductor layer 4 and the fourth nitride semiconductor layer 5 and the source electrode 6 and the drain electrode 7 can be reduced, and the transistor has high efficiency. This is advantageous for increasing the output by increasing the current and increasing the current, and can be said to be a more preferable structure. The impurity in the high-concentration n-type impurity region 12 doped with Si at a high concentration is not limited to Si, and it is sufficient that the n-type impurity is doped at a high concentration. It is only necessary that the material (O, C, N, vacancies, etc.) that forms the layer is doped. As a doping method, the high-concentration n-type impurity region 12 may be formed using an ion implantation method or a thermal diffusion method, and the nitride semiconductor layer below the source electrode 6 and the drain electrode 7 is etched. For example, n-GaN doped with an n-type impurity may be formed by regrowth after the removal. In FIG. 5, the high-concentration n-type impurity region 12 doped with an n-type impurity at a high concentration is formed from the surface of the nitride semiconductor layer to a region extending from the third nitride semiconductor layer 4 (channel layer). However, the above effect is not limited to this region, and the above effect is achieved if it is formed in at least a part of the nitride semiconductor layer below the source electrode 6 and the drain electrode 7 even if it is larger or smaller than the region. Is obtained.

  1 and 5, at least a part of the nitride semiconductor layer below the source electrode 6 and the drain electrode 7 may be removed as shown in FIG. That is, for example, as shown in FIG. 6, the source electrode 6 and the drain electrode 7 may be formed so as to be embedded in the fourth nitride semiconductor layer 5. With such a structure, the two-dimensional electron gas 11 generated at the interface between the third nitride semiconductor layer 4 (channel layer) and the fourth nitride semiconductor layer 5 (barrier layer), and the source electrode 6 and the drain electrode 7 can be reduced, which is advantageous for increasing the efficiency of the transistor and increasing the output by increasing the current, and can be said to be a more preferable structure. In FIG. 6, the fourth nitride semiconductor layer 5 (barrier layer) is removed from the surface of the nitride semiconductor layer to the region near the lower layer of the fourth nitride semiconductor layer 5. The limit in the depth direction is up to the interface between the third nitride semiconductor layer 4 and the fourth nitride semiconductor layer 5, and at least a part of the nitride semiconductor layer below the source electrode 6 and the drain electrode 7. If the inside is removed, the above effect can be obtained.

  Further, the source electrode 6 and the drain electrode 7 shown in FIGS. 1, 5 and 6 are not necessarily made of Ti / Al. If ohmic characteristics are obtained, Ti, Al, Nb, Hf, Zr, Sr, Ni, You may form with metals, such as Ta, Au, Pt, V, Mo, and W, or the multilayer film comprised from these.

  Further, the gate electrode 8 shown in FIGS. 1, 5, and 6 is configured so that the bottom surface of the gate electrode 8 does not contact the surface of the fourth nitride semiconductor layer 5 (barrier layer) as shown in FIG. 7. Compared with the case where the bottom surface of the gate electrode 8 is in contact with the surface of the fourth nitride semiconductor layer 5, the current collapse can be suppressed and the mutual conductance can be increased.

  Further, the gate electrode 8 shown in FIGS. 1, 5 to 7 does not necessarily have a quadrangular cross section as shown in each figure. For example, a gate electrode 81 having a T-type or Y-type structure as shown in FIG. There may be. With such a structure, the gate resistance can be reduced while maintaining the area where the gate electrode 81 is in contact with the nitride semiconductor layer.

  FIG. 8 shows a structure in which the umbrella of the T-type gate electrode 81 (the fourth nitride semiconductor layer 5 side of the umbrella portion in the gate electrode 81) is not in contact with the insulating film 10. As shown in the figure, the structure in which the umbrella of the T-shaped gate electrode 81 is in contact with the insulating film 10 reduces the electric field concentrated on the edge portion of the gate electrode 81 on the drain electrode 7 side during high voltage operation. Thus, current collapse can be suppressed and the breakdown voltage can be increased.

  Further, as shown in FIG. 10, the insulating film 10 may be formed only under the umbrella of the gate electrode 81. With such a structure, the capacitance generated between the source electrode 6 and the gate electrode 81 or between the gate electrode 81 and the drain electrode 7 can be reduced, and the gain and efficiency during high-frequency operation can be reduced. It becomes possible to improve.

  In addition, the insulating film 10 shown in FIGS. 1, 5 to 10 is an oxide, nitride, oxynitride or the like of at least one kind of atoms among Al, Ga, Si, Hf, Ti, Zr, Ta, V, and the like. Alternatively, it may be formed of a multilayer film composed of these.

The gate electrodes 8 and 81 shown in FIGS. 1 to 5 are not necessarily made of Ni / Au, but are made of metals such as Ti, Al, Pt, Au, Ni, and Pd, IrSi, PtSi, NiSi _{2, and the} like. It may be formed of silicide, nitride metal such as TiN, WN, TaN, or a multilayer film composed of these.

  Note that it is not necessary to employ all of the above-described structures individually, and for example, as shown in FIG.

  In the above, only the minimum necessary elements that operate as a transistor have been described. However, the heterojunction field effect transistor according to the present embodiment is finally used as a device in a structure in which wirings, via holes, and the like are formed. .

<Manufacturing process>
Next, a manufacturing process of the heterojunction field effect transistor according to the present embodiment will be described.

  12 to 22 are diagrams showing an example of a manufacturing process of the heterojunction field effect transistor according to the embodiment of the present invention. In these drawings, the constituent elements denoted by the same reference numerals as those in FIGS. 1 and 5 to 11 indicate the same or corresponding constituent elements.

First, as shown in FIG. 12, a substrate 1 made of, for example, sapphire, SiC (silicon carbide), GaN, or Si is prepared. Next, the first nitride semiconductor layer 2 and AlN are formed on the main surface of the substrate 1 by MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition), for example. A second nitride semiconductor layer 3, a third nitride semiconductor layer 4 that is a channel layer, and a fourth nitride semiconductor layer 5 that is a barrier layer are sequentially stacked. Hereinafter, Al _0.2 Ga _0.8 N (fourth nitride semiconductor layer) / GaN (third nitride semiconductor layer) / AlN (second nitride semiconductor layer) / Al _0.05 Ga _0.95 N (first nitride) An example of epitaxial growth of the structure of the (physical semiconductor layer) on the SiC substrate will be described.

  The band gap energy of the first nitride semiconductor layer 2 is such that the band of the third nitride semiconductor layer 4 does not form a channel at the interface with the second nitride semiconductor layer 3 (AlN layer). It needs to be larger than the gap energy.

Further, the film thickness of the first nitride semiconductor layer 2 is desirably a thickness that does not affect the upper epitaxial crystal layer (second nitride semiconductor layer 3) due to lattice mismatch with the substrate 1. . Here, the first nitride semiconductor layer 2 was Al _0.03 Ga _0.07 N, and the film thickness was 300 nm. Since the second nitride semiconductor layer 3 (AlN layer) has the largest band gap energy among the nitride semiconductor layers, the valence band of AlN becomes a barrier (barrier layer) against electrons. Accordingly, the thickness of the second nitride semiconductor layer 3 that is as thin as about 4 nm or less is sharper between adjacent layers (the first nitride semiconductor layer and the third nitride semiconductor layer). This is desirable because a large band gap difference can be generated. If the thickness of the second nitride semiconductor layer 3 is greater than 4 nm, a channel is formed at the interface with the first nitride semiconductor layer 2 to form a double channel structure, resulting in an increase in leakage current and a decrease in breakdown voltage. In order to suppress these, the film thickness of the second nitride semiconductor layer 3 is desirably 4 nm or less. In the present embodiment, the thickness of the second nitride semiconductor layer 3 (AlN layer) is 1 nm. The third nitride semiconductor layer 4 (channel layer) was GaN and the film thickness was 50 nm. The fourth nitride semiconductor layer 5 (barrier layer) was Al _0.2 Ga _0.8 N and the film thickness was 30 nm.

The impurity concentration of the first nitride semiconductor layer 2, the second nitride semiconductor layer 3, the third nitride semiconductor layer 4, and the fourth nitride semiconductor layer 5 is 1 × 10 ¹⁸ cm ⁻³ or less. In particular, the impurity concentration of the fourth nitride semiconductor layer 5 (barrier layer) is set to 1 × 10 ¹ cm ⁻³ or less in order to obtain a high breakdown voltage layer. Here, the conductivity type of the impurity is always n-type. In the nitride semiconductor layer, even when impurities are not intentionally introduced (non-doped), the impurities enter the nitride semiconductor from the growth furnace or atmospheric gas, and the nitride semiconductor contains n-type impurities. Become. Therefore, it is sufficient that the actual impurity concentration is 1 × 10 ¹ cm ⁻³ or less even when non-doped during crystal growth.

  In addition, after the third nitride semiconductor layer 4 is formed, the above-described epitaxial structure can be formed by forming the fourth nitride semiconductor layer 5 as a barrier layer by continuing to form the AlN layer. . As the thickness of the AlN layer at this time, it is desirable that a thin layer of about 4 nm or less can cause a steep band gap difference as in the case of the second nitride semiconductor layer 3 (AlN barrier layer). In particular, it is more desirable to set the thickness to 1 to 2 nm. A nitride semiconductor heterojunction field effect transistor having the above-described structure can be manufactured on an epitaxial substrate having such an epitaxial structure by a transistor manufacturing method described later.

Next, as shown in FIG. 13, using a resist pattern or the like as a mask 13, an ion implantation method or the like is used in at least a part of the nitride semiconductor layer below the region where the source electrode 6 and the drain electrode 7 are formed. Then, under the conditions of implantation dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁷ (cm ⁻² ) and implantation energy of 10 to 1000 (keV), ions 14 such as Si that become n-type in each nitride semiconductor layer are desired. A high concentration n-type impurity region 12 is formed by implanting the region and subsequent heat treatment. The impurity concentration of the high-concentration n-type impurity region 12 is preferably equal to or higher than that used when intentionally forming n-type GaN or AlGaN during crystal growth, for example, 1 × 10 ¹⁸ cm ⁻³ or more. Is greater than or ^{equal to} 1 × 10 ^{19 -cm 3} or higher. One desirable distribution of impurities in the high-concentration n-type impurity region 12 is a fourth nitride semiconductor layer 5 (barrier layer) in which electrons flow from the semiconductor surface under the source electrode 6 and the drain electrode 7 and a third one. There is a structure having a high impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more in a region up to about 10 nm at the interface with the nitride semiconductor layer 4 (channel layer) and on the channel layer side thereof. The injection energy and implantation dose satisfying the above conditions can be determined by simulating the ion range using Monte Carlo calculation with the implantation energy and the structure of the irradiation object as parameters. I can decide. Further, in order to suppress the atoms (Al, Ga, In, N, etc.) constituting the fourth nitride semiconductor layer 5 from being injected into the vacuum by the implanted ions, the fourth nitride semiconductor 5 A nitride film (SiN _x , AlN, etc.) or an oxide film (SiO ₂ , Al ₂ O _3, etc.) of about 10-100 nm is formed thereon, and then a resist pattern as an implantation mask may be formed (FIG. 14). reference). Thereafter, heat treatment is performed to activate the implanted ions, thereby reducing the resistance of the high-concentration n-type impurity region 12 below the source electrode 6 and the drain electrode 7. In order to prevent nitrogen atoms from escaping from the semiconductor surface during this heat treatment, a nitride film (SiNx, AlN, etc.) of about 10 to 100 nm, an oxide film, etc. (SiO ₂ , SiO ₂ , etc.) are formed on the fourth semiconductor layer 5. Heat treatment may be performed after the surface of the nitride semiconductor is covered with Al ₂ O ₃ or the like.

  Next, as shown in FIG. 15, after removing the mask 13, for example, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Pt, V, Mo, and W, or from these metals A source electrode 6 and a drain electrode 7 composed of a multilayer film are deposited by vapor deposition or sputtering, and formed by a lift-off method or the like. Note that heat treatment may be performed after electrode formation to form a reaction layer (alloy layer) with the semiconductor layer, and contact resistance and access resistance may be further reduced.

  Next, as shown in FIG. 16, using the resist pattern or the like as a mask 13, from the first nitride semiconductor layer 2 to the fourth nitride semiconductor layer 5 outside the region for forming the transistor, for example, He, N, O , Mg, Ar, Ca, Fe, Zn, Sr, Ba, etc. are used to form the element isolation region 9 by using an ion implantation method (see FIG. 16) for irradiating the ions 14, etching, or the like.

Next, as shown in FIG. 17, after removing the mask 13, Ti, Al, Pt, Au, Ni, metals such as Pd or IrSi, PtSi, silicide such as NiSi ₂ or TiN,,, WN, TaN, etc. A gate electrode 8 made of a nitride metal or a multilayer film composed of these is deposited by vapor deposition or sputtering, and formed by lift-off or the like.

  Next, as shown in FIG. 18, at least one kind of oxide, nitride, oxynitride, or the like of at least one of Al, Ga, Si, Hf, Ti, Zr, Ta, V, or the like is configured. The insulating film 10 made of a multilayer film is formed by plasma CVD, Cat-CVD, or sputtering.

  By the above method, a heterojunction field effect transistor having the structure shown in FIG. 1 can be manufactured. Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device through a formation process of wiring, via holes, and the like. In the above, as an example of the order of the manufacturing process after the epitaxial crystal is formed, the low resistance layer is formed under the source electrode 6 and the drain electrode 7, the source electrode 6 and the drain electrode 7 are formed over the low resistance layer, the element The manufacturing of the isolation region 9, the formation of the gate electrode 8, and the formation of the insulating film 10 has been described in this order. However, element isolation may be performed after the formation of the gate electrode 8, and the insulating film 10 may be formed. The gate electrode 8 may be formed after the insulating film 10 in the gate forming region is removed, or element isolation is performed after the insulating film 10 is formed, and then the gate electrode 8 is removed after removing the insulating film 10 in the gate forming region. May be formed.

  Note that when the structure shown in FIG. 12 is epitaxially grown on the substrate 1 using the MOCVD method, trimethylammonium, trimethylgallium, trimethylindium, ammonia, or an n-type dopant source gas, which is a nitride semiconductor source gas, is used. The various nitride semiconductor heterojunction field effect types shown in FIG. 1 are obtained by adjusting the flow rate, pressure, temperature, and time of the silane, etc., so that each nitride semiconductor layer has a desired composition, film thickness, and doping concentration. A transistor can be manufactured.

Use also before the ion implantation to be an n-type impurity to form regions of the source electrode 6 and drain electrode 7 shown in FIG. 13 and 14, as shown in FIG. 19, a resist pattern such as a mask 13, a Cl ₂ or the like The nitride semiconductor heterojunction having the structure shown in FIG. 6 is removed by removing at least a part of the nitride semiconductor layer below the region where the source electrode 6 and the drain electrode 7 are formed by a dry etching method or the like. A field effect transistor can be manufactured. The formation process of the low resistance layer below the formation region of the source electrode 6 and the drain electrode 7 may be either before or after the etching process shown in FIG. By forming the source electrode 6 and the drain electrode 7 on the formed low resistance layer by a lift-off method or the like, a nitride semiconductor heterojunction field effect transistor having a structure as shown in FIG. 6 can be manufactured.

In addition, before forming the gate electrode 8 shown in FIG. 17, as shown in FIG. 20, a gate formation region in which the gate electrode 8 is formed by a dry etching method using Cl ₂ or the like using a resist pattern or the like as a mask 131. Part of the 15th fourth nitride semiconductor layer 5 is removed. When etching is performed, a desired etching depth can be formed by adjusting the etching time and the gas flow rate, and then the gate electrode 8 is formed by the method shown in FIG. A nitride semiconductor heterojunction field effect transistor having a structure having a recess depth as shown can be manufactured.

  In addition, before forming the gate electrode 8 shown in FIG. 17, as shown in FIG. 21, the surface of the nitride semiconductor layer is formed by using, for example, an evaporation method, a plasma CVD method, a Cat-CVD method, an ALE method, or the like. , Ga, Si, Hf, Ti, Zr, Ta, V, etc., deposit an insulating film 10 made of an oxide, nitride, oxynitride or the like containing at least one kind of atom to form the gate electrode 8. The insulating film 10 in the gate forming region 15 is removed by dry etching or wet etching through a resist mask 131 having an opening in the gate forming region 15 or an oxide film mask. After removing the mask, an electrode metal that becomes a gate metal is deposited by an evaporation method using a resist pattern having an opening wider than the opening of the insulating film 10 opened by etching, and a gate electrode 81 is formed by a lift-off method or the like. A nitride semiconductor field effect transistor having the structure shown in FIG. 9 can be manufactured.

  Further, in order to finally use as a device, a part of the insulating film 10 formed so as to cover the source electrode 6 and the drain electrode 7 is removed by wet etching using, for example, hydrofluoric acid, It is necessary to form a wiring electrode. Further, an insulating film that can be easily removed by wet etching after the insulating film 10 is formed, for example, an insulating film 110 such as SiO is formed. After that, as shown in FIG. 22, the insulating film 110 and the insulating film 10 in the gate forming region 15 are sequentially removed by dry etching or wet etching through a resist mask having an opening in the gate forming region 15 where the gate electrode 8 is formed. To do. After the removal of the mask 131, an electrode metal to be a gate metal is deposited by an evaporation method using an insulating film 110 opened by etching and a resist pattern having an opening wider than the opening of the insulating film 10, and a gate electrode is formed by a lift-off method or the like. 81 is formed. Then, the nitride semiconductor field effect transistor having the structure shown in FIG. 8 having the structure without the insulating film 110 under the gate electrode 81 is removed by removing the insulating film 110 that is easily wet-etched with, for example, buffered hydrofluoric acid. Can be produced. Furthermore, by adjusting the wet etching process conditions (time and concentration), a nitride semiconductor field effect transistor having the structure shown in FIG. 10 in which the insulating film 110 is left in a desired region can be manufactured.

  Further, after forming the gate recess structure, the gate electrode 8 having various shapes may be formed.

  Further, the formation of the low resistance region (high concentration n-type impurity region 12) and the formation of the source electrode 6 and the drain electrode 7 below the source / drain electrode formation region shown in FIGS. The three steps of forming and forming the gate electrodes 8 and 81 shown in FIGS. 17 and 20 to 22 are not necessarily performed in this order, and the order of the steps may be changed. For example, the element isolation region 9 may be formed before the source electrode 6 and the drain electrode 7 are formed. Further, after forming the recess, the insulating film, and the gate electrode in this order, the insulating film may be formed again to enhance the insulating properties on the side surfaces of the gate electrode and the fourth nitride semiconductor layer 5.

  Moreover, it is not necessary to employ all the processes described above, and a structure as shown in FIG. 11 can be formed by a process combining them.

  From the above, according to the present embodiment, in the heterojunction field effect transistor made of a nitride semiconductor, the thin second nitride semiconductor layer is formed immediately below the third nitride semiconductor layer 4 (channel layer). By having a structure having 3 (AlN layer), confinement of the two-dimensional electron gas at the interface between the fourth nitride semiconductor layer 5 (barrier layer) and the third nitride semiconductor layer 4 (channel layer) And a good pinch-off characteristic is obtained. In addition, the influence of alloy scattering of a two-dimensional electron gas can be reduced as compared with a structure having an AlGaN layer, which is a ternary alloy, immediately below the channel layer described in the prior art (for example, Patent Document 1). Can be suppressed. Further, when the thickness of the second nitride semiconductor layer 3 (AlN layer) is set to 4 nm or less, a sharp band is formed between the upper and lower layers (the second nitride semiconductor layer and the fourth nitride semiconductor layer). Since a gap difference can be generated and a double channel structure can be avoided, leakage current can be reduced and breakdown voltage can be improved. In addition, since the third nitride semiconductor layer 4 (channel layer) can be thickened without increasing the confinement width of the two-dimensional electron gas, the crystallinity of the third nitride semiconductor layer 4 (channel layer) can be increased. Thus, the crystallinity and surface morphology of the hetero interface with the fourth nitride semiconductor layer 5 (barrier layer) are improved, and the mobility can be improved. Thereby, even if the gate length is shortened, the short channel effect is suppressed, so that it is possible to improve the high frequency characteristics, increase the efficiency, and increase the output by improving the mobility.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention.

  DESCRIPTION OF SYMBOLS 1 Semi-insulating SiC substrate, 2 1st nitride semiconductor layer, 3rd 2nd nitride semiconductor layer, 4th 3rd nitride semiconductor layer, 5th 4th nitride semiconductor layer, 6 source electrode, 7 drain electrode 8 gate electrode, 9 element isolation region, 10 insulating film, 11 two-dimensional electron gas, 12 high-concentration n-type impurity region, 13 mask, 14 ions, 15 gate formation region, 81 gate electrode, 110 insulating film, 131 mask.

Claims (6)

A heterojunction field effect transistor made of a nitride semiconductor,
A first nitride semiconductor layer that is a buffer layer formed on the substrate;
A second nitride semiconductor layer which is a barrier layer formed on the first nitride semiconductor layer;
A third nitride semiconductor layer which is a channel layer formed on the second nitride semiconductor layer;
With
The second nitride semiconductor layer is AlN, and the third nitride semiconductor layer is Al _a In _b Ga _{1-(a + b)} N (0 ≦ a <1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). A heterojunction field-effect transistor. A fourth nitride semiconductor layer that is a barrier layer formed on the third nitride semiconductor layer;
The fourth nitride semiconductor layer is _{Al c In d Ga 1- (c} + d) N (0 ≦ c <1,0 ≦ d ≦ 1,0 ≦ c + d ≦ 1), the fourth nitride The heterojunction field effect transistor according to claim 1, wherein the semiconductor layer has a band gap energy larger than that of the third nitride semiconductor layer. The first nitride semiconductor layer is _{1- Al e In f Ga (e} + f) N (0 ≦ e <1, 0 ≦ f ≦ 1,0 ≦ e + f ≦ 1), the first nitride 3. The heterojunction field effect transistor according to claim 1, wherein the semiconductor layer has a band gap energy larger than that of the third nitride semiconductor layer.   4. The conductor level at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer is higher than the Fermi level. Heterojunction field effect transistor.   The heterojunction field effect transistor according to any one of claims 1 to 4, wherein the third nitride semiconductor layer has a band gap energy larger than that of GaN. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a first nitride semiconductor layer as a buffer layer on a substrate;
(B) forming a second nitride semiconductor layer as a barrier layer on the first nitride semiconductor layer;
(C) forming a third nitride semiconductor layer as a channel layer on the second nitride semiconductor layer;
(D) forming a fourth nitride semiconductor layer as a barrier layer on the third nitride semiconductor layer;
With
The first nitride semiconductor layer is _{1- Al e In f Ga (e} + f) N (0 ≦ e <1, 0 ≦ f ≦ 1,0 ≦ e + f ≦ 1), the second nitride The semiconductor layer is AlN, and the third nitride semiconductor layer is Al _a In _b Ga _{1- (a + b)} N (0 ≦ a <1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). The fourth nitride semiconductor layer is Al _c In _d Ga _{1- (c + d)} N (0 ≦ c <1, 0 ≦ d ≦ 1, 0 ≦ c + d ≦ 1),
The method for manufacturing a heterojunction field effect transistor, wherein the first nitride semiconductor layer and the fourth nitride semiconductor layer have a band gap energy larger than that of the third nitride semiconductor layer.

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