JP2011210751A - Group iii nitride semiconductor element, method of manufacturing group iii nitride semiconductor element, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor element that has low access resistance and ON resistance, a method of manufacturing the group III nitride semiconductor element, and an electronic device.SOLUTION: In the group III nitride semiconductor, a barrier layer 902 is formed having a heterojunction over a channel layer 901; a part of an upper part of the channel layer 901 and the barrier 902 above thereof are removed to form a recess; an n-type conductive layer region 904 is formed at a part of the channel layer 901 and barrier layer 902; the n-type conductive layer region 904 includes a surface of the recess, and has a depth Tof the n-type conductive layer region 904 of ≥15 nm in terms of measured value from each part of a surface of the n-type conductive layer region 904 in a direction perpendicular to the surface; and ohmic electrodes 906 and 907 are in ohmic contact with the n-type conductive layer region through the surface of the recess.

Description

  The present invention relates to a group III nitride semiconductor device, a method for manufacturing a group III nitride semiconductor device, and an electronic device.

Recently, in a GaN-based heterojunction field effect transistor, a dopant such as Si is ion-implanted into a semiconductor structure (for example, an AlGaN / GaN structure) under an ohmic electrode to reduce access resistance, on-resistance, and the like. Attempts have been made to form n ⁺ -type layers.

  The cross-sectional view of FIG. 4 schematically shows an example of the structure of this type of GaN-based heterojunction field effect transistor (commonly known as HEMT: High Electron Mobility Transistor). Note that a field effect transistor may be abbreviated as an FET, and a heterojunction field effect transistor (HEMT) is a kind of field effect transistor. As shown in the figure, this HEMT has a GaN layer 901 formed on a substrate (not shown) via a buffer layer (not shown), and an AlGaN layer 902 is heterojunction on the upper surface of the GaN layer 901. . The GaN layer 901 has a higher electron affinity than the AlGaN layer 902 and has a small band gap. A gate electrode 905, a source electrode 906, and a drain electrode 907 (ohmic electrode) are formed on the AlGaN layer 902, and the source electrode 906 and the drain electrode 907 are arranged so as to sandwich the gate electrode 905. An upper portion of the GaN layer 901 and a portion below the source electrode 906 in the AlGaN layer form an n-type impurity implantation region 904. Similarly, the upper part of the GaN layer 901 and the part below the drain electrode 907 in the AlGaN layer 902 also form an n-type impurity implantation region 904. When the HEMT is in an on state, a channel of the two-dimensional electron gas layer 903 is formed at and near the heterojunction interface between the AlGaN layer 902 and the GaN layer 901, and a current flows through the two-dimensional electron gas layer 903. As a prior art document regarding such a GaN-based HEMT, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2007-335768) can be cited.

In addition, for the purpose of reducing the ohmic contact resistance value, trench (mesa) formation and n ⁺ -type impurity diffusion are used in the ohmic electrode portion. FIG. 6 shows an example of the structure of such a HEMT. As shown in the figure, this HEMT has a GaN layer 901 formed on a substrate (not shown), and a barrier layer 909 and an AlGaN layer 902 are stacked above the GaN layer 901 in the above order. The barrier layer 909 and the AlGaN layer 902 are heterojunction with the GaN layer 901. The GaN layer 901 has a higher electron affinity than the AlGaN layer 902 and has a small band gap. The source electrode 906 and the drain electrode 907 are arranged so as to sandwich the gate electrode 905. In this HEMT, when forming ohmic electrodes (source electrode 906 and drain electrode 907), first, a trench (mesa) 101 reaching the upper part of the GaN layer 901 is formed in the vicinity of the ohmic electrode forming portion. Next, an impurity diffusion source is deposited on the trench (mesa) 101, and further, n-type impurity is diffused and activated by annealing to form an n-type impurity implantation region 904. After removing the impurity diffusion source, ohmic electrodes (source electrode 906 and drain electrode 907) are formed on the n-type impurity implantation region 904. As a prior art document regarding such a GaN-based HEMT, for example, Patent Document 2 (Japanese Patent Laid-Open No. 2007-329350) can be cited.

JP2007-335768 JP2007-329350A

  In the group III nitride semiconductor device, in order to obtain higher performance, it is required to further reduce the access resistance and the on-resistance.

  Accordingly, it is an object of the present invention to provide a group III nitride semiconductor device having a low access resistance and low on-resistance, a method for manufacturing a group III nitride semiconductor device, and an electronic device.

In order to achieve the above object, the group III nitride semiconductor device of the present invention comprises:
Including a channel layer, a barrier layer, and an ohmic electrode;
The channel layer and the barrier layer are formed of a group III nitride semiconductor,
The barrier layer is heterojunction above the channel layer;
The upper part of the channel layer and the barrier layer thereabove are removed to form a recess,
An n-type conductive layer region is formed in part of the channel layer and the barrier layer;
The n-type conductive layer region includes the surface of the recess,
A depth of the n-type conductive layer region is 15 nm or more in a measured value in a direction perpendicular to the surface from each part of the surface of the n-type conductive layer region;
The ohmic electrode is in ohmic contact with the n-type conductive layer region through the surface of the recess.

The manufacturing method of the group III nitride semiconductor device of the present invention,
A channel layer forming step of forming a channel layer from a group III nitride semiconductor;
A barrier layer forming step for forming a barrier layer by heterojunction a group III nitride semiconductor above the channel layer;
A recess forming step of forming a recess by removing a portion of the upper portion of the channel layer and the barrier layer thereabove;
The region including the surface of the recess is doped with n-type impurity ions by accelerating by potential difference so as to reach a depth of 15 nm or more from each part of the surface of the region in a measured value perpendicular to the surface. An n-type conductive layer region forming step of forming an n-type conductive layer region by being activated by
An ohmic electrode forming step of forming an ohmic electrode in ohmic contact with the n-type conductive layer region through the surface of the recess.

  An electronic device according to the present invention includes the group III nitride semiconductor element according to the present invention.

  According to the present invention, it is possible to provide a group III nitride semiconductor device having a low access resistance and low on-resistance, a method for manufacturing a group III nitride semiconductor device, and an electronic device.

It is sectional drawing which shows an example of the group III nitride semiconductor element of this invention. FIG. 3 is a cross-sectional view schematically showing a resistance component around an ohmic electrode in the group III nitride semiconductor device of FIG. 1. It is sectional drawing which illustrates the other shape of the recessed part (recessed part) in the group III nitride semiconductor element of this invention. It is sectional drawing which shows an example of the group III nitride semiconductor element relevant to this invention. It is sectional drawing which shows another example of the group III nitride semiconductor element relevant to this invention. It is sectional drawing which shows another example of the group III nitride semiconductor element relevant to this invention.

  In the group III nitride semiconductor device of the present invention, the “on resistance” is between the positive bias application side and the negative bias application side when the voltage is on (voltage application) (for example, between the source electrode and the drain electrode). Or between the anode and cathode). “Access resistance” refers to the electrical resistance between an ohmic electrode and a two-dimensional electron gas (2DEG). “Contact resistance” refers to the resistance between two parts in direct contact. For example, “ohmic contact resistance” refers to an ohmic electrode (source electrode, drain electrode, anode electrode, cathode electrode, etc.) directly with a barrier layer. When in contact, it refers to the electrical resistance between the ohmic electrode and the barrier layer.

  In the present invention, “above” and “above” may be in direct contact with the upper surface without other components unless otherwise specified, and even if other components exist between them. good. The same applies to “down” and “down”. Further, “on the top surface” means a state in which the top surface is in direct contact with no other components. The same applies to “on the bottom surface”.

In the present invention, when the n-type impurity (donor impurity) concentration or the like is expressed by volume density (cm ⁻³ or the like), the volume density with respect to the number of atoms is expressed unless otherwise specified. Similarly, when the effective dose amount of n-type impurity ions is expressed by area density (cm ^-2 etc.), the area density with respect to the number of atoms is expressed unless otherwise specified. The “effective dose amount” refers to an actual dose amount that has reached the upper surface of the electron absorption layer after subtracting a loss such as absorption by the through film.

  In the present invention, the ionized donor impurity concentration (concentration of ionized n-type impurity) means a concentration in a state where no voltage is applied to any electrode of the group III nitride semiconductor element unless otherwise specified.

In the present invention, “composition” and “composition ratio” refer to, for example, the numerical value of x in the semiconductor layer represented by the composition of Al _x Ga _1-x N as “Al composition ratio”. In the present invention, when the composition or composition ratio of the semiconductor layer is defined, impurities (dopants) that develop conductivity and the like are not considered as elements constituting the semiconductor layer. For example, a p-type GaN layer and an n-type GaN layer are different in impurities (dopants) but have the same composition. For example, when there is an n-type GaN layer and an n ⁺ GaN layer having a higher impurity concentration, their compositions are assumed to be the same.

  Hereinafter, the present invention will be described more specifically with reference to the drawings. However, the present invention is not limited by the following description. In the drawings, similar components are denoted by the same reference numerals, and description of overlapping portions may be omitted as appropriate. In the cross-sectional view, the dimensional ratio of each part is different from the actual one for convenience of explanation.

[First Embodiment]
The cross-sectional view of FIG. 1A shows an example of the structure of a group III nitride semiconductor device of the present invention. The group III nitride semiconductor device of the figure is a heterojunction field effect transistor (HEMT). As shown, the HEMT includes a channel layer 901, a plurality of barrier layers 909 and 902, and ohmic electrodes 906 and 907. Reference numeral 906 denotes a source electrode, and reference numeral 907 denotes a drain electrode. The channel layer 901, the barrier layer 909, and the barrier layer 902 are made of a group III nitride semiconductor. The channel layer 901, the barrier layer 909, and the barrier layer 902 are stacked in the above order on a substrate (not shown). The barrier layers 909 and 902 are heterojunction above the channel layer 901. The channel layer 901 is made of, for example, GaN. The barrier layer 909 is made of, for example, AlN. The barrier layer 902 is made of, for example, AlGaN. In the channel layer 901, a heterojunction channel (two-dimensional electron gas layer) 903 is formed in the vicinity of the heterojunction interface with the barrier layer 902. The left and right end portions of the channel layer 901 and the barrier layers 909 and 902 thereabove are removed to form recesses. In the figure, the surface of the recess has a side surface and a bottom surface. In the same figure, the side surface of the recess has an inclination angle with respect to the heterojunction interface. Note that the left and right end portions of the channel layer 901 and the upper portion 101 forming these recesses may be hereinafter referred to as “mesa”. The depth of the mesa 101 is not particularly limited except that it is deeper than the heterojunction channel 903, but it is usually sufficient if it is 450 mm or more. Note that 1 mm is equal to 1 × 10 ⁻¹⁰ m (0.1 nm). An n-type conductive layer region 904 is formed in part of the channel layer 901, the barrier layer 909, and the barrier layer 902. The n-type conductive layer region 904 includes a side surface and a bottom surface of the recess. The depth T _imp of the n-type conductive layer region 904 is 15 nm or more as measured from each part of the surface of the n-type conductive layer region 904 in the direction perpendicular to the surface. The ohmic electrodes (source electrode 906 and drain electrode 907) are in ohmic contact with the n-type conductive layer region 904 through the side and bottom surfaces of the recess. In addition, the HEMT in the figure further includes a gate electrode 905. The gate electrode 905 is provided on (above) the barrier layer 902 and is disposed between the source electrode 906 and the drain electrode 907. In the present invention, in the n-type conductive layer region, the conduction band lower energy level of the barrier layer (for example, AlGaN) and the channel layer (for example, GaN), which are semiconductors, becomes lower than the Fermi level by n-type impurities. Thus, it has high conductivity by being in a degenerated state. The depth of the n-type conductive layer region measured from the upper surface of the barrier layer in a direction perpendicular to the upper surface is preferably deeper than the depth from the upper surface of the barrier layer to the heterojunction channel (two-dimensional electron gas). In the present invention, the depth of the n-type conductive layer region needs to be 15 nm or more as a measured value in a direction perpendicular to the surface from each part of the surface of the n-type conductive layer region. The depth of the n-type conductive layer region is preferably 20 nm or more, more preferably 45 nm or more. The upper limit value of the depth is not particularly limited, but is, for example, 300 nm or less.

  FIG. 1B shows the structure of another example of the group III nitride semiconductor device of the present invention. The group III nitride semiconductor device of the figure is a heterojunction field effect transistor (HEMT). The structure of this HEMT is the same as that of the HEMT in FIG. 1A except that the barrier layer is only one layer 902 and the barrier layer 902 is in direct contact with the upper surface of the channel layer 901. FIG. 1C shows the structure of still another example of the group III nitride semiconductor device of the present invention. The structure of this group III nitride semiconductor device is the same as that of FIG. 1B except that the gate electrode 905 is not provided.

  As described above, in the group III nitride semiconductor device of the present invention, an n-type conductive layer region is formed in part of the channel layer and the barrier layer. The n-type conductive layer region includes a surface (for example, a side surface and a bottom surface) of the recess from which a part of an upper portion of the channel layer and the barrier layer above the channel layer are removed. The depth of the n-type conductive layer region is 15 nm or more as measured in the direction perpendicular to the surface from each part of the surface of the n-type conductive layer region. The ohmic electrode is in ohmic contact with the n-type conductive layer region through the surface (for example, side surface and bottom surface) of the recess. Thereby, in the group III nitride semiconductor device of the present invention, the access resistance between the ohmic electrode and the two-dimensional electron gas (2DEG) in the channel layer is reduced, and thus the on-resistance is reduced. ing. Further, the group III nitride semiconductor device of the present invention may or may not contain components other than these as appropriate. For example, the group III nitride semiconductor device of the present invention may include a gate electrode as shown in FIGS. 1A and 1B, or may include a gate electrode as shown in FIG. It does not have to be. In addition, although the gate electrode is illustrated in FIGS. 1A and 1B as being in direct contact with the upper surface of the barrier layer 902, the present invention is not limited to this. For example, the group III nitride semiconductor device of the present invention may further include a gate insulating film, and the gate electrode may be formed above the barrier layer via the gate insulating film. Further, for example, there may be no other components between the barrier layer and the channel layer as shown in FIGS. 1A to 1C, but other components may exist. .

  Further, in order to further effectively reduce the access resistance between the ohmic electrode and the 2DEG, the width of the heterojunction interface in the n-type conductive layer region is set so that the surface of the n-type conductive layer region The thickness is preferably 50 nm or more in a direction perpendicular to a line where the heterojunction interface intersects. In the heterojunction interface, the width in the “perpendicular direction to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect” is, for example, the sign W in FIGS. The width shown. In the n-type conductive layer region, the width of the heterojunction interface is preferably 100 nm or more in a direction perpendicular to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect. In the n-type conductive layer region, the upper limit value of the width of the heterojunction interface is not particularly limited, but from the viewpoint of reducing access resistance, for example, the surface of the n-type conductive layer region and the heterojunction interface intersect. It is 3 μm or less in the direction perpendicular to the line. Details will be described later.

In the group III nitride semiconductor device of the present invention, in the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 5 ° C. or more and 35 ° C. or less. It is preferably 1 × 10 ¹⁹ cm ⁻³ or more under the temperature conditions of When the operating temperature of the group III nitride semiconductor device of the present invention is room temperature, that is, 5 ° C. or more and 35 ° C. or less, if the concentration of the ionized n-type impurity satisfies the above condition, the ohmic electrode and the two-dimensional electron gas This is because it is easy to reduce the access resistance to (2DEG). However, depending on the use of the group III nitride semiconductor device of the present invention, the operating temperature may differ greatly from room temperature. For example, the group III nitride semiconductor device of the present invention is operated in an engine room of an automobile. In such a case, in the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 under a temperature condition of 5 ° C. or more and 35 ° C. or less. It is preferable that it is more than ^x10 < ¹⁹ > cm < ^-3 >. The operating temperature of the group III nitride semiconductor device of the present invention is not particularly limited, and is, for example, room temperature. However, when operating in the engine room of the automobile, it is, for example, 5 ° C. or higher and 250 ° C. or lower. The operating environment of the group III nitride semiconductor device of the present invention includes, for example, cold regions such as polar regions such as the Arctic and Antarctic regions, in addition to the engine room of an automobile. The operating temperature when operating in a cold region such as a polar region is, for example, -60 ° C to 20 ° C, preferably -40 ° C to 20 ° C, more preferably -30 ° C to 20 ° C. Note that the channel layer portion of the n-type conductive layer region preferably has a depth of 10 nm or more from the heterojunction interface, more preferably, has a depth of 20 nm or more from the heterojunction interface, and more preferably, The ionized n-type impurity is included at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more over a depth of 30 nm or more from the heterojunction interface. In this case, the measurement temperature condition of the ionized n-type impurity concentration is 5 ° C. or more and 35 ° C. or less as described above, or the operating temperature condition of the group III nitride semiconductor device of the present invention. If the ionized n-type impurity has a concentration of 1 × 10 ¹⁹ cm ⁻³ or more in these depth ranges, the access resistance between the ohmic electrode and the two-dimensional electron gas (2DEG) is further increased. It can be effectively reduced. Further, if the ionized n-type impurity has a concentration of 1 × 10 ¹⁹ cm ⁻³ or more in the range of these depths, the concentration (volume density) of the ionized n-type impurity at the heterojunction interface. Becomes 1 × 10 ¹⁹ cm ⁻³ or more. Further, from the viewpoint of further reducing the access resistance and the like, the ionized donor impurity concentration (concentration of the ionized n-type impurity) under the temperature condition of 5 ° C. to 35 ° C. or the operating temperature condition of the HEMT of the present invention is It is particularly preferable that it is 1 × 10 ¹⁹ cm ⁻³ or more over the entire n-type conductive layer region (from the upper part of the channel layer to the upper surface of the barrier layer).

  In the group III nitride semiconductor device of the present invention, the recess from which a part of the upper part of the channel layer and the barrier layer thereabove are removed has a side surface and a bottom surface, and the side surface of the recess is the heterojunction. It is preferable to have an inclination angle within a range of 45 ° ± 15 ° with respect to the interface. As will be described later, it is preferable for the access angle between the ohmic electrode and the 2DEG to be reduced that the tilt angle is neither too large nor too small. The tilt angle is more preferably 35 to 55 degrees, and still more preferably 40 to 50 degrees. In addition, the said recessed part (recessed part) in FIG. 1 has a side surface and a bottom surface, and the said side surface has an inclination angle of less than 90 degree | times with respect to the said heterojunction interface. However, in the group III nitride semiconductor device of the present invention, the shape of the recess (recess portion) is not particularly limited. For example, as for the said recessed part (recessed part), as shown in FIG. Further, as shown in FIG. 3B, the concave portion (recess portion) may have a shape in which the inclination angle of the side surface exceeds 90 degrees and the side surface is overhanging. Further, for example, as shown in FIG. 3C, the concave portion (recess portion) may have a shape having a curved surface and a side surface and a bottom surface that are not clearly separated. 3A to 3C are drawings showing the shape of the recess (recess portion), the illustration of the heterojunction channel, the ohmic electrode, and the like is omitted for simplification.

The upper limit value of the ionized n-type impurity (ionized donor impurity) concentration in the n-type conductive layer region is not particularly limited, but is, for example, 10 ²² cm ⁻³ or less from the viewpoint of the solid solution limit of the impurity concentration. It is. That is, from the viewpoint of preventing deterioration of the crystal quality of the n-type conductive layer region, it is preferable that the n-type impurity (ionized donor impurity) concentration does not exceed the solid solution limit of the impurity concentration.

In the group III nitride semiconductor device of the present invention, in the channel layer portion of the n-type conductive layer region, the concentration of the n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ²⁰ cm ⁻³ or more. Preferably there is. According to this, it is easy to satisfy the condition that the concentration of the ionized n-type impurity (ionized donor impurity) in the n-type conductive layer region is 1 × 10 ¹⁹ cm ⁻³ or more.

In the n-type conductive layer region, the distribution of n-type impurity concentration is not particularly limited, but is a function of depth. The reference of the depth is not particularly limited, and may be expressed by, for example, the depth from the barrier layer surface. In the channel layer portion of the n-type conductive layer region, the n-type impurity concentration in the vicinity of the heterojunction interface with the barrier layer, that is, the volume density of the n-type impurity is, for example, the depth z from the heterojunction interface. Can be expressed as a function of volume density, i.e., z. In this case, the “n-type impurity concentration at the heterojunction interface with the barrier layer” is the n-type impurity concentration at z = 0. This value can be measured with a normal measuring instrument. The ionized n-type impurity concentration can also be measured with a normal measuring instrument. In the group III nitride semiconductor device of the present invention, the channel layer portion of the n-type conductive layer region preferably has a depth of 10 nm or more from the heterojunction interface, more preferably the heterojunction interface. The n-type impurity is contained at a concentration of 1 × 10 ²⁰ cm ⁻³ or more from the hetero junction interface to a depth of 20 nm or more, more preferably from the heterojunction interface to a depth of 30 nm or more. If the concentration of the n-type impurity is 1 × 10 ²⁰ cm ⁻³ or more within these depth ranges, the access resistance between the ohmic electrode and the two-dimensional electron gas (2DEG) is more effectively reduced. it can. In addition, if the concentration of n-type impurities is 1 × 10 ²⁰ cm ⁻³ or more in these depth ranges, the n-type impurity concentration (volume density) at the heterojunction interface is 1 × 10 ²⁰ cm ⁻³ or more. It becomes.

Furthermore, in the group III nitride semiconductor device of the present invention, from the viewpoint of further reducing the access resistance and the like, the n-type impurity concentration is set over the entire n-type conductive layer region (from the upper part of the channel layer to the upper surface of the barrier layer). ) 1 × 10 ²⁰ cm ⁻³ or more is preferable. In addition, it is preferable that the upper limit of the said n-type impurity (donor impurity) density | concentration in the said n-type conductive layer area | region is 10 < ²² > cm < ^-3 > or less from a viewpoint of the favorable crystalline quality.

In the group III nitride semiconductor device of the present invention, in the upper portion of the channel layer and the barrier layer, the portion other than the n-type conductive layer region is, for example, non-doped, but is not limited thereto. The portion other than the n-type conductive layer region may not contain any n-type impurities, or may contain some n-type impurities, for example. Further, for example, even if an n-type impurity is introduced (doping) into the barrier layer, a two-dimensional electron gas layer is formed at and near the heterojunction interface between the barrier layer and the channel layer. good. The n-type impurity concentration in the portion other than the n-type conductive layer region is not particularly limited in the barrier layer. Also in the channel layer, the n-type impurity concentration is not particularly limited, but is, for example, 1 × 10 ¹⁷ cm ⁻³ or less, preferably 1 × 10 ¹⁶ cm ⁻³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less. It is. Note that the concentration of the n-type impurity is not usually reduced stepwise at the boundary with the n-type conductive layer region in the channel layer upper portion and the barrier layer other than the n-type conductive layer region. , Gradually decrease. More specifically, for example, a portion other than the n-type conductive layer region has a transition region at the boundary with the n-type conductive layer region, and the n-type impurity concentration gradually decreases in the transition region. To do. It should be noted that the width of the transition region in the layer plane direction of the channel layer usually changes substantially in proportion to the range of implanted ions in ion implantation, and is, for example, about half the range of the range.

In the group III nitride semiconductor device of the present invention, the material for forming the ohmic electrode is not particularly limited, and may be the same as, for example, a general group III nitride semiconductor device. The ohmic electrode includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al) or gold (Au), oxides thereof, And at least one selected from the group consisting of nitrides thereof. The n-type impurity is not particularly limited, but is preferably at least one of ²⁸ Si and ²⁹ Si.

  In the group III nitride semiconductor device of the present invention, the channel layer is preferably made of gallium nitride (GaN) or indium gallium nitride (InGaN). The barrier layer is preferably made of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium aluminum nitride (InAlN). The combination of the channel layer and the barrier layer is not particularly limited. For example, a combination in which the band gap of the barrier layer is larger than that of the channel layer may be appropriately selected with reference to a general HEMT or the like. When there are a plurality of the barrier layers, the plurality of barrier layers may be formed of different materials. For example, it is preferable that the plurality of barrier layers are stacked above the channel layer, and the barrier layer closest to the channel layer has a higher Al composition ratio than the other barrier layers. It is particularly preferable that the barrier layer closest to the channel layer is made of AlN. Alternatively, as described above, the barrier layer may be doped with n-type impurities.

  The use of the group III nitride semiconductor device of the present invention is not particularly limited, but can be preferably used as, for example, a heterojunction field effect transistor (HEMT). In such a HEMT of the present invention, for example, as shown in FIG. 1 (a) or (b), a plurality of the recesses and the ohmic electrodes are formed, and the ohmic electrodes include one or more source electrodes and one or more source electrodes. It is preferable that a gate electrode is further included, and the gate electrode is formed on the barrier layer.

  Although the manufacturing method of the group III nitride semiconductor device of the present invention is not particularly limited, it is preferably manufactured by the manufacturing method of the present invention. The group III nitride semiconductor device produced by the production method of the present invention is not particularly limited, but is preferably the group III nitride semiconductor device of the present invention. Hereinafter, the method for manufacturing a group III nitride semiconductor device of the present invention will be specifically described with reference to the HEMT of FIG.

  First, a channel layer 901 is formed from a group III nitride semiconductor on a substrate (not shown) (channel layer forming step). Next, a barrier layer 909 is formed on the channel layer 901 with AlN or the like. Further, another barrier layer 902 is formed on the upper surface of the barrier layer 909 (above the channel layer 901) by heterojunction with a group III nitride semiconductor (barrier layer forming step). In FIG. 1A, the barrier layer has two layers 909 and 902. However, in the group III nitride semiconductor device of the present invention, the barrier layer may be only one layer or three or more layers. . As the substrate, for example, a silicon substrate, a sapphire substrate, a silicon carbide substrate, or the like can be used. The channel layer 901, the barrier layer 909, and the barrier layer 902 can be formed by, for example, epitaxial growth. Examples of the epitaxial growth method include a metal-organic vapor phase epitaxy (MOVPE) method, a molecular beam epitaxy (MBE) method, and the like. Note that the metal organic chemical vapor deposition method is sometimes referred to as a MOCVD (Metal Organic Chemical Vapor Deposition) method. In the channel layer forming step, the channel layer is preferably formed from gallium nitride (GaN) or indium gallium nitride (InGaN). In the barrier layer forming step, the barrier layer is preferably formed of aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or indium aluminum nitride (InAlN). The combination of the channel layer and the barrier layer is not particularly limited. For example, a combination in which the band gap of the barrier layer is larger than that of the channel layer may be appropriately selected with reference to a general HEMT or the like. Alternatively, as described above, the barrier layer may be doped with n-type impurities. Further, for example, after a buffer layer (not shown) is epitaxially grown on the substrate, the channel layer 901 and the barrier layer 902 may be continuously epitaxially grown. Examples of the buffer layer interposed between the substrate and the channel layer 901 include group III nitride compound semiconductors such as AlN, GaN, and AlGaN. Further, for example, a group III nitride semiconductor substrate such as GaN or AlN may be used instead of the silicon substrate, sapphire substrate, silicon carbide substrate, or the like, and the buffer layer may be omitted.

Next, a recess is formed by removing a part of the upper portion of the channel layer 901 (in FIG. 1A, both left and right end portions of the upper portion of the channel layer) and the barrier layers 909 and 902 thereabove (recess forming step). . This recess forming step can be performed by, for example, wet etching, dry etching, or the like. The dry etching is performed by using, for example, a plasma-like gas such as SF ₆ (sulfur hexafluoride), CF ₄ (tetrafluoromethane), CHF ₃ (methane trifluoride), C ₂ F ₆ (ethane hexafluoride). Can be used. As described above, the depth of the recess (mesa 101) is not particularly limited except that it is deeper than the heterojunction channel (two-dimensional electron gas layer) 903, but it is usually sufficient if it is 450 mm or more. Moreover, in the said recessed part formation process, the said recessed part is formed so that the said recessed part may have a side surface and a bottom face, for example. In this case, the side surface of the recess is preferably inclined with respect to the heterojunction interface within a range of 45 ° ± 15 °, more preferably within a range of 35 to 55 °, and even more preferably within a range of 40 to 50 °. The recess is formed to have When the inclination angle is within the above range, when an n-type conductive layer is formed by ion implantation described later, a conductive layer is easily formed immediately behind the side wall (the inclined surface), and ohmic metal is deposited. In this case, the metal tends to be firmly in contact with the side wall. In the ohmic structure of the group III nitride semiconductor device of the present invention, for example, as shown in FIG. 1A, an energization path 908 (908 ′) is formed through the side surface of the mesa (the inclined surface). it is conceivable that. In order to reduce the tilt angle, for example, dry etching can be performed by using a nitride film SiN as an etching mask material and using only BCl _{3 as} an etching gas. In this case, the etching of SiN is isotropic, and since the etching rate is relatively close to that of a group III nitride semiconductor such as GaN, an etching shape having the inclined surface can be formed. For example, as shown in FIGS. 1A to 1C, when the inclined surfaces are formed at both ends of the element, the etching shape becomes tapered (tapered shape).

  Next, in the region including the surface (for example, the side surface and the bottom surface) of the recess, the potential difference is such that n-type impurity ions reach a depth of 15 nm or more from each part of the surface of the region in a measured value in a direction perpendicular to the surface. The n-type conductive layer region is formed by accelerating by doping and activated by annealing (n-type conductive layer region forming step). As described above, the depth is preferably 20 nm or more, and more preferably 45 nm or more. The upper limit value of the depth is not particularly limited, but is, for example, 300 nm or less. In the n-type conductive layer region, the width of the heterojunction interface is 50 nm or more in a direction perpendicular to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect. It is preferable to perform a layer formation process. In the n-type conductive layer region, the width of the heterojunction interface is preferably 100 nm or more in the direction perpendicular to the line where the surface of the n-type conductive layer region and the heterojunction interface intersect as described above. . In the n-type conductive layer region, the upper limit value of the width of the heterojunction interface is not particularly limited, but from the viewpoint of reducing access resistance, for example, the surface of the n-type conductive layer region and the heterojunction interface intersect. It is 3 μm or less in the direction perpendicular to the line. The acceleration energy for doping the n-type impurity ions until reaching the predetermined depth is not particularly limited, and may be set as appropriate. The acceleration energy is, for example, 20 keV or more, preferably 25 keV or more, more preferably 30 keV or more. The upper limit value of the acceleration energy is not particularly limited, but is, for example, 200 keV or less.

In the n-type conductive layer region forming step, the sample surface, that is, the n-type conductive layer region is relatively heavy (high concentration so that the ionized donor impurity concentration _Nde1 is 1 × 19 cm ⁻³ or more). It is preferable to select ion implantation conditions. Thereby, for example, the connection resistance between the n-type conductive layer region (n ⁺ layer) and the 2DEG adjacent thereto can be reduced. In the n-type conductive layer forming step, it is preferable that n-type impurity ions are doped so as to have a concentration of 1 × 10 ²⁰ cm ⁻³ or more at the heterojunction interface with the barrier layer above the channel layer. More specifically, for example, in the n-type conductive layer region forming step, the n-type impurity ions are implanted into at least part of the source electrode formation planned region and the drain electrode formation planned region at 5 × 10 ¹⁵ cm ^−2. It is preferable to dope with the above effective dose. When the effective dose is 5 × 10 ¹⁵ cm ⁻² or more, the n-type impurity ions are likely to have a concentration of 1 × 10 ²⁰ cm ⁻³ or more in the upper portion of the channel layer and the barrier layer. From the viewpoint of improving the crystal quality, as described above, the upper limit of the implanted donor impurity concentration is preferably 10 ²² cm ⁻³ . In the n-type conductive layer region forming step, the n-type impurity is not particularly limited, but it is preferable to dope at least one of ²⁸ Si and ²⁹ Si as the n-type impurity. In the n-type conductive layer region 904, the optimum implantation concentration of n-type impurities at the upper surface of the channel layer 901, that is, the heterojunction interface (or the heterojunction channel 903) is, for example, 1 × 21 cm ^−3. It is not limited. Suitable ion implantation conditions for realizing the optimum implantation concentration or a concentration close thereto are, for example, an acceleration energy of 100 keV and a dose amount of 1 × 10 ¹⁶ cm ⁻² , but are not limited thereto.

  The annealing treatment can be performed by, for example, RTA (Rapid Thermal Annealing) in a nitrogen atmosphere. The annealing treatment is preferably performed at a temperature of 1,100 ° C. or more and 1,300 ° C. or less in order to obtain a high concentration of ionized donor impurity concentration (ionized n-type impurity concentration). The annealing temperature is more preferably 1,100 ° C. or more and less than 1,300 ° C., more preferably 1,125 ° C. or more and 1,250 ° C. or less, further preferably 1,150 ° C. or more and 1,250 ° C. or less, particularly preferably. Is 1,150 ° C. or more and 1,225 ° C. or less. More specifically, in order to increase the activation rate of the ion-implanted n-type impurity, the lower limit value of the annealing temperature is preferably 1,100 ° C. or higher, more preferably 1,125 ° C. or higher. More preferably, it is 1,150 ° C. or higher. In addition, from the viewpoint of suppressing nitrogen desorption from the surface of the group III nitride semiconductor layer and thereby suppressing alteration of the surface of the group III nitride semiconductor layer, the upper limit of the annealing temperature is preferably 1, It is 300 ° C. or lower, more preferably less than 1,300 ° C., further preferably 1,250 ° C. or lower, particularly preferably 1,225 ° C. or lower. The annealing time is not particularly limited, but is set to, for example, about 30 seconds to 5 minutes depending on the performance of the heat treatment apparatus used for heating.

  For example, when a substrate that is easily plastically deformed at a high temperature, such as a silicon (Si) substrate, is used, the activation annealing of the n-type impurity is performed at a temperature lower than the activation annealing temperature, for example, 1,000 ° C. May be. By performing the annealing process at a relatively low temperature, it is possible to reduce the warpage of the wafer, the generation of defects in the epitaxial film, and the leakage current (to ensure the device operation breakdown voltage). However, when annealing is performed at a relatively low temperature, a relatively long annealing process is required. For example, when annealing at 1,000 ° C., the annealing time is preferably 20 minutes or longer.

In the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ¹⁹ cm ⁻ under a temperature condition of 5 ° C. or more and 35 ° C. or less. It is preferable to perform the annealing treatment in the n-type conductive layer region forming step so as to be ³ or more. Alternatively, in the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × under the operating temperature condition of the group III nitride semiconductor device. The annealing treatment in the n-type conductive layer region forming step is preferably performed so as to be 10 ¹⁹ cm ⁻³ or more. Thereby, for example, a low connection resistance can be obtained at the connection portion between the n-type conductive layer region 904 shown in FIG. 1 and the channel region (2DEG layer) 903 below the gate electrode 905. More preferably, the channel layer portion of the n-type conductive layer region has a depth of 10 nm or more from the heterojunction interface, more preferably, a depth of 20 nm or more from the heterojunction interface, and more preferably, The annealing treatment is performed so as to include the ionized n-type impurity at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more over a depth of 30 nm or more from the heterojunction interface. In this case, the measurement temperature condition of the ionized n-type impurity concentration is 5 ° C. or more and 35 ° C. or less as described above, or the operating temperature condition of the group III nitride semiconductor device of the present invention. When the ionized n-type impurity has a concentration of 1 × 10 ¹⁹ cm ⁻³ or more in these depth ranges, the connection resistance and the like at the connection portion can be further effectively reduced. Further, if the ionized n-type impurity has a concentration of 1 × 10 ¹⁹ cm ⁻³ or more in the range of these depths, the concentration (volume density) of the ionized n-type impurity at the heterojunction interface. Becomes 1 × 10 ¹⁹ cm ⁻³ or more. From the viewpoint of further reducing the access resistance and the like, the ionized donor impurity concentration (the concentration of the ionized n-type impurity) under the temperature condition of 5 ° C. or more and 35 ° C. or less or the operating temperature condition of the group III nitride semiconductor device. ) Is particularly preferably performed so that the entire n-type conductive layer region (from the upper part of the channel layer to the upper surface of the barrier layer) becomes 1 × 10 ¹⁹ cm ⁻³ or more.

  Furthermore, ohmic electrodes (source electrode 906 and drain electrode 907) that are in ohmic contact with the n-type conductive layer region through the side and bottom surfaces of the recess are formed (ohmic electrode forming step). The material for forming the ohmic electrode is not particularly limited, but tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al) or gold (Au And at least one selected from the group consisting of oxides thereof and nitrides thereof. For example, the ohmic electrode may be formed of a laminate of the metals such as a Ti / Al / Nb / Au structure or a Ti / Mo / Au structure. Although ohmic alloy conditions can provide relatively good ohmic contact characteristics even when non-alloyed, ohmic alloy can provide an ohmic electrode that is further reduced in resistance and highly reliable in terms of thermal stability. The ohmic alloy may be performed under a low temperature condition of less than 550 ° C., for example.

  Further, a metal material is formed on the barrier layer 902, and further subjected to an alloy process, thereby forming a gate electrode 905 having a T-shaped cross-sectional shape (gate electrode forming step). The gate electrode 905 is not particularly limited, but is formed from, for example, a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, or a laminate of two or more of these metal layers. be able to. In this way, the HEMT (Group III nitride semiconductor device) shown in FIG. 1A can be manufactured. The order of the gate electrode forming step, the n-type conductive layer forming step, and the ohmic electrode forming step may be reversed. Further, for example, the gate electrode forming step may be performed between the doping of the n-type impurity and the annealing treatment. For example, the gate electrode may be formed on the channel layer via an insulating film. Further, the group III nitride semiconductor device of the present invention does not have to have a gate electrode as shown in FIG. 1C, for example, and in this case, the gate electrode forming step may not be performed. Furthermore, as described above, the group III nitride semiconductor device of the present invention may have only one barrier layer as shown in FIG. 1 (b) or (c), for example. These can be manufactured, for example, in the same manner as the group III nitride semiconductor device of FIG. 1A except that only one barrier layer is formed in the barrier layer forming step.

In the manufacturing method of the present invention, for example, the n-type impurity ion doping in the n-type conductive layer region forming step includes an n-type impurity ion doping first step and an n-type impurity ion doping second step. Two-stage doping may be included. The doping region in the second step of n-type impurity ion doping may protrude from the end including the end of the doping region in the first step of n-type impurity ion doping. The terminal may be a gate electrode side terminal in the case of HEMT. Further, the acceleration energy E ₁ of the n-type impurity ion doping in the n-type impurity ion doping first step, the relationship between the acceleration energy E ₂ of the n-type impurity ion doping in the n-type impurity ion doping second step For example, E ₁ > E ₂ . Acceleration energy E ₁ is, for example, may be a relatively high energy of several hundred keV. The order of the first-stage ion implantation (the n-type impurity ion doping first process) and the second-stage ion implantation (the n-type impurity ion doping second process) depends on the circumstances of device fabrication (HEMT manufacturing), etc. It may be replaced depending on

  Further, for example, the manufacturing method of the present invention further includes a dry surface treatment step of performing a dry surface treatment by exposing the upper surface of the n-type conductive layer region to a plasma-like gas after the n-type conductive layer region forming step. Also good. The dry surface treatment step is preferably performed prior to the ohmic electrode formation step. Further, in the dry surface treatment step, the region for performing the dry surface treatment includes the entire upper surface of the n-type conductive layer region, and in the ohmic electrode formation step, the ohmic contact is performed so as to cover the entire upper surface of the n-type conductive layer region. It is preferable to form an electrode.

For example, the barrier layer may be damaged when n-type impurity ion implantation is performed to form the n-type conductive layer region. In contrast, by performing a dry surface treatment on the upper surface of the n-type conductive layer region, damage to the barrier layer can be reduced, a good crystal structure can be obtained, and contact resistance can be further reduced. In the present invention, “dry surface treatment” refers to treatment without bringing a liquid into contact with the surface, and examples thereof include dry etching and exposure to plasma. The plasma-like gas is not particularly limited, and may be a gas generally used in dry etching, for example. Specifically, the plasma-like gas is, for example, SF ₆ (sulfur hexafluoride), CF ₄ (tetrafluoromethane), CHF ₃ (methane trifluoride), C ₂ F ₆ (hexafluoroethane). ) And the like.

  Hereinafter, the principle that the access resistance and the on-resistance can be reduced in the group III nitride semiconductor device of the present invention will be described in comparison with the group III nitride semiconductor device related to the present invention. However, the following description is an example of a mechanism that can be estimated, and does not limit the present invention.

  As a result of independent research, the present inventors have found the following regarding the field effect transistor (FET) having the structure of FIGS.

In a group III nitride semiconductor HEMT such as an AlGaN / GaN heterojunction field effect transistor (HEMT) in Ga plane growth, as shown in FIG. 4, for example, ohmic electrodes (906 and 907) have a planar structure without digging a recess. Form. In this case, for example, an ohmic metal (Ti / Al / Mo / Au, etc.) is deposited on a semiconductor substrate by means such as vapor deposition, and then ohmic alloy at a temperature around 850 ° C. is performed. By this method, a relatively good practical level of contact resistance _Rc can be obtained. The contact resistance _{R c} value in this case is typically in the range of such 0.3～0.5Omumm. However, for the purpose of improving the mobility of the heterojunction 2DEG carrier, for example, as shown in FIG. 5, in the epi, a thin barrier layer such as AlN is further provided between the barrier layer 902 (AlGaN) and the channel layer 901 (GaN). 909 may be arranged. For the same purpose, the Al composition ratio of AlGaN of the barrier layer 902 may be increased instead of providing the barrier layer 909 such as AlN. This is because as the Al composition ratio of the barrier layer adjacent to the channel layer increases, heterojunction channel (2DEG layer) carriers tend to be formed (concentration increases) in the channel layer. In these cases, due to the barrier layer 909 such as AlN or the barrier layer 902 having a large Al composition ratio, the access resistance from the ohmic electrode to the heterojunction channel (2DEG layer) 903 increases, and the on-resistance also increases. This is because as the Al composition ratio of the barrier layer increases, the electric resistance value in the direction perpendicular to the layer plane of the barrier layer tends to increase.

According to the HEMT having the structure as shown in FIG. 6, even when the barrier layer 909 such as AlN is present as described above, it is said that a good ohmic contact resistance can be obtained (Patent Document 2). According to the HEMT structure of FIG. 6, first, contacts with ohmic electrodes (source electrode 906 and drain electrode 907) are formed between n ⁺ semiconductor (n-type impurity implantation region 904). Thus, the effect of reducing the ohmic contact resistance value can be expected. Second, when the trench (mesa) 101 is dug deeper than the semiconductor heterointerface (upper surface of the 2DEG layer 903), as shown in the energization path 908 (908 ') of FIG. The energization path 908 (908 ′) at the time of access can be formed without using the barrier layer 909. These mechanisms can be expected to reduce the access resistance of the device (HEMT).

  However, as a result of the inventors verifying the HEMT of Patent Document 2 through experiments, the reduction in access resistance is not always sufficient. Specifically, the measured value of the access resistance was at least 0.8 Ωmm or more, usually 1 Ωmm or more, as a contact component for ohmic contact. This cause is presumed as follows. That is, in the manufacture of the HEMT of FIG. 6, the mesa 101 is formed deeper than the heterojunction channel (2DEG layer) 903 by etching or the like, and ohmic electrodes (906 and 907) are formed there. In this case, the mesa side surface portion of the heterojunction channel 903 is damaged by etching, so that the interface lattice is disturbed, 2DEG carriers are decreased, and the resistance of the portion 910 is increased. In order to reduce the access resistance of the HEMT having the device structure of FIG. 6, a path that bypasses the portion damaged by the mesa formation must be formed as the energization path 908 (908 ′). Although the distance (width) of the damaged portion in the heterojunction portion 903 is not necessarily clear, it is considered that the distance (width) is probably 10 nm or more and has reached about 50 nm or more.

According to the manufacturing method described in Patent Document 2, when forming the n-type impurity implantation region (n ⁺ layer) 904 in the device structure of FIG. 6, the n-type impurity is implanted by a thermal diffusion method. However, as described in Patent Document 2, the thickness T _dif of the n ⁺ layer 904 formed by diffusion is at most 10 nm. Accordingly, 2DEG 910 damaged by etching, and got over the entire range of the thickness _{T dif} of ^{the n +} layer 904, ^{the n +} layer 904 inside, the low access resistance between the ohmic electrode and the 2DEG can not be realized Conceivable. If the n ⁺ layer 904 is as shallow as 10 nm, the contact resistance cannot be reduced sufficiently.

On the other hand, in the group III nitride semiconductor device of the present invention, as described above, the depth of the n-type conductive layer region is 15 nm as measured from each part of the surface of the n-type conductive layer region in a direction perpendicular to the surface. That's it. In addition, the said depth is shown by _Timp in sectional drawing of Fig.1 (a)-(c). Thereby, for example, as indicated by the energization paths 908 and 908 ′ in the arrows of FIGS. 1A to 1C, the damaged 2DEG portion 910 is bypassed, and the normal heterojunction portion at the back of the semiconductor sample is The n-type conductive layer region 904 can be connected well. In order to form an n-type conductive layer region having a sufficient depth as described above, for example, as described in the manufacturing method of the present invention, an “ion implantation method (ion implantation using an accelerator)” is used. Is preferred. As described above, the n-type conductive layer region having a sufficient depth cannot be formed by the thermal diffusion method. Therefore, if the depth of the n-type conductive layer region is 15 nm or more from each part of the surface of the n-type conductive layer region in a measured value in the direction perpendicular to the surface, the n-type conductive layer region is (Ion implantation using an accelerator) ”.

According to the results of experiments by the present inventors, the following has been found. That is, in the HEMT manufacturing of FIG. 1A, a mesa deeper than the heterojunction channel is formed in the region where the ohmic electrode is formed, and the channel layer (GaN) is exposed on the mesa bottom surface (recess formation step). Next, ²⁸ Si impurity is heavily doped by ion implantation (acceleration energy: 100 keV, dose amount: 1E16 / cm ² ), and activation annealing (1200 ° C. × 5 minutes) is performed to thereby form an n ⁺ conductive layer (n-type conductive layer). Layer region) was formed (n-type conductive layer region forming step). Further, an ohmic electrode was formed by depositing a metal (ohmic electrode forming step). When evaluating the contact resistance _{R c} of the ohmic electrode in this structure, for example, even as low as _{R c} ≒ _0.03Ωmm in non-alloy, if Hodokose appropriate alloy _was found to be a R c <0.03Ωmm. However, these numerical values are all examples and do not limit the present invention. In addition, about these manufacturing processes and HEMT performance evaluation, it mentions more concretely in the below-mentioned Example.

Hereinafter, a preferred configuration for further effectively reducing the contact resistance component in the group III nitride semiconductor device of the present invention will be described with reference to FIG. However, as described above, the resistance reduction mechanism (mechanism) is an exemplification, and does not limit the present invention. First, FIG. 2 is an enlarged cross-sectional view showing a part of a contact portion between the ohmic electrode 906 or 907 and the channel layer 901, the barrier layer 909, and the barrier layer 902 in the cross-sectional view of FIG. In FIG. 2, the parts denoted by the same reference numerals as those in FIG. 1A are the same as those in FIG. Further, the HEMT end portion (left side in FIG. 2, right side or left side in FIG. 1) where the n-type conductive layer region 904 is formed is a contact portion 911, and a portion other than the contact portion 911 is an interelectrode portion 912. . According to FIG. 2, first, an energization path from the ohmic electrode (the part in contact with the barrier layer 902 and the barrier layer 909) in the upper part of the 2DEG that has entered the mesa stage to the 2DEG layer 903 can be considered. However, in parallel with this energization path, the channel layer of the n-type conductive layer region (n ⁺ region) 904 is connected to the mesa side surface below 2DEG and the ohmic electrode on the mesa bottom surface (the portion in contact with the channel layer 901). It is considered that there is an energization path to the 2DEG layer via 901. Since the latter energization path has a relatively low resistance, it is considered that the contact resistance is reduced by the following formula (1) as the total contact resistance component R _c (total). According to the latter energization path, the distance from the ohmic electrode to the heterojunction channel (2DEG layer) is relatively short. Further, according to this energization path, the heterojunction channel (2DEG layer) can be accessed from the ohmic electrode without passing through the barrier layer. For example, the group III nitride semiconductor device of FIGS. 4 and 5 does not have such an energization path.

Furthermore, as described with reference to FIG. 6, when the mesa is formed deeper than the heterojunction 2DEG by etching or the like and the ohmic electrode is formed there, the mesa side surface portion 910 of the heterojunction has a 2DEG due to damage due to etching. The carrier is decreased and the resistance of the portion is increased. According to actual measurement, the value is, for example, 0.8 Ωmm or more, usually 1 Ωmm or more, as a contact component of ohmic contact. On the other hand, in the electrode structure in the group III nitride semiconductor device of the present invention, as shown in FIG. 1, a relatively low resistance n-type conductive layer around the 2DEG portion 910 damaged by ion implantation is used. A region (n ⁺ layer) 904 is formed. Thus, the energization path 908 (908 ′) is formed so as to bypass the portion where the resistance has increased due to damage. From this viewpoint, in the n-type conductive layer region of the group III nitride semiconductor device of the present invention, as described above, the width of the heterojunction interface (W in FIG. 1) is the surface of the n-type conductive layer region and the surface of the n-type conductive layer region. It is preferably 50 nm or more in the direction perpendicular to the line where the heterojunction interface intersects. In the n-type conductive layer region, the width of the heterojunction interface is preferably 100 nm or more in a direction perpendicular to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect. In the n-type conductive layer region, the upper limit value of the width of the heterojunction interface is not particularly limited, but from the viewpoint of reducing access resistance, for example, the surface of the n-type conductive layer region and the heterojunction interface intersect. It is 3 μm or less in the direction perpendicular to the line. Note that, in the heterojunction channel (2DEG layer) 903, the width of the 2DEG portion 910 damaged by etching differs depending on the manufacturing conditions of the element and is not constant and is not necessarily clear. As described above, it is considered that the width of the 2DEG part (heterojunction interface) 910 may reach 10 nm or more, or 50 nm or more. In the group III nitride semiconductor device of the present invention, the width of the heterojunction interface in the n-type conductive layer region is preferably larger than the width of the damaged 2DEG part (heterojunction interface).

In the element of FIG. 1, the contact resistance component of the energization path from the n ⁺ region (the channel layer 901 portion of the n-type conductive layer region 904) on the mesa side surface or the mesa bottom surface of the ohmic electrode 906 or 907 to the 2DEG is These can be divided into the following (1) to (3).

(1) Contact resistance Rc ′ between the ohmic electrode and the n ⁺ region (n-type conductive layer region 904)
(2) Sheet resistance Rsh · ΔL from the tip of the ohmic electrode to the n ⁺ -2DEG boundary (boundary between the n-type conductive layer region 904 and the 2DEG layer 903 formed in a portion other than 904) (distance ΔL)
(3) Connection resistance R _{b at the} n ⁺ -2DEG boundary

Among the resistors (1) to (3), in order to reduce R _{b of} (3), as described above, in the channel layer 901 portion of the n-type conductive layer region 904, a heterojunction with the barrier layer 902 The concentration of ionized n-type impurities at the interface is preferably 1 × 10 ¹⁹ cm ⁻³ or more. R _c ′ of (1) is almost zero. R _sh · ΔL can be reduced by shortening the margin portion ΔL at the electrode end by improving the manufacturing process. For example, ΔL is preferably 0.5 μm or less, and ΔL is particularly preferably 0. That is, in the group III nitride semiconductor device of the present invention, it is particularly preferable that the ohmic electrode is formed so as to cover the entire upper surface of the n-type conductive layer region. As described above, for example, in the case of the ohmic non-alloy in the HEMT structure shown in FIGS. 4 to 6, the contact resistance is significantly larger than 1 Ωmm. In the present invention, the contact resistance is about 0. It is also possible to obtain a significant reduction in resistance value such as 03 Ωmm. However, as described above, these numerical values are examples and do not limit the present invention.

In the channel layer 901 portion of the n-type conductive layer region 904, when the concentration of ionized n-type impurities at the heterojunction interface with the barrier layer 902 is 1 × 10 ¹⁹ cm ⁻³ or more, the connection resistance Rb is reduced. The reason for this is not always clear. As the reason, for example, the distance between the donor (n-type impurity) atoms is shortened, so that the electron distribution is degenerated and the conduction by the field emission tunneling mechanism becomes dominant.

  A HEMT having a structure shown in FIG. 1B (Example 1) and a HEMT having a structure shown in FIG. 4 (Comparative Example 1) were manufactured.

First, epitaxial growth is carried out by MOCVD on a 3-inch SiC substrate to form Al _0.15 Ga _0.85 N (45 nm) / GaN heterojunction epi, and the GaN channel layer and the AlGaN barrier layer are in the above order on the substrate. The wafers laminated in (1) were fabricated (channel layer forming step and barrier layer forming step). Two of the same wafers were produced, the group III nitride semiconductor device of Example 1 was manufactured using the first wafer, and the group III nitride semiconductor device of Comparative Example 1 was manufactured using the second wafer. Manufactured. “3 inches” represents the width of the SiC substrate, and 1 inch is equal to about 2.54 cm.

Next, after patterning a sample with a resist on the first wafer, dry etching was performed to form a mesa 101 in the ohmic electrode formation portion (recess formation step). An ICP dry etching apparatus was used as the dry etching apparatus. Further, a nitride film SiN was used as an etching mask material, and only BCl ₃ was used as an etching gas. In this case, the etching of SiN is isotropic, and since the etching rate is relatively close to that of the GaN-based material, an etching shape having an inclined surface can be formed. In this embodiment, as shown in FIG. 1B, the mesa 101 is formed at both ends of the element, so that the etching shape is tapered (tapered shape). The mesa 101 having a step of 700 mm (70 nm) was formed in an etching time of 450 seconds. The taper angle (inclination angle) on the inclined surface of the mesa 101 was 57 degrees with respect to the upper surface (heterojunction interface) of the channel layer 901. There was no etching residue on the taper side surface, and a relatively clean taper side surface was obtained. Thereafter, the resist was removed. On the other hand, mesa formation (recessed portion forming step) was not performed on the second wafer. In the subsequent steps, the same processing was performed on the first wafer and the second wafer.

Next, a silicon nitride film (SiN) as an ion implantation through film is deposited by CVD on the upper surface (upper side in FIG. 1B or FIG. 4) of each of the first and second wafers by CVD. did. After patterning this through-SiN film with a resist, ion implantation of ²⁸ Si was performed at an acceleration energy of 100 keV and a dose of 1 × 10 ¹⁶ cm ⁻³ (effective dose of 9.2 × 10 ¹⁵ cm ⁻³ ). Thereafter, the resist was removed with an organic solvent, and the through SiN film was removed with hydrofluoric acid.

  Further, after depositing a 200 nm nitride film as an activation annealing protection film on the entire wafer surface (front surface, back surface, and side surface), impurity activation annealing was performed at 1200 ° C. for 5 minutes. Thereafter, the annealing protective film was removed with hydrofluoric acid.

  Further, the wafer after the annealing protective film was removed was patterned with a resist, and then metal (Ti / Mo / Au) was vapor-deposited on the entire surface of the wafer and subjected to a lift-off process. Thus, in the first wafer, as shown in FIG. 1B, the source electrode 906 and the drain electrode 907 were formed so as to cover the area of the mesa 101. In the second wafer, as shown in FIG. 4, the source electrode 906 and the drain electrode 907 were formed on both ends of the upper surface. Furthermore, ohmic alloy was performed on each wafer at 500 ° C. for 5 minutes. The wafer after the formation of the ohmic electrodes (source electrode 906 and drain electrode 907) was patterned with a resist, and then Ni / Au was deposited and lifted off to form a gate electrode 905. Thus, the HEMTs of Example 1 and Comparative Example 1 were manufactured.

Resistance measurement was performed using a TLM (Transmission Line Model) pattern. In the HEMT of Example 1, ΔL (margin from the ohmic electrode end to the n-type conductive layer region 904 end) in FIG. 2 was 0.5 μm, and the HEMT of Comparative Example 1 was the same. As a result, in the HEMT of Example 1, the contact resistance component R _c (total) showed a low practical level value of 0.23 Ωmm. In contrast, in the HEMT of Comparative Example 1, the contact resistance component R _c (total) was as large as 0.50 Ωmm. Further, in the HEMT of Example 1, from the analysis of the resistance component by TLM evaluation, as the resistance component shown in FIG. 2, 2DEG-n ⁺ connection resistance R _b = 0.15 Ωmm, n ⁺ layer sheet resistance R _sh = 100 Ω / □ Contact resistance R _c = 0.3 Ωmm, R _c ′ = 0.03 Ωmm were obtained. From the above evaluation results, it was confirmed that according to the present invention, a group III nitride semiconductor device having low access resistance and on-resistance can be provided.

  In the present embodiment, the case where the present invention is applied to a field effect transistor has been shown. However, the present invention can be widely used to make an ohmic contact low resistance. That is, the group III nitride semiconductor device of the present invention is not limited to a field effect transistor, and may be any semiconductor device such as an epi-resistance wiring or a diode.

  The embodiments and preferred examples of the present invention have been described above with reference to the drawings.

  As described above, according to the present invention, it is possible to provide a group III nitride semiconductor device having a low access resistance and low on-resistance, a method for manufacturing a group III nitride semiconductor device, and an electronic device.

  Each of the above embodiments and examples is illustrative of the present invention. The present invention is not limited to the above embodiments and examples, and various configurations other than these can be employed. For example, all the HEMT structures of the above embodiments are single heterostructures having a single heterojunction interface, but the group III nitride semiconductor device of the present invention is not limited to this. For example, the group III nitride semiconductor device of the present invention may have a double heterostructure having two heterojunction interfaces. Examples of the double heterostructure include an AlGaN / GaN / AlGaN / GaN structure.

  In each of the above embodiments, the two-dimensional electron gas layer is formed at and near the heterojunction interface, but the heterojunction is formed so that a one-dimensional electron gas layer is formed instead of the two-dimensional electron gas layer. A structure may be configured.

  In each of the embodiments described above, in order to obtain a high concentration of ionized donor impurity, silicon (atomic weight: 28) is introduced (doped) as an n-type impurity as a particularly suitable example. The n-type impurity (donor impurity) is not limited to this. For example, silicon (atomic weight: 29) may be introduced instead of silicon (atomic weight: 28). Alternatively, oxygen, sulfur, selenium, and tellurium may be introduced as n-type impurities to obtain the high concentration of ionized donor impurities.

  In each of the embodiments described above, the source electrode and the drain electrode are in ohmic contact with the upper surface of the barrier layer. However, the source electrode and the drain electrode may be disposed on the barrier layer via another semiconductor layer or the like. Moreover, although the form which has arrange | positioned the gate electrode directly on the barrier layer upper surface was shown, you may arrange | position through a gate insulating film etc. on a barrier layer, for example. Furthermore, as described above, the group III nitride semiconductor device of the present invention is not limited to HEMT, and may be any semiconductor device such as an epi-resistance wiring or a diode. Therefore, the group III nitride semiconductor device of the present invention may not have a gate electrode.

  The use of the group III nitride semiconductor device of the present invention is not particularly limited, and can be widely used for various purposes such as power control and communication. As described above, the electronic device of the present invention is characterized by including the heterojunction field effect transistor of the present invention. Applications of the electronic device of the present invention are not particularly limited. For example, a power control device, a motor control device (for example, for an electric vehicle, for an air conditioner), a power supply device (for example, for a computer), inverter lighting, a high-frequency power generation device ( (For example, for microwave ovens, electromagnetic cookers, etc.), image display devices, information recording / reproducing devices, communication devices, arithmetic devices (for example, the group III nitride semiconductor element of the present invention is included as arithmetic devices), etc. .

101 Mesa 901 Channel layer (GaN, etc.), or GaN layer 902 Barrier layer (AlGaN, etc.), or AlGaN layer 903 Heterojunction channel (two-dimensional electron gas layer)
904 n + conductive layer 905 gate electrode 906 source electrode 907 drain electrode 908, 908 ′ conduction path 909 barrier layer (AlN, etc.)
910 2DEG part damaged during mesa formation 911 Contact part 912 Inter-electrode part

Claims (26)

Including a channel layer, a barrier layer, and an ohmic electrode;
The channel layer and the barrier layer are formed of a group III nitride semiconductor,
The barrier layer is heterojunction above the channel layer;
The upper part of the channel layer and the barrier layer thereabove are removed to form a recess,
An n-type conductive layer region is formed in part of the channel layer and the barrier layer;
The n-type conductive layer region includes the surface of the recess,
A depth of the n-type conductive layer region is 15 nm or more in a measured value in a direction perpendicular to the surface from each part of the surface of the n-type conductive layer region;
The group III nitride semiconductor device, wherein the ohmic electrode is in ohmic contact with the n-type conductive layer region through the surface of the recess.   The width of the heterojunction interface in the n-type conductive layer region is 50 nm or more in a direction perpendicular to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect. The group III nitride semiconductor device described. In the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ¹⁹ cm ⁻ under a temperature condition of 5 ° C. or more and 35 ° C. or less. ^The group III nitride semiconductor device according to claim 1, wherein the group is ³ or more and 1 × 10 ²² cm ⁻³ or less. In the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ¹⁹ under the operating temperature condition of the group III nitride semiconductor device. group III nitride semiconductor device according to any one of claims 1 to 3, characterized in that cm ^-3 to 1 × is ¹⁰ 22 ^{cm -3} or less. The concave surface has a side surface and a bottom surface;
5. The group III nitride semiconductor device according to claim 1, wherein the side surface of the concave portion has an inclination angle within a range of 45 degrees ± 15 degrees with respect to the heterojunction interface. . In the channel layer portion of the n-type conductive layer region, the concentration of the n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The group III nitride semiconductor device according to claim 1, wherein the device is a group III nitride semiconductor device. A plurality of the barrier layers;
The plurality of barrier layers are stacked above the channel layer;
The group III nitride semiconductor device according to any one of claims 1 to 6, wherein the barrier layer closest to the channel layer has an Al composition ratio higher than that of the other barrier layers.   8. The group III nitride semiconductor device according to claim 7, wherein the barrier layer closest to the channel layer is made of AlN.   The ohmic electrode is tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al) or gold (Au), oxides thereof, And a group III nitride semiconductor device according to claim 1, wherein the group III nitride semiconductor device is formed of at least one selected from the group consisting of nitrides thereof. The group III nitride semiconductor device according to claim 1, wherein the n-type impurity is at least one of ²⁸ Si and ²⁹ Si.   The channel layer is formed from gallium nitride (GaN) or indium gallium nitride (InGaN), and the barrier layer is formed from aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or indium aluminum nitride (InAlN). The group III nitride semiconductor device according to claim 1, wherein the group III nitride semiconductor device is formed. A plurality of the recesses and the ohmic electrodes are formed,
The ohmic electrode includes one or more source electrodes and one or more drain electrodes;
A gate electrode;
The gate electrode is formed above the barrier layer;
The group III nitride semiconductor device according to any one of claims 1 to 11, wherein the group III nitride semiconductor device is used as a heterojunction field effect transistor. A channel layer forming step of forming a channel layer from a group III nitride semiconductor;
A barrier layer forming step for forming a barrier layer by heterojunction a group III nitride semiconductor above the channel layer;
A recess forming step of forming a recess by removing a portion of the upper portion of the channel layer and the barrier layer thereabove;
The region including the surface of the recess is doped with n-type impurity ions by accelerating by potential difference so as to reach a depth of 15 nm or more from each part of the surface of the region in a measured value perpendicular to the surface. An n-type conductive layer region forming step of forming an n-type conductive layer region by being activated by
And a ohmic electrode formation step of forming an ohmic electrode in ohmic contact with the n-type conductive layer region through the surface of the recess.   The n-type conductive layer region forming step so that a width of the heterojunction interface in the n-type conductive layer region is 50 nm or more in a direction perpendicular to a line where the surface of the n-type conductive layer region and the heterojunction interface intersect The manufacturing method according to claim 13, wherein:   In the recess forming step, the recess is formed such that the recess has a side surface and a bottom surface, and the recess side surface has an inclination angle within a range of 45 degrees ± 15 degrees with respect to the heterojunction interface. The method according to claim 13 or 14, wherein the side surface of the concave portion is formed as described above. In the n-type conductive layer forming step, n-type impurity ions are doped so as to have a concentration of 1 × 10 ²⁰ cm ⁻³ or more at a heterojunction interface with the barrier layer above the channel layer. The manufacturing method as described in any one of Claim 13 to 15. In the n-type conductive layer region forming step, at least a part of the source electrode formation scheduled region and the drain electrode formation scheduled region is doped with the n-type impurity ions with an effective dose of 5 × 10 ¹⁵ cm ⁻² or more. The n-type impurity ion concentration is set to 1 × 10 ²⁰ cm ⁻³ or more at the heterojunction interface with the barrier layer above the channel layer.   The n-type conductive layer forming step is characterized in that a region to be subjected to the annealing treatment is previously covered with an annealing protective film, and the annealing treatment is performed at a temperature of 1,100 ° C. or more and 1,300 ° C. or less. The production method according to any one of 13 to 17. In the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ¹⁹ cm ⁻ under a temperature condition of 5 ° C. or more and 35 ° C. or less. The manufacturing method according to any one of claims 13 to 18, wherein the annealing treatment in the n-type conductive layer region forming step is performed so as to be ³ or more. In the channel layer portion of the n-type conductive layer region, the concentration of the ionized n-type impurity at the heterojunction interface with the barrier layer is 1 × 10 ¹⁹ cm under the operating temperature condition of the heterojunction field effect transistor. The manufacturing method according to any one of claims 13 to 19, wherein the annealing treatment in the n-type conductive layer region forming step is performed so as to be ^-3 or more. In the n-type conductive layer regions forming step, the manufacturing method according to claims 13 to any one of 20, characterized by doping as the n-type impurity at least one of the ^{28 Si} and ^{29 Si.}   In the ohmic electrode forming step, the ohmic electrode is made of tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al) or gold (Au The method according to any one of claims 13 to 21, wherein the production method is at least one selected from the group consisting of oxides thereof and nitrides thereof. In the channel layer forming step, the group III nitride semiconductor forming the channel layer is gallium nitride (GaN) or indium gallium nitride (InGaN),
In the barrier layer forming step, the group III nitride semiconductor forming the barrier layer is aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or indium aluminum nitride (InAlN). Item 23. The production method according to any one of Items 13 to 22.   A group III nitride semiconductor device manufactured by the manufacturing method according to any one of claims 13 to 23.   The group III nitride semiconductor device according to claim 24, which is used as a heterojunction field effect transistor.   An electronic device comprising the group III nitride semiconductor device according to any one of claims 1 to 10, 24, and 25.

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