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WO2018072304A1 - Goa驱动电路及液晶显示装置 - Google Patents

Goa驱动电路及液晶显示装置 Download PDF

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Publication number
WO2018072304A1
WO2018072304A1 PCT/CN2016/111059 CN2016111059W WO2018072304A1 WO 2018072304 A1 WO2018072304 A1 WO 2018072304A1 CN 2016111059 W CN2016111059 W CN 2016111059W WO 2018072304 A1 WO2018072304 A1 WO 2018072304A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
gate
drain
nth
Prior art date
Application number
PCT/CN2016/111059
Other languages
English (en)
French (fr)
Inventor
吕晓文
陈书志
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to EP16919325.7A priority Critical patent/EP3531410A4/en
Priority to KR1020197013127A priority patent/KR102190079B1/ko
Priority to US15/323,974 priority patent/US10121441B2/en
Priority to JP2019520818A priority patent/JP6775682B2/ja
Publication of WO2018072304A1 publication Critical patent/WO2018072304A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a GOA driving circuit and a liquid crystal display device.
  • Gate Driver On Array is a technology that uses a conventional thin film transistor liquid crystal display array process to fabricate a gate row scan driving signal circuit on an array substrate to realize a driving method of progressively scanning a pixel structure.
  • the present invention provides a GOA driving circuit, characterized in that the GOA driving circuit includes a plurality of cascaded GOA units, and outputs a gate driving signal to the N-th horizontal scanning line Gn of the display area according to the N-th stage GOA unit.
  • the N-level GOA unit includes a pull-up module, a pull-up control module, a pull-down maintenance module, a downlink module, and a bootstrap capacitor module; the pull-up module, the pull-down maintenance module, and the bootstrap capacitor module are respectively associated with the Nth-level gate signal
  • the point Qn and the Nth horizontal scanning line Gn are electrically connected, and the pull-up control module and the downlink module are connected to the Nth-level gate signal point Qn;
  • the pull-down maintaining module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a tenth thin film transistor, and a sixteenth thin film.
  • a transistor and a seventeenth thin film transistor a gate of the first thin film transistor and a drain of the second thin film transistor are connected to the drain of the second thin film transistor and connected to the Nth stage low frequency clock signal LCn, a source of the first thin film transistor, a gate of the second thin film transistor and a drain of the fourth thin film transistor, a source of the second thin film transistor, a drain of the third thin film transistor, a gate of the fifth thin film transistor, and a gate of the seventh thin film transistor Connected to the Nth common point Pn; the drain of the seventh thin film transistor and the drain of the eighth thin film transistor are connected to the Nth gate signal point Qn, the drain of the fifth thin film transistor and the first a drain of the ten thin film transistor is connected to the Nth horizontal scan line; the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the seventh The source-film transistor, and a tenth eighth thin film transistor TFT and the low reference voltage source is connected to a low voltage reference access;
  • a drain of the sixteenth thin film transistor is connected to the Nth common node Pn, and a gate of the sixteenth thin film transistor is connected to a reference low voltage source to access a reference low voltage, the sixteenth thin film transistor The gate is connected to the N+1th gate signal point Qn+1;
  • a drain of the seventeenth thin film transistor is connected to a source of the first thin film transistor and a gate of the second thin film transistor, and a gate of the seventeenth thin film transistor is connected to a reference low voltage source to input a reference low voltage.
  • a gate of the seventeenth sixth thin film transistor is connected to an N+1th gate signal point Qn+1;
  • the gates of the eighth thin film transistor and the tenth thin film transistor are connected and connected to the N+1th common node Pn+1, and the Nth stage low frequency clock signal LCn and the N+ accessed by the Nth stage GOA unit
  • the frequency of the N+1th low frequency clock signal LCn+1 accessed by the level 1 GOA unit is the same and the phases are opposite.
  • the pull-down maintaining module further includes a sixth thin film transistor and a ninth thin film transistor
  • the down-transmission module includes an eleventh thin film transistor
  • the drains of the sixth thin film transistor and the ninth thin film transistor respectively a source of the eleventh thin film transistor is connected
  • a gate of the sixth thin film transistor is connected to the Nth common node Pn
  • the drain of the eleventh thin film transistor is connected to the first high frequency clock signal
  • the gate of the eleventh thin film transistor is connected to the Nth gate signal point Qn.
  • the pull-up control module includes a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film transistor, a gate of the thirteenth thin film transistor and the fourteenth thin film transistor
  • the gate is connected to and connected to the second high frequency clock signal XCK, the source of the thirteenth thin film transistor, the drain of the fourteenth thin film transistor, and the drain of the fifteenth thin film transistor, and the source of the fifteenth thin film transistor
  • the pole is connected to the drain of the fifth thin film transistor and the drain of the ninth thin film transistor; the source of the fourteenth thin film transistor is connected to the Nth gate signal point Qn.
  • the reference low voltage includes a first reference low voltage VSS1 and a second reference low voltage VSS2;
  • the source of the third thin film transistor and the source of the sixteenth thin film transistor are connected to the second reference low voltage VSS1, the seventh thin film transistor, the sixth thin film transistor, the fifth thin film transistor, and the eighth thin film transistor And a source of the ninth thin film transistor and the tenth thin film transistor is connected to the first reference low voltage, and the voltage value of the second reference low voltage is smaller than a voltage value of the first reference low voltage.
  • the pull-up module includes a twelfth thin film transistor, a drain of the twelfth thin film transistor is connected to a first high level signal, a source of the twelfth thin film transistor and the Nth stage A horizontal scan line is connected, and a gate of the twelfth thin film transistor is connected to the Nth gate signal point.
  • the first high frequency clock signal and the second high frequency clock signal have the same frequency and opposite phases.
  • the first high frequency clock signal and the second high frequency clock signal are respectively connected through the first common metal line and the second common metal line.
  • the bootstrap capacitor module includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the Nth stage gate signal point Qn, and the other end of the bootstrap capacitor is horizontally scanned with the Nth stage Line Gn is connected.
  • the Nth stage low frequency clock signal Ln is accessed through a third common metal line.
  • the present invention also provides a GOA driving circuit comprising a plurality of cascaded GOA units, and outputting a gate driving signal to the display area Nth horizontal scanning line Gn according to the Nth stage GOA unit, the Nth stage GOA unit including Pulling module, pull-up control module, pull-down maintaining module, down-transmitting module and bootstrap capacitor module; said pull-up module, pull-down maintaining module and bootstrap capacitor module are respectively associated with Nth-level gate signal point Qn and Nth stage
  • the horizontal scanning line Gn is electrically connected, and the pull-up control module and the downlink module are connected to the Nth-level gate signal point Qn;
  • the pull-down maintaining module includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a tenth thin film transistor, and a sixteenth thin film.
  • a transistor and a seventeenth thin film transistor a gate of the first thin film transistor and a drain of the second thin film transistor are connected to the drain of the second thin film transistor and connected to the Nth stage low frequency clock signal LCn, a source of the first thin film transistor, a gate of the second thin film transistor and a drain of the fourth thin film transistor, a source of the second thin film transistor, a drain of the third thin film transistor, a gate of the fifth thin film transistor, and a gate of the seventh thin film transistor Connected to the Nth common point Pn; the drain of the seventh thin film transistor and the drain of the eighth thin film transistor are connected to the Nth gate signal point Qn, the drain of the fifth thin film transistor and the first a drain of the ten thin film transistor is connected to the Nth horizontal scan line; the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the seventh The source-film transistor, and a tenth eighth thin film transistor TFT and the low reference voltage source is connected to a low voltage reference access;
  • a drain of the sixteenth thin film transistor is connected to the Nth common node Pn, and a gate of the sixteenth thin film transistor is connected to a reference low voltage source to access a reference low voltage, the sixteenth thin film transistor The gate is connected to the N+1th gate signal point Qn+1;
  • a drain of the seventeenth thin film transistor is connected to a source of the first thin film transistor and a gate of the second thin film transistor, and a gate of the seventeenth thin film transistor is connected to a reference low voltage source to input a reference low voltage.
  • a gate of the seventeenth sixth thin film transistor is connected to an N+1th gate signal point Qn+1;
  • the gates of the eighth thin film transistor and the tenth thin film transistor are connected and connected to the N+1th common node Pn+1, and the Nth stage low frequency clock signal LCn and the N+ accessed by the Nth stage GOA unit
  • the frequency of the N+1th low frequency clock signal LCn+1 accessed by the level 1 GOA unit is the same and the phase is opposite;
  • the pull-down maintaining module further includes a sixth thin film transistor and a ninth thin film transistor, the down-transmission module includes an eleventh thin film transistor, and the drains of the sixth thin film transistor and the ninth thin film transistor respectively a source of the eleven thin film transistor is connected, a gate of the sixth thin film transistor is connected to the Nth common node Pn, and a gate of the ninth thin film transistor is connected to an N+1th common node Pn+1
  • the drain of the eleventh thin film transistor is connected to the first high frequency clock signal, and the gate of the eleventh thin film transistor is connected to the Nth gate signal point Qn;
  • the pull-up control module includes a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film transistor, and a gate of the thirteenth thin film transistor is connected to a gate of the fourteenth thin film transistor and connected a second high frequency clock signal XCK, a source of the thirteenth thin film transistor, a drain of the fourteenth thin film transistor, and a drain of the fifteenth thin film transistor, a source of the fifteenth thin film transistor and the fifth thin film a drain of the transistor and a drain of the ninth thin film transistor; a source of the fourteenth thin film transistor is connected to the Nth gate signal point Qn;
  • the reference low voltage includes a first reference low voltage VSS1 and a second reference low voltage VSS2;
  • the source of the third thin film transistor and the source of the sixteenth thin film transistor are connected to the second reference low voltage VSS1, the seventh thin film transistor, the sixth thin film transistor, the fifth thin film transistor, and the eighth thin film transistor a source of the ninth thin film transistor and the tenth thin film transistor is connected to the first reference low voltage, and a voltage value of the second reference low voltage is smaller than a voltage value of the first reference low voltage;
  • the pull-up module includes a twelfth thin film transistor, a drain of the twelfth thin film transistor is connected to a first high level signal, a source of the twelfth thin film transistor and the Nth horizontal scan line Connecting, a gate of the twelfth thin film transistor is connected to the Nth gate signal point;
  • the first high frequency clock signal and the second high frequency clock signal have the same frequency and opposite phases;
  • the first high frequency clock signal and the second high frequency clock signal are respectively accessed through the first common metal line and the second common metal line;
  • the bootstrap capacitor module includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the Nth stage gate signal point Qn, and the other end of the bootstrap capacitor is connected to the Nth horizontal scan line Gn ;
  • the Nth stage low frequency clock signal Ln is accessed through a third common metal line.
  • the present invention also provides a liquid crystal display device comprising the GOA driving circuit according to any of the above.
  • the GOA driving circuit provided by the present invention shares the N+1th common node Pn+1 of the pull-down maintaining module of the N+1th GOA unit through the pull-down maintaining module of the Nth stage GOA unit, so that each pull-down maintaining module only needs
  • a set of four thin film transistors can realize time-sharing use between the fifth thin film transistor and the seventh thin film transistor and the eighth thin film transistor and the tenth thin film transistor to avoid the fifth thin film transistor and the seventh thin film transistor.
  • the eighth thin film transistor and the tenth thin film transistor have been used all the time to cause the thin film transistor to fail, and have the beneficial effect of reducing the number of thin film transistors.
  • FIG. 1 is a schematic block diagram of a GOA driving circuit in a preferred embodiment of the present invention.
  • FIG. 2 is a circuit schematic diagram of an Nth stage GOA unit in the embodiment of FIG. 1 of the present invention.
  • the GOA driving circuit includes a plurality of cascaded GOA units, and outputs a gate driving signal to the display area Nth horizontal scanning line Gn according to the Nth stage GOA unit, the Nth level GOA.
  • the unit includes a pull-up control module 101, a pull-up module 102, a pull-down maintenance module 103, a downlink module 105, and a bootstrap capacitor module 104.
  • the pull-up module 102, the pull-down maintaining module 103, and the bootstrap capacitor module 104 are electrically connected to the Nth-level gate signal point Qn and the N-th horizontal scanning line Gn, respectively, and the pull-up control module 101 and the downlink module 105 and The Nth gate signal point Qn is connected.
  • the pull-down maintaining module 103 is also connected to the downlink module 105.
  • the pull-up module 102 includes a twelfth thin film transistor T12.
  • the gate of the twelfth thin film transistor T12 is connected to the Nth-level gate signal point Qn.
  • the twelfth thin film transistor T12 is connected.
  • the source is connected to the Nth horizontal scanning line Gn.
  • the pull-up module 102 is configured to output the first high-frequency clock signal CK as a gate scan signal to the Nth-level horizontal scan line Gn.
  • the down-going module 104 includes an eleventh thin film transistor T11.
  • the gate of the eleventh thin film transistor T11 is connected to the Nth-level gate signal point Qn, and the drain of the eleventh thin film transistor T11 is connected to the first high.
  • the frequency clock signal CK, the source of the eleventh thin film transistor T11 outputs the Nth stage down signal STn.
  • the pull-up control module 101 includes a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, and a fifteenth thin film transistor T15.
  • the gate of the thirteenth thin film transistor T13 is connected to the gate of the fourteenth thin film transistor T14 and is connected to the second high frequency clock signal XCK, and the second high frequency clock signal XCK has the same frequency as the first high frequency clock signal CK. The opposite is true.
  • the source of the thirteenth thin film transistor T13, the drain of the fourteenth thin film transistor T14, and the drain of the fifteenth thin film transistor T15 are connected, and the source of the fifteenth thin film transistor T15 is connected to the pull-down maintaining module 103, the tenth The source of the four thin film transistor is connected to the Nth stage gate signal point Qn.
  • the drain of the thirteenth thin film transistor T13 is connected to the turn-on signal STV, and when the Nth-level GOA unit is the first-level GOA unit, the thirteenth The drain of the thin film transistor T13 is connected to the down signal output from the down module 104 of the N-1th stage GOA unit.
  • the bootstrap capacitor module 105 includes a bootstrap capacitor Cb. One end of the bootstrap capacitor Cb is connected to the Nth gate signal point, and the other end of the bootstrap capacitor Cb is connected to the Nth horizontal scan line Gn.
  • the pull-down maintaining module 103 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth The thin film transistor T8, the ninth thin film transistor T9, the tenth thin film transistor T10, the sixteenth thin film transistor T16, and the seventeenth thin film transistor T17.
  • the gate of the first thin film transistor T1 is connected to the drain and the drain of the second thin film transistor T2 and is connected to the Nth stage low frequency clock signal LCn.
  • the gate of the thin film transistor T5, the gate of the sixth thin film transistor T6, and the gate of the seventh thin film transistor T7 are connected to the Nth common point Pn.
  • the drain of the seventh thin film transistor T7 and the drain of the eighth thin film transistor T8 are connected to the Nth gate signal point Qn, and are both used to pull down the voltage of the gate signal point Qn after the end of the line scanning.
  • the drain of the fifth thin film transistor T5 and the drain of the tenth thin film transistor T10 are connected to the Nth horizontal scanning line Gn; both are used to pull down the voltage of the Nth horizontal scanning line after the end of the line scanning.
  • the drain of the fifth thin film transistor T5 and the drain of the tenth thin film transistor T10 are connected to the source of the fifteenth thin film transistor T15 to lower the voltage of the source of the fifteenth thin film transistor T15. Therefore, the pull-up control module 101 is prevented from leaking to the Nth-level gate signal Qn point.
  • the drains of the sixth thin film transistor T6 and the ninth thin film transistor T9 are both connected to the source of the eleventh thin film transistor T11 for pulling down the output voltage of the down module 105 after the scanning is completed.
  • the reference low voltage source is connected to access the reference low voltage.
  • the reference low voltage includes a first reference low voltage VSS1 and a second reference low voltage VSS2.
  • the source of the third thin film transistor T3 and the source of the sixteenth thin film transistor T16 are connected to the second reference low voltage VSS1.
  • the sources of the seventh thin film transistor T7, the sixth thin film transistor T6, the fifth thin film transistor T5, the eighth thin film transistor T8, the ninth thin film transistor T9, and the tenth thin film transistor T10 are connected to the first reference low voltage VSS1.
  • the voltage value of the second reference low voltage VSS2 is smaller than the voltage value of the first reference low voltage VSS1.
  • the drain of the seventeenth thin film transistor T17 is connected to the source of the first thin film transistor T1 and the gate of the second thin film transistor T2, and the gate of the seventeenth thin film transistor T17 is connected to the reference low voltage source to be low in the reference.
  • the voltage, the gate of the seventeenth thin film transistor T17 is connected to the N+1th gate signal point Qn+1.
  • the sixteenth thin film transistor T16 is for forcibly pulling down the voltage of the Nth stage common node Pn when scanning the (N+1)th row.
  • the seventeenth thin film transistor T17 is for forcibly pulling down the potential voltage of the connection point between the source of the first thin film transistor T1 and the gate of the second thin film transistor T2 when scanning the (N+1)th row.
  • the gates of the eighth thin film transistor T8, the ninth thin film transistor T9, and the tenth thin film transistor T10 are connected and connected to the (N+1)th common node Pn+1.
  • the pull-down maintaining modules of the adjacent two GOA units can share the potential of the common node P, and the number of thin film transistors can be reduced.
  • the Nth low frequency clock signal LCn accessed by the Nth stage GOA unit is the same as the frequency of the N+1th low frequency clock signal LCn+1 accessed by the N+1th GOA unit, and the phases are opposite, the adjacent A portion of the thin film transistors of the pull-down sustaining modules 103 of the two GOA units can alternately operate to avoid failure due to prolonged use.
  • the GOA driving circuit provided by the present invention shares the N+1th common node Pn+1 of the pull-down maintaining module of the N+1th GOA unit through the pull-down maintaining module of the Nth stage GOA unit, so that each pull-down maintaining module only needs
  • a set of four thin film transistors can realize time-sharing use between the fifth thin film transistor and the seventh thin film transistor and the eighth thin film transistor and the tenth thin film transistor to avoid the fifth thin film transistor and the seventh thin film transistor.
  • the eighth thin film transistor and the tenth thin film transistor have been used all the time to cause the thin film transistor to fail, and have the beneficial effect of reducing the number of thin film transistors.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种GOA驱动电路及液晶显示装置，GOA驱动电路包括多个级联的GOA单元，该第N级GOA单元包括上拉模块(102)、上拉控制模块(101)、下拉维持模块(103)、下传模块(105)以及自举电容模块(104)；上拉模块(102)、下拉维持模块(103)以及自举电容模块(104) 均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，上拉控制模块(101)以及下传模块(105)与第N级栅极信号点Qn连接。

Description

GOA驱动电路及液晶显示装置 技术领域
本发明涉及液晶显示领域，特别是涉及一种GOA驱动电路及液晶显示装置。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对像素结构逐行扫描的驱动方式的一项技术。
随着技术的发展，窄边框是一种必然趋势。现有技术中，GOA驱动电路使用薄膜晶体管的数量较多，如何在不影响功能的情况下减薄膜晶体管的数量是一个技术难题。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种改进的GOA驱动电路及液晶显示装置。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种GOA驱动电路，其特征在于，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
所述下拉维持模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管；所述第一薄膜晶体管的栅极与漏极以及第二薄膜晶体管的漏极连接并接入第N级低频时钟信号LCn，所述第一薄膜晶体管的源极、第二薄膜晶体管的栅极以及第四薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极、第三薄膜晶体管的漏极、第五薄膜晶体管的栅极以及第七薄膜晶体管的栅极连接于第N级公共点Pn；所述第七薄膜晶体管的漏极以及第八薄膜晶体管的漏极与第N级栅极信号点Qn连接，所述第五薄膜晶体管的漏极以及所述第十薄膜晶体管的漏极与所述第N级水平扫描线连接；所述第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第十薄膜晶体管的源极与基准低电压源连接以接入基准低电压；
所述第十六薄膜晶体管的漏极与所述第N级公共节点Pn连接，所述第十六薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
所述第十七薄膜晶体管的漏极与第一薄膜晶体管的源极以及第二薄膜晶体管的栅极连接，所述第十七薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十七六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
所述第八薄膜晶体管以及第十薄膜晶体管的栅极连接并与第N+1级公共节点Pn+1连接，所述第N级GOA单元接入的第N级低频时钟信号LCn与第N+1级GOA单元接入的第N+1级低频时钟信号LCn+1的频率相同且相位相反。
优选地，所述下拉维持模块还包括第六薄膜晶体管以及第九薄膜晶体管，所述下传模块包括第十一薄膜晶体管，所述第六薄膜晶体管以及所述第九薄膜晶体管的漏极分别与所述第十一薄膜晶体管的源极连接，所述第六薄膜晶体管的栅极与所述第N级公共节点Pn连接，所述第九薄膜晶体管的栅极与第N+1级公共节点Pn+1连接，所述第十一薄膜晶体管的漏极接入第一高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn连接。
优选地，其特征在于，所述上拉控制模块包括第十三薄膜晶体管、第十四薄膜晶体管以及第十五薄膜晶体管，所述第十三薄膜晶体管的栅极与所述第十四薄膜晶体管的栅极连接并接入第二高频时钟信号XCK，第十三薄膜晶体管的源极、第十四薄膜晶体管的漏极以及第十五薄膜晶体管的漏极连接，第十五薄膜晶体管的源极与所述第五薄膜晶体管的漏极以及第九薄膜晶体管的漏极连接；第十四薄膜晶体管的源极与第N级栅极信号点Qn连接。
优选地，所述基准低电压包括第一基准低电压VSS1以及第二基准低电压VSS2；
所述第三薄膜晶体管的源极以及第十六薄膜晶体管的源极接入所述第二基准低电压VSS1，所述第七薄膜晶体管、第六薄膜晶体管、第五薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管的源极接入所述第一基准低电压，所述第二基准低电压的电压值小于所述第一基准低电压的电压值。
优选地，所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入第一高电平信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线连接，所述第十二薄膜晶体管的栅极与所述第N级栅极信号点连接。
优选地，所述第一高频时钟信号与所述第二高频时钟信号频率相同且相位相反。
优选地，所述第一高频时钟信号以及第二高频时钟信号分别通过第一公共金属线以及第二公共金属线接入。
优选地，所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接。
优选地，所述第N级低频时钟信号Ln通过第三公共金属线接入。
本发明还提供一种GOA驱动电路，其包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
所述下拉维持模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管；所述第一薄膜晶体管的栅极与漏极以及第二薄膜晶体管的漏极连接并接入第N级低频时钟信号LCn，所述第一薄膜晶体管的源极、第二薄膜晶体管的栅极以及第四薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极、第三薄膜晶体管的漏极、第五薄膜晶体管的栅极以及第七薄膜晶体管的栅极连接于第N级公共点Pn；所述第七薄膜晶体管的漏极以及第八薄膜晶体管的漏极与第N级栅极信号点Qn连接，所述第五薄膜晶体管的漏极以及所述第十薄膜晶体管的漏极与所述第N级水平扫描线连接；所述第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第十薄膜晶体管的源极与基准低电压源连接以接入基准低电压；
所述第十六薄膜晶体管的漏极与所述第N级公共节点Pn连接，所述第十六薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
所述第十七薄膜晶体管的漏极与第一薄膜晶体管的源极以及第二薄膜晶体管的栅极连接，所述第十七薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十七六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
所述第八薄膜晶体管以及第十薄膜晶体管的栅极连接并与第N+1级公共节点Pn+1连接，所述第N级GOA单元接入的第N级低频时钟信号LCn与第N+1级GOA单元接入的第N+1级低频时钟信号LCn+1的频率相同且相位相反；
所述下拉维持模块还包括第六薄膜晶体管以及第九薄膜晶体管，所述下传模块包括第十一薄膜晶体管，所述第六薄膜晶体管以及所述第九薄膜晶体管的漏极分别与所述第十一薄膜晶体管的源极连接，所述第六薄膜晶体管的栅极与所述第N级公共节点Pn连接，所述第九薄膜晶体管的栅极与第N+1级公共节点Pn+1连接，所述第十一薄膜晶体管的漏极接入第一高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn连接；
所述上拉控制模块包括第十三薄膜晶体管、第十四薄膜晶体管以及第十五薄膜晶体管，所述第十三薄膜晶体管的栅极与所述第十四薄膜晶体管的栅极连接并接入第二高频时钟信号XCK，第十三薄膜晶体管的源极、第十四薄膜晶体管的漏极以及第十五薄膜晶体管的漏极连接，第十五薄膜晶体管的源极与所述第五薄膜晶体管的漏极以及第九薄膜晶体管的漏极连接；第十四薄膜晶体管的源极与第N级栅极信号点Qn连接；
所述基准低电压包括第一基准低电压VSS1以及第二基准低电压VSS2；
所述第三薄膜晶体管的源极以及第十六薄膜晶体管的源极接入所述第二基准低电压VSS1，所述第七薄膜晶体管、第六薄膜晶体管、第五薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管的源极接入所述第一基准低电压，所述第二基准低电压的电压值小于所述第一基准低电压的电压值；
所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入第一高电平信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线连接，所述第十二薄膜晶体管的栅极与所述第N级栅极信号点连接；
所述第一高频时钟信号与所述第二高频时钟信号频率相同且相位相反；
所述第一高频时钟信号以及第二高频时钟信号分别通过第一公共金属线以及第二公共金属线接入；
所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接；
所述第N级低频时钟信号Ln通过第三公共金属线接入。
本发明还提供一种液晶显示装置，包括上述任一项所述的GOA驱动电路。
 有益效果
本发明提供的GOA驱动电路通过第N级GOA单元的下拉维持模块共享第N+1级GOA单元的下拉维持模块的第N+1级公共节点Pn+1，从而使得每一下拉维持模块仅需一组共四个薄膜晶体管就可以实现对于第五薄膜晶体管和第七薄膜晶体管与第八薄膜晶体管与第十薄膜晶体管之间的分时使用，以避免由于第五薄膜晶体管和第七薄膜晶体管与第八薄膜晶体管与第十薄膜晶体管一直使用导致薄膜晶体管失效，具有减少薄膜晶体管数量的有益效果。
 附图说明
图1是本发明一优选实施例中的GOA驱动电路的原理框图。
图2是本发明图1所示实施例中的第N级GOA单元的电路原理图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的模块是以相同标号表示。
请参照图1，该GOA驱动电路，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉控制模块101、上拉模块102、下拉维持模块103、下传模块105以及自举电容模块104。上拉模块102、下拉维持模块103以及自举电容模块104均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块101以及下传模块105与第N级栅极信号点Qn连接。该下拉维持模块103还与该下传模块105连接。
具体地，同时参照图2，该上拉模块102包括第十二薄膜晶体管T12，该第十二薄膜晶体管T12的栅极与该第N级栅极信号点Qn连接，该第十二薄膜晶体管T12的源极与该第N级水平扫描线Gn连接。该上拉模块102用于将第一高频时钟信号CK输出为栅极扫描信号给该第N级水平扫描线Gn。
该下传模块104包括第十一薄膜晶体管T11，该第十一薄膜晶体管T11的栅极与该第N级栅极信号点Qn连接，该第十一薄膜晶体管T11的漏极接入第一高频时钟信号CK，该第十一薄膜晶体管T11的源极输出第N级下传信号STn。
该上拉控制模块101包括第十三薄膜晶体管T13、第十四薄膜晶体管T14以及第十五薄膜晶体管T15。第十三薄膜晶体管T13的栅极与第十四薄膜晶体管T14的栅极连接并接入第二高频时钟信号XCK，该第二高频时钟信号XCK与该第一高频时钟信号CK频率相同，相位相反。第十三薄膜晶体管T13的源极、第十四薄膜晶体管T14的漏极以及第十五薄膜晶体管T15的漏极连接，第十五薄膜晶体管T15的源极与下拉维持模块103连接，该第十四薄膜晶体管的源极与第N级栅极信号点Qn连接。当该第N级GOA单元为第1级GOA单元时，该第十三薄膜晶体管T13的漏极接入开启信号STV，当该第N级GOA单元为第1级GOA单元时，该第十三薄膜晶体管T13的漏极接入第N-1级GOA单元的下传模块104输出的下传信号。
该自举电容模块105包括自举电容Cb，该自举电容Cb的一端与该第N级栅极信号点连接，该自举电容Cb的另一端与第N级水平扫描线Gn连接。
该下拉维持模块103包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十六薄膜晶体管T16以及第十七薄膜晶体管T17。
该第一薄膜晶体管T1的栅极与漏极以及第二薄膜晶体管T2的漏极连接并接入第N级低频时钟信号LCn。第一薄膜晶体管T1的源极、第二薄膜晶体管T2的栅极以及第四薄膜晶体管T4的漏极连接，所述第二薄膜晶体管T2的源极、第三薄膜晶体管T3的漏极、第五薄膜晶体管T5的栅极、第六薄膜晶体管T6的栅极以及第七薄膜晶体管T7的栅极连接于第N级公共点Pn。
第七薄膜晶体管T7的漏极以及第八薄膜晶体管T8的漏极与第N级栅极信号点Qn连接，均用于在该行扫描结束后，拉低该栅极信号点Qn的电压。
第五薄膜晶体管T5的漏极以及第十薄膜晶体管T10的漏极与第N级水平扫描线Gn连接；均用于在该行扫描结束后，拉低该第N级水平扫描线的电压。该第五薄膜晶体管T5的漏极以及第十薄膜晶体管T10的漏极该与该第十五薄膜晶体管T15的源极连接，以拉低该第十五薄膜晶体管T15源极的电压。从而避免该上拉控制模块101向第N级栅极信号Qn点漏电。
该第六薄膜晶体管T6以及该第九薄膜晶体管T9的漏极均与该第十一薄膜晶体管T11的源极连接，用于在扫描结束后拉低下传模块105的输出电压。
第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8第九薄膜晶体管T9以及第十薄膜晶体管T10的源极与基准低电压源连接以接入基准低电压。具体地，该基准低电压包括第一基准低电压VSS1以及第二基准低电压VSS2。第三薄膜晶体管T3的源极以及第十六薄膜晶体管T16的源极接入第二基准低电压VSS1。第七薄膜晶体管T7、第六薄膜晶体管T6、第五薄膜晶体管T5、第八薄膜晶体管T8、第九薄膜晶体管T9以及第十薄膜晶体管T10的源极接入所述第一基准低电压VSS1，所述第二基准低电压VSS2的电压值小于所述第一基准低电压VSS1的电压值。
第十七薄膜晶体管T17的漏极与第一薄膜晶体管T1的源极以及第二薄膜晶体管T2的栅极连接，所述第十七薄膜晶体管T17的栅极与基准低压源连接以接入基准低电压，所述第十七六薄膜晶体管T17的栅极与第N+1级栅极信号点Qn+1连接。
该第十六薄膜晶体管T16用于在扫描第N+1行时，强行拉低该第N级公共节点Pn的电压。
该第十七薄膜晶体管T17用于在扫描第N+1行时，强行拉低第一薄膜晶体管T1的源极与第二薄膜晶体管T2的栅极的连接点的电位压。
第八薄膜晶体管T8、第九薄膜晶体管T9以及第十薄膜晶体管T10的栅极连接并与第N+1级公共节点Pn+1连接。从而使得相邻两个GOA单元的下拉维持模块可以共享公共节点P的电位，可以减少薄膜晶体管的数量。并且，由于第N级GOA单元接入的第N级低频时钟信号LCn与第N+1级GOA单元接入的第N+1级低频时钟信号LCn+1的频率相同且相位相反，使得相邻两个GOA单元的下拉维持模块103的部分薄膜晶体管可以交替工作，从而避免由于长时间使用而失效。
本发明提供的GOA驱动电路通过第N级GOA单元的下拉维持模块共享第N+1级GOA单元的下拉维持模块的第N+1级公共节点Pn+1，从而使得每一下拉维持模块仅需一组共四个薄膜晶体管就可以实现对于第五薄膜晶体管和第七薄膜晶体管与第八薄膜晶体管与第十薄膜晶体管之间的分时使用，以避免由于第五薄膜晶体管和第七薄膜晶体管与第八薄膜晶体管与第十薄膜晶体管一直使用导致薄膜晶体管失效，具有减少薄膜晶体管数量的有益效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种GOA驱动电路，其包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
    所述下拉维持模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管；所述第一薄膜晶体管的栅极与漏极以及第二薄膜晶体管的漏极连接并接入第N级低频时钟信号LCn，所述第一薄膜晶体管的源极、第二薄膜晶体管的栅极以及第四薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极、第三薄膜晶体管的漏极、第五薄膜晶体管的栅极以及第七薄膜晶体管的栅极连接于第N级公共点Pn；所述第七薄膜晶体管的漏极以及第八薄膜晶体管的漏极与第N级栅极信号点Qn连接，所述第五薄膜晶体管的漏极以及所述第十薄膜晶体管的漏极与所述第N级水平扫描线连接；所述第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第十薄膜晶体管的源极与基准低电压源连接以接入基准低电压；
    所述第十六薄膜晶体管的漏极与所述第N级公共节点Pn连接，所述第十六薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
    所述第十七薄膜晶体管的漏极与第一薄膜晶体管的源极以及第二薄膜晶体管的栅极连接，所述第十七薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十七六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
    所述第八薄膜晶体管以及第十薄膜晶体管的栅极连接并与第N+1级公共节点Pn+1连接，所述第N级GOA单元接入的第N级低频时钟信号LCn与第N+1级GOA单元接入的第N+1级低频时钟信号LCn+1的频率相同且相位相反。
  2. 根据权利要求1所述的GOA驱动电路，其中，所述下拉维持模块还包括第六薄膜晶体管以及第九薄膜晶体管，所述下传模块包括第十一薄膜晶体管，所述第六薄膜晶体管以及所述第九薄膜晶体管的漏极分别与所述第十一薄膜晶体管的源极连接，所述第六薄膜晶体管的栅极与所述第N级公共节点Pn连接，所述第九薄膜晶体管的栅极与第N+1级公共节点Pn+1连接，所述第十一薄膜晶体管的漏极接入第一高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn连接。
  3. 根据权利要求2所述的GOA驱动电路，其中，所述上拉控制模块包括第十三薄膜晶体管、第十四薄膜晶体管以及第十五薄膜晶体管，所述第十三薄膜晶体管的栅极与所述第十四薄膜晶体管的栅极连接并接入第二高频时钟信号XCK，第十三薄膜晶体管的源极、第十四薄膜晶体管的漏极以及第十五薄膜晶体管的漏极连接，第十五薄膜晶体管的源极与所述第五薄膜晶体管的漏极以及第九薄膜晶体管的漏极连接；第十四薄膜晶体管的源极与第N级栅极信号点Qn连接。
  4. 根据权利要求3所述的GOA驱动电路，其中，所述基准低电压包括第一基准低电压VSS1以及第二基准低电压VSS2；
    所述第三薄膜晶体管的源极以及第十六薄膜晶体管的源极接入所述第二基准低电压VSS1，所述第七薄膜晶体管、第六薄膜晶体管、第五薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管的源极接入所述第一基准低电压，所述第二基准低电压的电压值小于所述第一基准低电压的电压值。
  5. 根据权利要求4所述的GOA驱动电路，其中，所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入第一高电平信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线连接，所述第十二薄膜晶体管的栅极与所述第N级栅极信号点连接。
  6. 根据权利要求3所述的GOA驱动电路，其中，所述第一高频时钟信号与所述第二高频时钟信号频率相同且相位相反。
  7. 根据权利要求6所述的GOA驱动电路，其中，所述第一高频时钟信号以及第二高频时钟信号分别通过第一公共金属线以及第二公共金属线接入。
  8. 根据权利要求1所述的GOA驱动电路，其中，所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接。
  9. 根据权利要求1所述的GOA驱动电路，其中，所述第N级低频时钟信号Ln通过第三公共金属线接入。
  10. 一种GOA驱动电路，其包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线Gn，该第N级GOA单元包括上拉模块、上拉控制模块、下拉维持模块、下传模块以及自举电容模块；所述上拉模块、下拉维持模块以及自举电容模块均分别与第N级栅极信号点Qn以及第N级水平扫描线Gn电连接，所述上拉控制模块以及下传模块与第N级栅极信号点Qn连接；
    所述下拉维持模块包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第十薄膜晶体管、第十六薄膜晶体管以及第十七薄膜晶体管；所述第一薄膜晶体管的栅极与漏极以及第二薄膜晶体管的漏极连接并接入第N级低频时钟信号LCn，所述第一薄膜晶体管的源极、第二薄膜晶体管的栅极以及第四薄膜晶体管的漏极连接，所述第二薄膜晶体管的源极、第三薄膜晶体管的漏极、第五薄膜晶体管的栅极以及第七薄膜晶体管的栅极连接于第N级公共点Pn；所述第七薄膜晶体管的漏极以及第八薄膜晶体管的漏极与第N级栅极信号点Qn连接，所述第五薄膜晶体管的漏极以及所述第十薄膜晶体管的漏极与所述第N级水平扫描线连接；所述第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第十薄膜晶体管的源极与基准低电压源连接以接入基准低电压；
    所述第十六薄膜晶体管的漏极与所述第N级公共节点Pn连接，所述第十六薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
    所述第十七薄膜晶体管的漏极与第一薄膜晶体管的源极以及第二薄膜晶体管的栅极连接，所述第十七薄膜晶体管的栅极与基准低压源连接以接入基准低电压，所述第十七六薄膜晶体管的栅极与第N+1级栅极信号点Qn+1连接；
    所述第八薄膜晶体管以及第十薄膜晶体管的栅极连接并与第N+1级公共节点Pn+1连接，所述第N级GOA单元接入的第N级低频时钟信号LCn与第N+1级GOA单元接入的第N+1级低频时钟信号LCn+1的频率相同且相位相反；
    所述下拉维持模块还包括第六薄膜晶体管以及第九薄膜晶体管，所述下传模块包括第十一薄膜晶体管，所述第六薄膜晶体管以及所述第九薄膜晶体管的漏极分别与所述第十一薄膜晶体管的源极连接，所述第六薄膜晶体管的栅极与所述第N级公共节点Pn连接，所述第九薄膜晶体管的栅极与第N+1级公共节点Pn+1连接，所述第十一薄膜晶体管的漏极接入第一高频时钟信号，所述第十一薄膜晶体管的栅极与第N级栅极信号点Qn连接；
    所述上拉控制模块包括第十三薄膜晶体管、第十四薄膜晶体管以及第十五薄膜晶体管，所述第十三薄膜晶体管的栅极与所述第十四薄膜晶体管的栅极连接并接入第二高频时钟信号XCK，第十三薄膜晶体管的源极、第十四薄膜晶体管的漏极以及第十五薄膜晶体管的漏极连接，第十五薄膜晶体管的源极与所述第五薄膜晶体管的漏极以及第九薄膜晶体管的漏极连接；第十四薄膜晶体管的源极与第N级栅极信号点Qn连接；
    所述基准低电压包括第一基准低电压VSS1以及第二基准低电压VSS2；
    所述第三薄膜晶体管的源极以及第十六薄膜晶体管的源极接入所述第二基准低电压VSS1，所述第七薄膜晶体管、第六薄膜晶体管、第五薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管的源极接入所述第一基准低电压，所述第二基准低电压的电压值小于所述第一基准低电压的电压值；
    所述上拉模块包括第十二薄膜晶体管，所述第十二薄膜晶体管的漏极接入第一高电平信号，所述第十二薄膜晶体管的源极与所述第N级水平扫描线连接，所述第十二薄膜晶体管的栅极与所述第N级栅极信号点连接；
    所述第一高频时钟信号与所述第二高频时钟信号频率相同且相位相反；
    所述第一高频时钟信号以及第二高频时钟信号分别通过第一公共金属线以及第二公共金属线接入；
    所述自举电容模块包括自举电容，所述自举电容的一端与所述第N级栅极信号点Qn连接，所述自举电容的另一端与所述第N级水平扫描线Gn连接；
    所述第N级低频时钟信号Ln通过第三公共金属线接入。
  11. 一种液晶显示装置，其包括权利要求1所述的GOA驱动电路。
  12. 一种液晶显示装置，其包括权利要求10所述的GOA驱动电路。
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