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WO2010038257A1 - Dispositif programmable et procédé d'écriture de données - Google Patents

Dispositif programmable et procédé d'écriture de données Download PDF

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Publication number
WO2010038257A1
WO2010038257A1 PCT/JP2008/002748 JP2008002748W WO2010038257A1 WO 2010038257 A1 WO2010038257 A1 WO 2010038257A1 JP 2008002748 W JP2008002748 W JP 2008002748W WO 2010038257 A1 WO2010038257 A1 WO 2010038257A1
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WO
WIPO (PCT)
Prior art keywords
floating electrode
insulating film
wiring
programmable device
circuit
Prior art date
Application number
PCT/JP2008/002748
Other languages
English (en)
Japanese (ja)
Inventor
岡安俊幸
渡邊大輔
Original Assignee
株式会社アドバンテスト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to PCT/JP2008/002748 priority Critical patent/WO2010038257A1/fr
Priority to JP2010531654A priority patent/JPWO2010038257A1/ja
Priority to TW098133035A priority patent/TW201015857A/zh
Publication of WO2010038257A1 publication Critical patent/WO2010038257A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to a programmable device and a data writing method.
  • Programmable logic circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) have a plurality of logic blocks, and the connection relationship between these logic blocks or logic elements can be switched by user programming (for example, , See Patent Document 1).
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • Patent Document 1 JP-A-8-204543
  • the switching state of the switching transistor changes according to data programmed by the user. For example, a voltage corresponding to program data is applied to the gate terminal of each switching transistor. Thereby, the connection relationship of each logical block can be changed according to a user's program. Data programmed by the user is stored in a memory provided in the device.
  • a voltage corresponding to a user program is supplied to the gate terminal of each switching transistor.
  • a wiring for supplying the voltage to each switching transistor is provided, and a region where a logic block or the like can be formed becomes narrow.
  • the programmable logic circuit is provided with a memory for storing a user program. This also narrows the area where logic blocks and the like can be formed.
  • an object of the present invention is to provide a programmable device and a data writing method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a programmable device in which the logical relationship of output logic data to input logic data changes according to predetermined program data, which can be irradiated with an electron beam.
  • the logical relationship of the output logic data to the input logic data depending on the amount of charge that is provided and stores the program data by storing the charge by irradiating the electron beam and the program data is stored
  • a programmable device is provided comprising a programmable logic array that varies.
  • the charge corresponding to the predetermined program data is held in each floating electrode, and the program data is written to the programmable device that functions according to the program data stored in the floating electrode.
  • a data writing method for irradiating a floating electrode with an electron beam according to program data to be written is provided.
  • FIG. 2 is a schematic diagram illustrating an example of an internal configuration of a programmable logic array 12.
  • FIG. 3 is a diagram illustrating a configuration example of a circuit connection unit 107.
  • FIG. 3 is a diagram illustrating a configuration example of a switching unit 102.
  • FIG. It is a figure which shows the other structural example of the programmable logic array.
  • 3 is a diagram illustrating a configuration example of an individual connection unit 109.
  • FIG. 6 is a diagram illustrating another configuration example of the circuit connection unit 107.
  • FIG. 2 is a top view of a transistor 101.
  • FIG. FIG. 9 is a cross-sectional view taken along a line AA ′ in FIG.
  • FIG. 10 is a cross-sectional view illustrating another structural example of the transistor 101.
  • 12 is a cross-sectional view illustrating still another configuration example of the transistor 101.
  • FIG. 12 is a cross-sectional view illustrating still another configuration example of the transistor 101.
  • DESCRIPTION OF SYMBOLS 10 ... Programmable device, 11 ... Data input terminal, 12 ... Programmable logic array, 13 ... Cache memory, 14 ... Data output terminal, 15 ... Input / output circuit, 20 ... Circuit block 31... Row direction wiring 32... Column direction wiring 51 .. input wiring 52 .. output wiring 71 .. individual wiring 81 .. buffer circuit 91. Input driver circuit, 92 ... Output driver circuit, 101 ... Transistor, 102 ... Switching unit, 107 ... Circuit connection unit, 108 ... Wiring connection unit, 109 ... Individual connection unit, DESCRIPTION OF SYMBOLS 110 ... Semiconductor substrate, 111 ... Source region, 113 ... Drain region, 115 ...
  • Isolation region 121 ... Insulating film, 122 ... Insulating film, 123 ... Insulating film, 131 ... Rotating electrode, 151 ... via, 161 ... pattern wiring, 162 ... pattern wiring, 164 ... pattern wiring, 171 ... guard ring, 172 ... guard ring, 184 ... guard Terminal, 191 ... through hole, 200 ... package part
  • FIG. 1 shows a functional block diagram of a programmable device 10 according to an embodiment of the present invention.
  • the programmable device 10 is a device in which the logical relationship of output logical data with respect to input logical data changes according to given program data, and includes a data input terminal 11, a programmable logic array 12, a cache memory 13, and a data output terminal. 14.
  • the programmable device 10 may be a PLD, an FPGA, or the like, for example.
  • the logical relationship of the output logical data with respect to the input logical data may be a relationship indicating the value of the output logical data with respect to each value of the input logical data.
  • the program data may be given from the user, manufacturer, etc. of the programmable device 10.
  • the programmable logic array 12 is a logic operation circuit that outputs output logic data corresponding to input logic data given from the outside via the data input terminal 11 to the cache memory 13, and by writing predetermined program data, The logical structure can be changed to a predetermined one.
  • the cache memory 13 stores output logic data from the programmable logic array 12.
  • the cache memory 13 outputs a part or all of stored data to the outside through the data output terminal 14 by accepting access from the outside, for example.
  • FIG. 2 is a schematic diagram showing an example of the internal configuration of the programmable logic array 12.
  • the programmable logic array 12 includes an input / output circuit 15, a plurality of circuit blocks 20, a plurality of column direction wirings 32, a plurality of row direction wirings 31, a plurality of circuit connection units 107, and a plurality of wiring connection units 108.
  • each of the circuit connection unit 107 and the wiring connection unit 108 may include a plurality of transistors 101.
  • the plurality of transistors 101 select whether or not to connect each circuit block 20 to each other circuit block 20.
  • the plurality of transistors 101 include at least a first circuit block 20-1 and a second circuit block 20-2, a first circuit block 20-1 and a third circuit block 20-3, and a second circuit. For each of the block 20-2 and the third circuit block 20-3, it may be selected whether or not the circuit blocks 20 are connected.
  • connection relationship of the plurality of circuit blocks 20 is selected according to the state of the plurality of transistors 101. For example, by controlling on / off of the transistor 101 in accordance with program data given by a user, a circuit having a logical structure corresponding to the program data can be formed.
  • the transistor 101 in this example has a floating electrode as a gate terminal. That is, each transistor 101 switches between an on state and an off state in accordance with the amount of charge accumulated in the floating electrode.
  • each floating electrode is provided so as to be able to irradiate an electron beam at least before or after packaging of the programmable device 10.
  • the programmable device 10 may be manufactured such that at least a part of the surface of each floating electrode is exposed before packaging.
  • each floating electrode by irradiating each floating electrode with an electron beam according to the program data given by the user, the on / off state of each transistor 101 is directly controlled by the amount of charge injected into the floating electrode by the electron beam. Can be controlled. Therefore, a wiring for applying a gate voltage to the transistor 101 is not necessarily provided. Therefore, the area where the circuit block 20 and the like can be formed can be enlarged.
  • the on / off state of the transistor is changed by applying a voltage corresponding to user program data to the gate terminal of each transistor 101.
  • a wiring for supplying a gate voltage is provided for each transistor, and a memory area for storing user program data is provided. For this reason, a region where the circuit block 20 and the like can be formed becomes narrow.
  • the programmable device 10 in this example can form the circuit blocks 20 and the like with higher density.
  • the row direction wiring 31 and the column direction wiring 32 are examples of common connection wiring provided in common to the plurality of circuit blocks 20.
  • the plurality of circuit blocks 20 are arranged in a matrix, for example.
  • a predetermined number of row-direction wirings 31 are provided between the circuit blocks 20 adjacent in the column direction, and a predetermined number of column directions are provided between the circuit blocks 20 adjacent in the row direction.
  • a wiring 32 is provided.
  • four row direction wirings 31 and four column direction wirings 32 are provided between each circuit block 20, but the number of these wirings is not limited to four.
  • the total number of row direction wirings 31 and column direction wirings 32 provided adjacent to each circuit block 20 is preferably larger than the number of input / output terminals of the circuit block 20.
  • Each circuit block 20 has a predetermined number of input terminals In and a predetermined number of output terminals Out.
  • the input terminal In is connected to one of a predetermined number of column-directional wirings 32 provided adjacent to each other via the input wiring 51.
  • the circuit connection unit 107 is provided corresponding to each circuit block 20. The plurality of transistors 101 in each circuit connection unit 107 select which column direction wiring 32 and row direction wiring 31 the input terminal In and the output terminal Out of the corresponding circuit block 20 are connected to.
  • the transistor 101 is provided in one-to-one correspondence with a predetermined number of column-directional wirings 32 provided adjacent to each of the input wirings 51 (for example, the transistors 101-1, 101-2, 101-3, 101-4).
  • each input wiring 51 is electrically connected to the column-directional wiring 32 corresponding to the transistor 101 set to the on state.
  • the output terminal Out of this example is connected to one of a predetermined number of row-directional wirings 31 provided adjacent to each other via the output wiring 52.
  • the plurality of transistors 101 in the circuit connection unit 107 determine which row-direction wiring 31 each output wiring 52 is electrically connected to.
  • the transistors 101 are provided in one-to-one correspondence with a predetermined number of row-directional wirings 31 provided adjacent to each other in each output wiring 52.
  • each output wiring 52 is electrically connected to the row direction wiring 31 corresponding to the transistor 101 set to the on state.
  • Each row direction wiring 31 is provided so as to intersect with a plurality of column direction wirings 32.
  • each row direction wiring 31 may be provided so as to cross all the column direction wirings 32.
  • each row direction wiring 31 may be electrically connected to a predetermined column direction wiring 32 among the column direction wirings 32 that intersect.
  • each row direction wiring 31 may be electrically connected to any one column direction wiring 32.
  • the wiring connection unit 108 selects which column direction wiring 32 to connect each row direction wiring 31 to.
  • the wiring connection unit 108 may electrically connect each row direction wiring 31 to a predetermined column direction wiring 32 by a previously fixed wiring.
  • the wiring connection unit 108 may include a plurality of switching units 102 that select which column-direction wiring 32 is electrically connected to each row-direction wiring 31.
  • the switching unit 102 in this example uses a transistor 101.
  • the switching unit 102 may be provided at each intersection of each row direction wiring 31 and each column direction wiring 32. In this case, each switching unit 102 selects whether the corresponding row direction wiring 31 and column direction wiring 32 are electrically connected.
  • an arbitrary input wiring 51 and an output wiring 52 can be connected between arbitrary circuit blocks 20.
  • the output wiring 52-a of the circuit block 20-1 is connected to the input wiring 51-b of the circuit block 20-4 will be described.
  • the state of each switching unit 102 is controlled so that the output wiring 52-a and the input wiring 51-b are connected to the corresponding wiring.
  • the corresponding wiring may be a combination of the row direction wiring 31 and the column direction wiring 32 electrically connected by the switching unit 102.
  • the switching unit 102-a in FIG. 2 is in the ON state
  • the row direction wiring 31a-4 and the column direction wiring 32b-4 electrically connected via the switching unit 102-a are connected to the corresponding wiring.
  • the corresponding wiring may be the same wiring.
  • the transistor 101 corresponding to the output wiring 52-a the transistor 101-a corresponding to the row direction wiring 31a-4 is turned on. Further, among the transistors 101 corresponding to the input wiring 51-b, the transistor 101-b corresponding to the column direction wiring 32b-4 is turned on. With such a configuration, the output wiring 52-a and the input wiring 51-b can be electrically connected. In this manner, by controlling the state of each transistor 101, it is possible to connect any input wiring 51 and output wiring 52 between any circuit blocks 20.
  • the input / output circuit 15 receives a signal to be processed in the programmable logic array 12 via the data input terminal 11 and supplies the signal to the programmable logic array 12.
  • the input / output circuit 15 may supply the signal to any one of the row direction wirings 31 or the column direction wirings 32. Which row direction wiring 31 or column direction wiring 32 the input / output circuit 15 supplies a signal corresponds to the plurality of row direction wirings 31 or the plurality of column direction wirings 32 with respect to the input terminal of the input / output circuit 15.
  • a plurality of transistors 101 provided may be selected.
  • the input / output circuit 15 receives the signal processed in the programmable logic array 12 and stores it in the cache memory 13.
  • the input / output circuit 15 may receive the signal from any one of the row direction wirings 31 or the column direction wirings 32. Which row direction wiring 31 or column direction wiring 32 the input / output circuit 15 supplies a signal to corresponds to the plurality of row direction wirings 31 or the plurality of column direction wirings 32 for the output terminal of the input / output circuit 15.
  • a plurality of transistors 101 provided may be selected.
  • the input terminal and output terminal of the input / output circuit 15 can be connected to an arbitrary circuit block 20 by controlling the on / off state of each transistor 101.
  • the programmable logic array 12 may include a plurality of input / output circuits 15. In this case, each transistor 101 may be controlled such that a terminal of each input / output circuit 15 is connected to a row direction wiring 31 or a column direction wiring 32 different from the other input / output circuits 15.
  • the programmable logic array 12 includes a large number of transistors 101.
  • the transistor 101 of this example does not need to be provided with a wiring for supplying a gate voltage. That is, in the programmable logic array 12, the ratio of the area occupied by the wiring can be reduced. For this reason, the circuit blocks 20 and the like can be formed with higher density.
  • FIG. 3 is a diagram illustrating a configuration example of the circuit connection unit 107.
  • the circuit connection unit 107 includes the plurality of transistors 101 for each of the input terminal In and the output terminal Out of the circuit block 20.
  • the plurality of transistors 101 are provided in one-to-one correspondence with the plurality of row direction wirings 31 or the plurality of column direction wirings 32 provided between the circuit blocks 20.
  • Each transistor 101 is provided between a corresponding terminal of the circuit block 20 and a corresponding row direction wiring 31 or column direction wiring 32, and selects whether or not to connect the terminal and the wiring. With such a structure, each terminal of the circuit block 20 can be selectively connected to an arbitrary wiring.
  • the wiring connection unit 108 may include a plurality of transistors 101 for each row-directional wiring 31 that passes through the wiring connection unit 108.
  • the plurality of transistors 101 are provided in one-to-one correspondence with the plurality of column-direction wirings 32 that pass through the wiring connection unit 108.
  • Each transistor 101 is provided between a corresponding row direction wiring 31 and a corresponding column direction wiring 32, and it may be selected whether or not these wirings are connected.
  • one transistor 101 is turned on in one circuit connection unit 107 or wiring connection unit 108, but in another example, a plurality of transistors 101 are connected in one circuit connection unit 107 or wiring connection unit 108.
  • the transistor 101 may be controlled to be on.
  • the logic of the value transmitted by the plurality of column-direction wirings 32 selected by the transistor 101 is input to the input terminal In.
  • the sum is entered.
  • the plurality of transistors 101 are set to the ON state in the circuit connection unit 107 corresponding to the output terminal Out
  • the logical value output from the output terminal Out is parallel to the plurality of row direction wirings 31 selected by the transistor 101. Given to.
  • FIG. 4 is a diagram illustrating a configuration example of the switching unit 102.
  • the switching unit 102 may be provided at each intersection of the column direction wiring 32 and the row direction wiring 31.
  • the upper column direction wiring 32 is the column direction wiring 32-u
  • the lower column direction wiring 32 is the column direction wiring 32-d
  • the right row direction wiring 31 is the row direction wiring with respect to the intersection of the wirings. 31-r
  • the left row direction wiring 31 will be described as a row direction wiring 31-l.
  • the switching unit 102 selects whether or not to electrically connect the column direction wirings 32-u, the column direction wirings 32-d, the row direction wirings 31-r, and the row direction wirings 31-l.
  • a transistor 101 is included.
  • the switching unit 102 is arranged between the column direction wiring 32-u and the column direction wiring 32-d, between the column direction wiring 32-u and the row direction wiring 31-l, and between the column direction wiring 32-u and the row direction.
  • Between the wiring 31-r, between the column-directional wiring 32-d and the row-directional wiring 31-r, between the column-directional wiring 32-d and the row-directional wiring 31-l, and between the row-directional wiring 31-r And the row direction wiring 31-l have transistors 101 respectively.
  • the switching unit 102 can connect any wiring.
  • the transistor 101 in the switching unit 102 may also be a transistor whose on / off state is switched according to the amount of charge accumulated in the floating electrode by the electron beam. Accordingly, since it is not necessary to provide a wiring for supplying a gate voltage to the transistor 101 in the switching unit 102, the ratio of the area occupied by the wiring in the programmable logic array 12 can be reduced.
  • FIG. 5 is a diagram showing another configuration example of the programmable logic array 12.
  • the programmable logic array 12 of this example further includes an individual connection unit 109 and an individual wiring 71 in addition to the configuration of the programmable logic array 12 described with reference to FIG.
  • the individual connection unit 109 electrically connects terminals of a predetermined circuit block 20 and other circuit blocks 20 using the individual wiring 71 without using the common connection wiring, the circuit connection unit 107, and the wiring connection unit 108. Connecting.
  • the individual connection unit 109 and the individual wiring 71 will be described using an example in which any input terminal of the circuit block 20-3 is connected to a predetermined output terminal of the circuit block 20-4.
  • the individual connection unit 109 selects any of the input wirings 51 of the circuit block 20-3 between the circuit block 20-3 and the circuit connection unit 107 corresponding to the input terminal of the circuit block 20-3.
  • the individual connection unit 109 may select one of the input wirings 51 using a plurality of transistors 101.
  • the individual connection unit 109 electrically connects the selected input wiring 51 to the individual wiring 71.
  • the individual wiring 71 converts the input wiring 51 selected by the individual connection unit 109 into a predetermined output wiring 52 between the circuit block 20-4 and the circuit connection unit 107 corresponding to the output terminal of the circuit block 20-4. Connect electrically. As a result, the predetermined circuit blocks 20 can be connected without using the row direction wiring 31 and the column direction wiring 32.
  • the row direction wiring 31 and the column direction wiring 32 are common connection wirings used in common by a plurality of circuit blocks 20, when a certain circuit block 20 uses a predetermined common connection wiring, the other circuit blocks 20 Connection wiring may not be used. For this reason, in order to increase the degree of freedom of connection between the circuit blocks 20, it is preferable to provide many common connection wirings in advance. However, if many common connection wirings are provided, an area where the circuit block 20 can be arranged becomes narrow.
  • the programmable logic array 12 of the present example is provided with the individual connection portions 109 and the individual wirings 71 between the circuit blocks 20 that are presumed to be relatively likely to be connected, for example. Thereby, since these circuit blocks 20 can be connected without using the common connection wiring, the degree of freedom of connection between the circuit blocks 20 can be ensured even if the number of common connection wirings is reduced.
  • FIG. 6 is a diagram illustrating a configuration example of the individual connection unit 109.
  • the individual connection unit 109 may include a plurality of transistors 101 that correspond one-to-one with the plurality of input wirings 51 in the predetermined circuit block 20. Each transistor 101 selects whether or not to electrically connect the corresponding input wiring 51 and a predetermined output wiring 52 in another circuit block 20 via the individual wiring 71. For example, each transistor 101 may be provided between the corresponding input wiring 51 and the individual wiring 71.
  • the transistor 101 in the individual connection unit 109 may also be a transistor whose on / off state is switched according to the amount of charge accumulated in the floating electrode by the electron beam. Accordingly, since it is not necessary to provide a wiring for supplying a gate voltage to the transistor 101 in the individual connection unit 109, the ratio of the area occupied by the wiring in the programmable logic array 12 can be reduced.
  • FIG. 7 is a diagram illustrating another configuration example of the circuit connection unit 107.
  • the circuit connection unit 107 connected to the input wiring 51 further includes a plurality of buffer circuits 81 and a plurality of input driver circuits 91 in addition to the configuration of the circuit connection unit 107 described with reference to FIG.
  • a plurality of buffer circuits 81 are provided for each input terminal In of the circuit block 20.
  • the buffer circuit 81 is provided between each transistor 101 and the corresponding column direction wiring 32, and transmits a signal received from the column direction wiring 32 to the transistor 101.
  • One input driver circuit 91 is provided for each input terminal In of the circuit block 20.
  • the input driver circuit 91 may be provided on the input wiring 51 between each transistor 101 and the input terminal In.
  • the input driver circuit 91 amplifies the signal output from the corresponding plurality of buffer circuits 81 and inputs the amplified signal to the circuit block 20.
  • Each transistor 101 is provided corresponding to a plurality of buffer circuits 81, and switches between outputting a signal to the corresponding buffer circuit 81 or setting the output of the corresponding buffer circuit 81 to a high impedance state.
  • any one of the plurality of transistors 101 corresponding to one input terminal In is turned on. Therefore, the number of driver circuits can be reduced by providing a common input driver circuit 91 for each input terminal as in this example, without providing a driver circuit for each transistor 101.
  • the circuit connection unit 107 connected to the output wiring 52 further includes a plurality of buffer circuits 81 and a plurality of output driver circuits 92 in addition to the configuration of the circuit connection unit 107 described with reference to FIG. Similar to the transistor 101, a plurality of buffer circuits 81 are provided for each output terminal Out of the circuit block 20.
  • the buffer circuit 81 transmits a signal received from the circuit block 20 via the output driver circuit 92 to the corresponding row direction wiring 31.
  • One output driver circuit 92 is provided for each output terminal Out of the circuit block 20.
  • the output driver circuit 92 may be provided on the output wiring 52 between each transistor 101 and the output terminal Out.
  • the output driver circuit 92 amplifies the signal received from the circuit block 20 and supplies the amplified signal to the plurality of buffer circuits 81.
  • the transistor 101 in the circuit connection unit 107 of this example may also be a transistor that is switched on / off according to the amount of charge accumulated in the floating electrode by the electron beam. Accordingly, since it is not necessary to provide a wiring for supplying a gate voltage to the transistor 101 in the circuit connection unit 107, the ratio of the area occupied by the wiring in the programmable logic array 12 can be reduced.
  • the transistor 101 of the programmable logic array 12 will be described with reference to a more specific configuration example.
  • FIG. 8 is a top view of the transistor 101.
  • FIG. 9 is a cross-sectional view taken along the line AA ′ in FIG.
  • the transistor 101 may be formed on the semiconductor substrate 110 by a predetermined semiconductor process, for example, and has P-type or N-type channel characteristics. Note that in the following description, the transistor 101 has N-type channel characteristics.
  • the transistor 101 is provided in a region partitioned by a plurality of isolation regions 115 formed of an insulating material such as silicon dioxide on the semiconductor substrate 110, and includes a source region 111, a drain region 113, a floating electrode 131, a via 151, And a guard ring 171.
  • the source region 111 and the drain region 113 are formed in the surface layer portion of the semiconductor substrate 110 so as to be separated from each other.
  • the source region 111 and the drain region 113 may be formed, for example, by implanting phosphorus ions from the upper surface of the polysilicon semiconductor substrate 110 to a predetermined depth.
  • the semiconductor substrate 110 may be a P-type substrate, while the source region 111 and the drain region 113 may be N-type regions.
  • the floating electrode 131 is provided to face the source region 111 and the drain region 113 with an insulating film 121 formed by laminating an insulating material such as silicon dioxide on the semiconductor substrate 110.
  • the floating electrode 131 may be provided between the source region 111 and the drain region 113 in the surface direction of the semiconductor substrate 110.
  • the insulating film 122 may be provided so as to cover the surface of the floating electrode 131.
  • the insulating film 123 formed on the insulating film 122 may be formed on the uppermost layer on the semiconductor substrate 110 on which the programmable logic array 12 is formed.
  • a pattern wiring or the like to be described later may be formed between the insulating film 122 and the insulating film 123.
  • the via 151 is formed of a conductive material, and is provided so as to penetrate from the surface of the insulating film 123 to the floating electrode 131.
  • an insulating film 122 and an insulating film 123 in which insulating materials are stacked are formed on the floating electrode 131, and the via 151 is provided through the insulating films 122 and 123, and one end thereof Is exposed on the surface of the insulating film 123.
  • One end of the via 151 is preferably exposed in the uppermost layer among the layers formed on the semiconductor substrate 110.
  • the pattern wiring 161 and the pattern wiring 162 are provided between the insulating film 122 and the insulating film 123.
  • the pattern wiring 161 electrically connects the source terminal 181 provided on the semiconductor substrate 110 and the source region 111.
  • the pattern wiring 162 electrically connects the drain terminal 182 provided on the semiconductor substrate 110 and the drain region 113.
  • the guard ring 171 is formed of, for example, a conductive metal material, and is provided so as to surround the via 151 on the surface of the insulating film 123.
  • the guard ring 171 is electrically connected to the guard terminal 184 connected to the reference potential via the pattern wiring 164.
  • the guard ring 171 is not limited to the form formed in the annular
  • the guard terminal 184 may be connected to the ground potential via the GND terminal of the programmable logic array 12, for example.
  • charges can be accumulated in the floating electrode 131 by irradiating the surface of the via 151 with an electron beam. That is, charge can be directly accumulated by an electron beam to the floating electrode 131 functioning as the gate electrode of the transistor 101 without using a wiring or the like, and the transistor 101 is controlled to be in an on state or an off state. Can do.
  • a user, a manufacturer, or the like may irradiate the floating electrode 131 of the transistor 101 to be controlled to the on state (or the off state) with an electron beam having a predetermined intensity for a predetermined time.
  • the programmable logic array 12 easily changes the circuit configuration of the programmable logic array 12 to a setting corresponding to the program data by irradiating each transistor 101 with an electron beam according to the program data. can do.
  • the via 151 when the via 151 is irradiated with an electron beam, a part of the electrons contained in the irradiated electron beam may be scattered around the via 151.
  • the conductive guard ring 171 is provided around the via 151 as described above, the scattered electrons are trapped by the guard ring 171. Therefore, in the transistor 101, for example, the scattered electrons are captured in the insulating film 123, whereby charge can be prevented from being accumulated in the insulating film 123 over time.
  • the charge accumulated in the floating electrode 131 of the transistor 101 can be erased by irradiating the floating electrode 131 with ultraviolet rays. That is, by irradiating the floating electrode of the transistor 101 for which stored data is to be erased with, for example, ultraviolet rays using an ultraviolet irradiation device or the like, the charges accumulated in the floating electrode 131 are discharged, thereby bringing the transistor 101 into an initial state. Can be reset to
  • the above erasing operation may be performed on the entire programmable logic array 12, that is, a plurality of transistors 101, or by using an ultraviolet laser, an ultraviolet lamp, a mask, or the like that can reduce the spot diameter to a minimum. This may be implemented for a specific transistor 101 by limiting the irradiation site.
  • the transistor 101 is irradiated with ultraviolet rays to the floating electrode 131 of the transistor 101. After the accumulated charge is discharged, the transistor 101 may be irradiated with an electron beam with a dose corresponding to new data to be written, and the charge corresponding to the data may be newly accumulated in the floating electrode 131.
  • FIG. 10 is a cross-sectional view illustrating another configuration example of the transistor 101.
  • the transistor 101 of this example has a through hole 191 formed by, for example, pattern etching instead of the via 151 in the transistor 101 described with reference to FIG.
  • the rest of the configuration is the same as that of the transistor 101 described above, and thus description thereof is omitted.
  • the transistor 101 of the transistor 101 since the transistor 101 of the transistor 101 includes the through hole 191, the floating electrode 131 can be irradiated with an electron beam through the through hole 191.
  • the transistor 101 described with reference to FIGS. 9 and 10 is provided with the via 151 or the through hole 191 above the floating electrode 131, so that the charge given by the electron beam irradiation can be reliably ensured by the floating electrode 131. It was set as the structure injected. However, for example, the thickness of the insulating film 122 and the insulating film 123 on the floating electrode 131 is set so that the electron beam tunnels through the insulating film 122 and the insulating film 123 when the floating electrode 131 is irradiated with the electron beam.
  • FIG. 11 is a cross-sectional view showing still another configuration example of the transistor 101.
  • the transistor 101 of this example includes a guard ring 172 instead of the guard ring 171 in the transistor 101 described with reference to FIG. Note that the configuration other than the guard ring 172 is the same as that of the transistor 101 described above, and thus description thereof is omitted.
  • the guard ring 172 is formed by, for example, pattern-etching the peripheral portion of the via 151 in the insulating film 123 and then depositing a conductive material in an etching groove formed by the etching.
  • 11 shows only a sectional view of the guard ring 172, the shape of the guard ring 172 at the peripheral edge of the via 151 may be the same as that of the guard ring 171 described above.
  • the guard ring can be prevented from being peeled off due to external contact with the programmable logic array 12 or the like.
  • FIG. 12 is a cross-sectional view showing still another configuration example of the transistor 101.
  • the insulating film 122 is provided so as to cover at least a part of the surface of the floating electrode 131 while covering the surface of the floating electrode 131.
  • a guard ring 171 is provided on the peripheral edge of the floating electrode 131 on the insulating film 122.
  • the package unit 200 is formed on the uppermost layer on the semiconductor substrate 110 so as to cover the upper surfaces of the pattern wirings 161 and 162, the guard ring 171, and the floating electrode 131 provided on the insulating film 122. It is formed.
  • each floating electrode 131 may be irradiated with an electron beam to a region not covered with the insulating film 122.
  • the package unit 200 may be provided so as to include the programmable logic array 12 after the electric charge corresponding to the program data is accumulated in the floating electrode 131.
  • an insulating resin material is preferably used for the package part 200.
  • the programmable logic array 12 shown in FIG. 12 may have a via that connects the upper surface of the package unit 200 and the floating electrode 131 of the transistor 101.
  • the charge corresponding to the new program data is written to the floating electrode 131 of the transistor 101 by irradiating the via with an electron beam. Can do.
  • the second package part may be provided so as to cover the via provided in the package part 200.
  • the second package part is preferably detachable. As a result, when new program data is written to the programmable logic array 12, the second package portion can be removed to expose the via.
  • each floating electrode 131 may be irradiated with an electron beam.
  • the floating electrode 131 may be provided so as to be able to irradiate an electron beam in the process.
  • the entire surface of the floating electrode 131 may be covered with an insulating film.
  • the step of irradiating the electron beam is preferably after the step using ultraviolet rays.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention porte sur un dispositif programmable dans lequel une relation logique de données logiques de sortie pour des données logiques d'entrée est changée conformément à des données de programme prédéterminées. Le dispositif programmable comprend une pluralité d'électrodes flottantes qui sont agencées de telle sorte qu'un faisceau d'électrons peut être appliqué aux électrodes, et accumule une charge pour stocker des données de programme lorsque le faisceau d'électrons est appliqué, et un réseau logique programmable dans lequel la relation logique des données logiques de sortie pour des données logiques d'entrée est changée conformément à la quantité de charge accumulée par les électrodes flottantes.
PCT/JP2008/002748 2008-09-30 2008-09-30 Dispositif programmable et procédé d'écriture de données WO2010038257A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2008/002748 WO2010038257A1 (fr) 2008-09-30 2008-09-30 Dispositif programmable et procédé d'écriture de données
JP2010531654A JPWO2010038257A1 (ja) 2008-09-30 2008-09-30 プログラマブルデバイス、およびデータ書込方法
TW098133035A TW201015857A (en) 2008-09-30 2009-09-29 Programmable device and data writing-in method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2011226689B2 (en) * 2010-03-11 2016-09-01 Kronos Bio, Inc. Imidazopyridines Syk inhibitors
JP2020010354A (ja) * 2014-01-17 2020-01-16 株式会社半導体エネルギー研究所 半導体装置

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPS59145576A (ja) * 1982-11-09 1984-08-21 ザイトレツクス・コ−ポレ−シヨン プログラム可能なｍｏｓトランジスタ
JPS61198499A (ja) * 1985-02-28 1986-09-02 Toshiba Corp 半導体メモリ素子の書込み方法
JPS6321868A (ja) * 1986-07-16 1988-01-29 Canon Inc メモリ方法
JPH08204543A (ja) * 1984-09-26 1996-08-09 Xilinx Inc 単一チップ形態適合可能論理アレイ

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Publication number Priority date Publication date Assignee Title
JPS59145576A (ja) * 1982-11-09 1984-08-21 ザイトレツクス・コ−ポレ−シヨン プログラム可能なｍｏｓトランジスタ
JPH08204543A (ja) * 1984-09-26 1996-08-09 Xilinx Inc 単一チップ形態適合可能論理アレイ
JPS61198499A (ja) * 1985-02-28 1986-09-02 Toshiba Corp 半導体メモリ素子の書込み方法
JPS6321868A (ja) * 1986-07-16 1988-01-29 Canon Inc メモリ方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2011226689B2 (en) * 2010-03-11 2016-09-01 Kronos Bio, Inc. Imidazopyridines Syk inhibitors
AU2016219585B2 (en) * 2010-03-11 2018-02-08 Kronos Bio, Inc. Imidazopyridines Syk inhibitors
US10092583B2 (en) 2010-03-11 2018-10-09 Gilead Connecticut, Inc. Imidazopyridines Syk inhibitors
US10842803B2 (en) 2010-03-11 2020-11-24 Kronos Bio, Inc. Imidazopyridines Syk inhibitors
JP2020010354A (ja) * 2014-01-17 2020-01-16 株式会社半導体エネルギー研究所 半導体装置

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