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WO2010058528A1 - 半導体層およびその形成方法 - Google Patents

半導体層およびその形成方法 Download PDF

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Publication number
WO2010058528A1
WO2010058528A1 PCT/JP2009/005824 JP2009005824W WO2010058528A1 WO 2010058528 A1 WO2010058528 A1 WO 2010058528A1 JP 2009005824 W JP2009005824 W JP 2009005824W WO 2010058528 A1 WO2010058528 A1 WO 2010058528A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor layer
etching
forming
layer according
semiconductor
Prior art date
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PCT/JP2009/005824
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English (en)
French (fr)
Japanese (ja)
Inventor
古川博章
Original Assignee
シャープ株式会社
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Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to BRPI0921984A priority Critical patent/BRPI0921984A2/pt
Priority to RU2011124916/28A priority patent/RU2011124916A/ru
Priority to CN2009801461110A priority patent/CN102217075A/zh
Priority to US13/130,141 priority patent/US8415673B2/en
Priority to JP2010539124A priority patent/JPWO2010058528A1/ja
Priority to EP09827309A priority patent/EP2357672A1/en
Publication of WO2010058528A1 publication Critical patent/WO2010058528A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Definitions

  • the present invention relates to a semiconductor layer and a method for forming the semiconductor layer.
  • the semiconductor layer can control the conductivity, and is used as an active layer of a thin film transistor (TFT).
  • TFT thin film transistor
  • the TFT is provided, for example, in an active matrix liquid crystal display device, and such a liquid crystal display device is used for a display of a television, a computer, a portable terminal, or the like.
  • the semiconductor layer is formed on the support substrate together with an insulating film, electrodes, wirings, and the like by a manufacturing technique similar to a semiconductor integrated circuit manufacturing technique such as thin film formation or photolithography.
  • a manufacturing technique similar to a semiconductor integrated circuit manufacturing technique such as thin film formation or photolithography.
  • a semiconductor layer is provided on an insulating surface, and a gate electrode is provided on the semiconductor layer via a gate insulating film.
  • Patent Document 1 describes that when the thickness of the gate insulating film is not uniform, an electric field is strongly formed at the edge portion of the semiconductor layer due to the fringe effect, a side current is generated, and the characteristics as a switching element are deteriorated. Has been. Also, the shorter the distance between the semiconductor edge and the gate electrode, the lower the absolute withstand voltage of the TFT due to the electric field concentration at the edge of the semiconductor wiring, and dielectric breakdown tends to occur. Therefore, Patent Document 1 discloses a configuration that suppresses a change in the thickness of the insulating film on the edge portion of the semiconductor film.
  • FIG. 8 shows a TFT 500 disclosed in Patent Document 1.
  • the TFT 500 includes a semiconductor layer 600, a gate insulating film 510 covering the semiconductor layer 600, a gate electrode 520 provided over the semiconductor layer 600 with the gate insulating film 510 interposed therebetween, and a source electrode 530 and a drain electrode in contact with the semiconductor layer 600. 540.
  • the semiconductor layer 600 has a tapered shape at an edge portion thereof, and fluctuations in the thickness of the gate insulating film 510 are suppressed, so that deterioration in characteristics as a switching element is suppressed.
  • Patent Document 1 describes a method for forming a semiconductor layer 600. Hereinafter, a method for forming the semiconductor layer 600 will be described with reference to FIG.
  • a semiconductor film S is deposited, and then a photoresist layer R is formed on the semiconductor film S.
  • the semiconductor film S is etched using the photoresist layer R as a mask.
  • FIG. 9B by etching, a portion of the semiconductor film S that is not covered with the photoresist layer R is removed to form an island-shaped semiconductor layer.
  • a part of the photoresist layer R is also removed from the side surface.
  • FIG. 9C after etching, the edge portion of the semiconductor layer 600 is tapered. Thereafter, by removing the photoresist layer R, a tapered semiconductor layer 600 is formed.
  • Patent Document 1 also discloses another TFT having a step-shaped semiconductor layer.
  • FIG. 10 shows a TFT 700 disclosed in Patent Document 1.
  • the TFT 700 includes a semiconductor layer 800, a gate insulating film 710 covering the semiconductor layer 800, a gate electrode 720 provided over the semiconductor layer 800 with the gate insulating film 710 interposed therebetween, and a source electrode 730 and a drain electrode in contact with the semiconductor layer 800. 740.
  • the semiconductor layer 800 has a step shape at the edge thereof, and the variation in the thickness of the gate insulating film 710 is suppressed, so that the deterioration of characteristics as a switching element is suppressed.
  • Patent Document 1 describes a method for forming a semiconductor layer 800. Hereinafter, a method for forming the semiconductor layer 800 will be described with reference to FIG.
  • a semiconductor film S is deposited, and then a photoresist layer R is formed on the semiconductor film S.
  • dry etching of the semiconductor film S is performed using the photoresist layer R as a mask.
  • the portion of the semiconductor film S that is not covered with the photoresist layer R is removed by etching to form an island-shaped semiconductor layer S ′. This etching is performed using a gas that removes the semiconductor film S but does not remove the photoresist layer R.
  • a part of the photoresist layer R is removed by ashing the photoresist layer R. Thereby, a part of the island-shaped semiconductor layer S ′ is exposed. Ashing is performed after the gas in the apparatus is changed to a gas that removes the photoresist layer R but does not remove the island-like semiconductor layer S ′.
  • the island-shaped semiconductor layer S ′ is etched using the ashed photoresist layer R as a mask. After this etching, the edge portion of the semiconductor layer 800 has a step shape. This etching is performed after the gas in the apparatus is changed to a gas that removes the semiconductor film S but does not remove the photoresist layer R.
  • the photoresist layer R is removed.
  • the semiconductor layer 800 having a step shape is formed.
  • FIG. 12A shows the semiconductor film S and the photoresist layer R before etching
  • FIG. 12B shows the semiconductor layer S ′ and the photoresist layer R after etching.
  • Patent Document 1 although the cross section along the normal direction of the substrate surface of the photoresist layer R is illustrated in a rectangular shape, in practice, the edge portion of the photoresist layer R is not necessarily vertical, It is inclined to some extent.
  • the width of the desired semiconductor layer S ′ is smaller than the width of the photoresist layer R before etching.
  • the difference between the photoresist layer R before etching and the desired width of the semiconductor layer S ′ is also referred to as etching shift.
  • the width of the photoresist layer R before etching is larger than the width of the desired semiconductor layer S ′. Therefore, it is difficult to form a plurality of semiconductor layers S ′ at short intervals.
  • the etching shift amount is large, the variation in the width of the semiconductor layer S ′ increases, and the variation in the characteristics of the TFT also increases.
  • the taper angle of the edge portion of the semiconductor layer S ′ becomes closer to the vertical. This will be described with reference to FIG.
  • the tapered shape of the edge portion of the semiconductor layer S ′ is affected by the shape of the photoresist layer R.
  • the inclination angle of the edge portion of the photoresist layer R is relatively small.
  • the corner is also relatively small, and a tapered shape is formed at the edge portion of the semiconductor layer S ′.
  • ashing is performed between two etchings, and it is necessary to change the gas in the apparatus according to the ashing and etching.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor layer suitable for miniaturization as well as suppression of dielectric breakdown and a simple formation method thereof.
  • the semiconductor layer according to the present invention is a semiconductor layer comprising an upper surface, a lower surface, and a side surface, and a tangent line in the vicinity of the boundary between the side surface and the upper surface is inclined with respect to the normal line of the lower surface
  • the angle between the tangent line at a certain part of the side surface that is away from the upper surface and the plane near the boundary is the plane defined by the lower surface, and the angle between the tangent at the boundary and the plane defined by the lower surface Bigger than.
  • an angle formed by a tangent of each portion of the side surface from the vicinity of the boundary with the upper surface of the semiconductor layer to the vicinity of the boundary with the lower surface with a plane defined by the lower surface is monotonously increased.
  • the side surface has a round shape.
  • the round shape has a radius of curvature of 20 nm or more.
  • the round shape has a radius of curvature substantially equal to the thickness of the semiconductor layer.
  • the round shape is located in an upper part of the side surface.
  • the round shape extends over 1/3 or more of the thickness of the semiconductor layer.
  • the side surface has an inclined plane.
  • the inclined plane extends over 1/3 or more of the thickness of the semiconductor layer.
  • the side surface further has a plane perpendicular to the lower surface.
  • the side surface further includes another inclined plane whose angle with respect to the lower surface is different from that of the inclined plane, and the angle formed between the inclined plane and the plane defined by the lower surface is the other plane. Is smaller than the angle formed by the inclined plane and the plane defined by the lower surface.
  • the semiconductor layer has a thickness of 30 nm to 80 nm.
  • a thin film transistor according to the present invention includes a substrate having an insulating surface, the semiconductor layer described above, a semiconductor layer provided on the insulating surface, a gate insulating film covering the semiconductor layer, and the gate insulation.
  • a method for forming a semiconductor layer according to the present invention includes a step of forming a semiconductor film, a step of forming a photoresist layer on the semiconductor film, and a step of performing a first etching, using the photoresist layer as a mask.
  • the etching rate of the photoresist layer is higher than the etching rate of the island-shaped semiconductor layer.
  • the etching rate of the semiconductor film is higher than the etching rate of the photoresist layer.
  • the time for performing the second etching is shorter than the time for performing the first etching.
  • the etching of the island-shaped semiconductor layer in the second etching is performed anisotropically.
  • a round shape or an inclined plane is formed at an edge portion of the island-shaped semiconductor layer.
  • the first etching includes dry etching using a mixed gas.
  • the second etching includes a step of making a mixing ratio of the mixed gas different from that of the first etching.
  • the mixed gas contains tetrafluoromethane and oxygen.
  • the step of performing the second etching includes a step of increasing the partial pressure ratio of oxygen more than the first etching.
  • a method of manufacturing a thin film transistor according to the present invention includes a step of preparing a substrate having an insulating surface, a step of forming a semiconductor layer on the insulating surface according to the formation method described above, and a gate covering the semiconductor layer.
  • FIG. 1 It is a schematic diagram which shows embodiment of the semiconductor layer by this invention.
  • FIG. 1 is a schematic diagram which shows the formation method of the semiconductor layer of this embodiment.
  • FIG. 1 is typical sectional drawing of embodiment of TFT by this invention,
  • (b) is another typical sectional drawing of TFT.
  • (A)-(e) is a schematic diagram which shows the manufacturing method of TFT of this embodiment.
  • (A) is the graph which shows the withstand voltage of TFT of a comparative example and TFT of this embodiment, (b),
  • (c) is a photograph which shows the semiconductor layer of a comparative example,
  • (d) is this implementation. It is a photograph which shows the semiconductor layer of a form.
  • FIGS. 9A to 9C are schematic views showing a method for forming a semiconductor layer included in the TFT shown in FIG. It is a schematic diagram which shows another conventional TFT.
  • FIG. (A) to (e) are schematic views showing a method for forming a semiconductor layer included in the TFT shown in FIG. (A)
  • (b) is a schematic diagram which shows the relationship between the semiconductor film and photoresist layer before an etching, and the semiconductor layer of the desired width after an etching.
  • (A)-(c) is a schematic diagram which shows the photoresist layer and corresponding semiconductor layer from which width differs.
  • the semiconductor layer 100 of the present embodiment has an upper surface 100o, a lower surface 100u, and a side surface 100s, and the side surface 100s is continuous with an end portion of the upper surface 100o and an end portion of the lower surface 100u.
  • the thickness t of the semiconductor layer 100 is 30 nm to 80 nm, preferably 40 nm to 60 nm.
  • the thickness t of the semiconductor layer 100 is 50 nm.
  • the side surface 100s of the semiconductor layer 100 is provided with a round shape 100r, and the side surface 100s has a portion provided with the round shape 100r and a plane perpendicular to the lower surface 100u.
  • the round shape 100r is located above the side surface 100s.
  • the cross section of the round shape 100r ideally corresponds to a part of a circle, and the radius of curvature r is 20 nm.
  • the width of the semiconductor layer 100 is 3 ⁇ m.
  • the thickness t of the semiconductor layer 100 is larger than the radius of curvature r, and the center of curvature of the round shape 100 r is in the semiconductor layer 100.
  • the semiconductor layer 100 is schematically shown, and the upper surface 100o and the lower surface 100u are planes parallel to each other.
  • the tangent line in the vicinity of the boundary with the upper surface 100o of the side surface 100s is examined.
  • the tangent on the boundary line is parallel to the lower surface 100u and they do not intersect, but the tangent in the vicinity of the boundary intersects the plane defined by the lower surface 100u at a small angle.
  • a straight line T1 indicates this tangent line.
  • the tangent line T1 is neither parallel nor orthogonal to the normal line of the lower surface 100u, but intersects the normal line of the lower surface 100u at an angle smaller than 90 °.
  • the tangent line T1 does not intersect the lower surface 100u, but intersects a portion other than the lower surface 100u in the plane defined by the lower surface 100u.
  • the angle formed with the plane defined by is very small.
  • a conductive member eg, a gate electrode
  • dielectric breakdown can be suppressed even if the insulating layer is thin.
  • the tangent line of the side surface 100s is parallel to the normal line of the lower surface 100u, and the angle formed by the tangent line with respect to the lower surface 100u is 90 °.
  • a straight line T2 indicates this tangent line.
  • the tangent line T1 described above does not intersect with the lower surface 100u, but intersects with a portion other than the lower surface 100u in the plane defined by the lower surface 100u, whereas the tangent line T2 intersects with the edge portion of the lower surface 100u. ing.
  • the tangent lines T1 and T2 of the side surface 100s intersect the plane defined by the lower surface 100u at different angles.
  • the angle formed between the tangent line T2 and the lower surface 100u is the plane of the tangent line T1 and the lower surface 100u. Is larger than the angle between For this reason, although the inclination in the vicinity of the boundary between the upper surface 100o and the side surface 100s is relatively large, the edge of the upper surface 100o of the semiconductor layer 100 when viewed from the normal direction of the upper surface 100o and the lower surface 100u of the semiconductor layer 100 The distance between the portion and the end of the lower surface 100u can be shortened, and the etching shift can be suppressed as will be described later.
  • the side surface 100s has a portion provided with a round shape 100r and a plane perpendicular to the lower surface 100u.
  • an angle formed between a tangent line of each portion from the upper surface 100o to the lower surface 100u of the semiconductor layer 100 along the side surface 100s and a plane defined by the lower surface 100u is considered.
  • the angle corresponding to the vicinity of the boundary is extremely small, but the angle increases as it proceeds through the round shape 100r, and the angle is 90 ° corresponding to the lower end of the round shape, and then the angle is 90 corresponding to the vertical plane. ° Maintain.
  • the angle corresponding to each part from the upper surface 100o to the lower surface 100u of the semiconductor layer 100 along the side surface 100s shows a monotonous increase.
  • the tangent line T1 near the boundary between the side surface 100s and the upper surface 100o is inclined with respect to the normal line of the lower surface 100u, and the angle formed between the tangent line T2 and the lower surface 100u is the tangent line T1 and the lower surface 100u. It is larger than the angle formed with the plane. For this reason, when a plane virtually including the end portion of the upper surface 100o and the end portion of the lower surface 100u (this plane is referred to as “virtual plane”) is considered, the side surface 100s protrudes from the virtual plane.
  • a semiconductor film S is deposited.
  • the semiconductor film S contains, for example, a silicon material.
  • the semiconductor film S may be crystallized by a low temperature polycrystal silicon (LPS) method or a continuous grain silicon (CGS) method.
  • LPS low temperature polycrystal silicon
  • CGS continuous grain silicon
  • the amorphous silicon may be used as it is without being crystallized.
  • a photoresist layer R containing a photoresist material is formed.
  • a novolac resist material may be used as the photoresist material, or a chemically amplified photoresist material may be used.
  • the photoresist layer R is formed by applying a photoresist film so as to cover the semiconductor film S and then exposing a predetermined pattern.
  • the photoresist layer R is selectively provided on the semiconductor film S. A part of the semiconductor film S is covered with the photoresist layer R, and another part of the semiconductor film S is covered with the photoresist layer R. Not.
  • the first etching is performed using the photoresist layer R.
  • the etching rate of the semiconductor film S is higher than the etching rate of the photoresist layer R.
  • the etching rate of the photoresist layer R is zero.
  • the etching is dry etching, and this etching is performed in a reactive ion etching apparatus.
  • a mixed gas of CF 4 and O 2 is used as an etching gas, and the partial pressure ratio of CF 4 and O 2 is 9: 1.
  • the partial pressure of CF 4 and O 2 is 900 sccm: 100 sccm.
  • the time for performing the first etching is, for example, 60 seconds.
  • the etching rate of the photoresist layer R is low, whereas the etching rate of the semiconductor film S is high. Further, this etching is anisotropically performed at a high etching rate in a direction perpendicular to the surface of the semiconductor film S. Therefore, the photoresist layer R is hardly removed, the portion of the semiconductor film S that is not covered by the photoresist layer R is removed, and the portion that is covered by the photoresist layer R is the island-shaped semiconductor layer S. Remain as'. In this case, in the first etching, the etching shift amount is small, and the side surface of the island-shaped semiconductor layer S ′ is substantially vertical.
  • second etching is performed using the photoresist layer R as a mask.
  • the etching rate of the photoresist layer R is higher than the etching rate of the semiconductor layer S ′.
  • the etching rate of the semiconductor layer S ′ is not zero.
  • the selectivity of the second etching is lower than the selectivity of the first etching.
  • the ratio of the etching rate of the semiconductor material to the etching rate of the photoresist material in the second etching is the first etching rate. Less than the ratio of the etching rate of the semiconductor material to the etching rate of the photoresist material in the etching.
  • the time for performing the second etching is shorter than that for the first etching.
  • the time for which the second etching is performed is, for example, 20 seconds.
  • the second etching similarly to the first etching, a mixed gas of CF 4 and O 2 is used as an etching gas.
  • the second etching is performed in a state where the partial pressure ratio of O 2 is increased as compared with the first etching.
  • the partial pressure ratio of CF 4 and O 2 is changed to 6: 4.
  • the partial pressure of CF 4 and O 2 is 600 sccm: 400 sccm.
  • the etching rate of the semiconductor film S and the semiconductor layer S ′ and the etching rate of the photoresist layer R are changed by changing the partial pressure ratio of CF 4 and O 2 so that the ratio of O 2 increases. Can do.
  • the etching may be temporarily stopped, the partial pressure ratio may be changed, and the second etching may be started.
  • the O 2 partial pressure ratio may be increased step by step, or the O 2 partial pressure ratio may be continuously increased as time elapses.
  • the etching rate of the photoresist layer R is high, a part of the edge portion of the photoresist layer R is removed and the edge portion of the island-shaped semiconductor layer S ′ is exposed. Further, even in the second etching, the etching of the semiconductor layer S ′ is anisotropically performed at a high etching rate in a direction perpendicular to the surface of the semiconductor layer S ′, and among the exposed edge portions of the island-shaped semiconductor layer S ′. The upper surface portion is removed. As described above, the edge portion of the island-shaped semiconductor layer S ′ is etched and rounded, and as a result, the semiconductor layer 100 having the round shape 100r is formed.
  • the photoresist layer R is removed. As described above, the semiconductor layer 100 having the round shape 100r is formed.
  • the etching shift in the first etching is small.
  • the etching rate of the photoresist layer R is relatively high in the second etching, since the time for performing the second etching is short, an etching shift hardly occurs in the second etching.
  • the etching shift of the semiconductor layer S ′ is mainly influenced by the first etching. As described above, the etching shift can be suppressed, whereby the miniaturization of the semiconductor layer can be easily realized. Further, the second etching can be performed with the same apparatus as the first etching, and it is not necessary to move the support substrate.
  • the semiconductor layer 100 can be easily formed without increasing the number of substantial manufacturing steps except for changing the ratio of the mixed gas. Furthermore, the island-shaped semiconductor layer S ′ and the photoresist layer R are simultaneously removed in the second etching, so that the processing steps and processing time can be shortened.
  • the semiconductor layer 100 of this embodiment is used as an active layer of a TFT, for example.
  • FIG. 3A shows a schematic cross-sectional view of the TFT 200 of this embodiment
  • FIG. 3B shows another cross-sectional view of the TFT 200.
  • the TFT 200 includes a semiconductor layer 100, a gate insulating film 210, a gate electrode 220, a source electrode 230, and a drain electrode 240.
  • the TFT 200 has a top gate structure.
  • the thickness of the gate insulating film 210 is, for example, 100 nm.
  • the semiconductor layer 100 has a round shape 100r.
  • the semiconductor layer 100 has a source region 112, a drain region 114, and a channel region 116 located therebetween.
  • the channel region 116 is opposed to the gate electrode 220 with the gate insulating film 210 interposed therebetween. Further, impurities are added to the source region 112 and the drain region 114 of the semiconductor layer 100, and the carrier mobility of the source region 112 and the drain region 114 may be higher than that of the channel region 116.
  • the gate electrode 220 is covered with an interlayer insulating film 250.
  • the source electrode 230 and the drain electrode 240 are electrically connected to the source region 112 and the drain region 114 of the semiconductor layer 100 through contact holes formed in the gate insulating film 210 and the interlayer insulating film 250, respectively.
  • the semiconductor layer 100 has a round shape 100r, and the dielectric breakdown is suppressed. For this reason, the semiconductor layer 100 can make the gate insulating film 210 thin, and as a result, the threshold voltage of the gate voltage can be lowered, thereby reducing power consumption and achieving high-speed operation.
  • the semiconductor layer 100 has a round shape 100r. As a result, it is possible to realize a reduction in the threshold voltage of the gate voltage while suppressing variations.
  • the round shape 100r of the semiconductor layer 100 can be observed using a scanning electron microscope or the like after the TFT 200 is broken.
  • a method for forming the TFT 200 will be described with reference to FIG.
  • a semiconductor layer 100 having a round shape 100r is formed.
  • the semiconductor layer 100 is formed as described above with reference to FIG.
  • a gate insulating film 210 that covers the semiconductor layer 100 is formed.
  • the gate insulating film 210 is made of, for example, SiO 2 or SiN.
  • the gate insulating film 210 may have a stacked structure of SiN / SiO 2 .
  • the semiconductor layer 100 has the round shape 100r, and the coverage of the gate insulating film 210 is good.
  • a gate electrode 220 is formed on the gate insulating film 210.
  • the gate electrode 220 is made of, for example, Mo or MoW.
  • the gate electrode 220 may have a laminated structure of W / TaN or Ti / Al.
  • an interlayer insulating film 250 that covers the gate insulating film 210 and the gate electrode 220 is formed, and then the gate insulating film 210 and the interlayer insulating film 250 are etched to form contact holes. Then, a part of the semiconductor layer 100 is exposed. Thereafter, impurities are introduced into the semiconductor layer 100 as necessary.
  • the source electrode 230 and the drain electrode 240 in contact with the semiconductor layer 100 are formed.
  • the source electrode 230 and the drain electrode 240 have a laminated structure such as Ti / Al / Ti, Ti / Al, TiN / Al / TiN, Mo / Al—Nd / Mo, or Mo / Al / M.
  • the TFT 200 is formed as described above. Note that the semiconductor layer 100 has a round shape 100r, whereby the electric field concentration at the edge portion of the semiconductor layer 100 is alleviated and the dielectric breakdown can be suppressed.
  • the TFT of the comparative example is manufactured as follows. In the process of forming the semiconductor layer 100 of the TFT 200 , the partial pressures of CF 4 and O 2 were changed in the second etching after the first etching, but in the process of forming the semiconductor layer of the TFT of the comparative example, the CF 4 and O 2 The partial pressure ratio remains constant at 8: 2 (specifically, 800 sccm: 200 sccm) without being changed. In this case, the edge portion of the semiconductor layer has a tapered shape.
  • the TFT 200 of the present embodiment is manufactured in the same manner as described above with reference to FIGS.
  • those obtained by performing the second etching for 10 seconds and those performed for 20 seconds are prepared.
  • FIG. 5A shows the withstand voltage of the TFT of the comparative example and the TFT 200 of the present embodiment.
  • the design value of the width of the semiconductor layer is 2.0 ⁇ m.
  • the average breakdown voltage of the TFTs of the comparative example was 6 mV / cm or less.
  • the second etching is performed even for 10 seconds in the TFT 200 of this embodiment, the average withstand voltage of the TFT 200 increases to 7 mV / cm or more.
  • the average breakdown voltage of the TFT 200 increases to 8 mV / cm or more.
  • the time for performing the second etching when the time for performing the second etching is short, the variation in the breakdown voltage of the TFT 200 is small, but when the time for performing the second etching is long, the variation in the breakdown voltage of the TFT 200 is large. This is because if the time for performing the second etching is long, the variation in the etching shift amount and the variation in the width of the semiconductor layer increase.
  • FIG. 5B and 5C show electron micrographs showing the edge portion of the semiconductor layer 500 in the TFT of the comparative example, and FIG. 5D shows the semiconductor layer 100 in the TFT 200 of the present embodiment. The electron micrograph which copied the edge part is shown. The edge of the semiconductor layer is observed using a scanning electron microscope. 5B and 5C show the semiconductor layer formed under the same conditions, but the angle of the side surface with respect to the lower surface is slightly different due to the variation in etching.
  • the edge of the semiconductor layer 500 in the TFT of the comparative example is linear, whereas the edge of the semiconductor layer 100 has a round shape 100r. From the comparison between FIG. 5B, FIG. 5C, and FIG. 5D, it can be seen that when the second etching is performed for 10 seconds, a round shape is formed at the edge portion. Note that when observing with an electron microscope, the boundary surface of a substance may be difficult to see depending on the intensity of the electron beam repelling from the observed material. In this case, in order to emphasize the shape and configuration of the semiconductor layer, the boundary of the material may be lifted by dipping in hydrofluoric acid or the like. Thereby, the boundary of a semiconductor layer can be specified easily.
  • the radius of curvature in the round shape 100r is constant, but the present invention is not limited to this.
  • the radius of curvature in the round shape 100r may not be constant.
  • the curvature radius of the lower part of the round shape 100r may be 20 nm, and the curvature radius may continuously change to 30 nm as it goes to the upper part of the round shape 100r.
  • the round shape 100r is located above the side surface 100s of the semiconductor layer 100, but the present invention is not limited to this. As shown in FIG. 6A, the round shape 100r may be provided on the entire side surface 100s of the semiconductor layer 100a. In this case, it is preferable that the radius of curvature of the round shape 100r is substantially equal to the thickness of the semiconductor layer 100a. As described above, since the radius of curvature is equal to the thickness of the semiconductor layer, the curved surface of the semiconductor layer 100a does not have an angular portion, and thus electric field concentration is unlikely to occur. For example, the radius of curvature of the round shape 100r and the thickness of the semiconductor layer 100a are each 50 nm.
  • the semiconductor layer 100a is subjected to the first etching with a partial pressure ratio of CF 4 and O 2 of 9: 1 (specifically, 900 sccm: 100 sccm), and then the partial pressure ratio of CF 4 and O 2 is 6: After changing to 4 (specifically 600 sccm: 400 sccm), the second etching is performed.
  • the second etching is performed for a relatively long time, and the time of the second etching process is, for example, 30 seconds. By performing the second etching for a relatively long time in this way, the round shape 100r is provided on the entire side surface 100s of the semiconductor layer 100a.
  • the round shape 100r is located in the upper part of the side surface 100s, but the present invention is not limited to this.
  • an inclined plane 100m may be provided in the upper part of the side surface 100s of the semiconductor layer 100b, and a plane perpendicular to the lower surface 100u may be provided in the lower part.
  • the inclined plane 100m extends over approximately 3 or more of the thickness of the semiconductor layer 100b.
  • the thickness tc of the inclined plane 100m is 20 nm
  • the thickness of the semiconductor layer 100b is 50 nm.
  • the semiconductor layer 100b is formed after the side surface 100s of the semiconductor layer 100b is vertically processed by performing the first etching with a partial pressure ratio of CF 4 and O 2 of 9: 1 (specifically, 900 sccm: 100 sccm).
  • the second etching is performed by setting the partial pressure ratio to 5: 5 (specifically, 500 sccm: 500 sccm) and performing the second etching for a relatively short time (for example, 10 seconds).
  • FIG. 6C shows an edge cross section of the semiconductor layer 100b observed using a scanning electron microscope. The corners of the edge of the semiconductor layer 100b are partially processed.
  • the inclined plane 100m can be formed on the side surface 100s of the semiconductor layer 100b by relatively increasing the O 2 partial pressure ratio during the second etching.
  • the lower part of the side surface 100s is a plane perpendicular to the lower surface 100u, but the present invention is not limited to this.
  • the lower portion of the side surface 100s of the semiconductor layer 100c may be an inclined plane 100m2 inclined with respect to the lower surface 100u.
  • the thickness to of the upper inclined plane 100m1 is smaller than the thickness tu of the lower inclined plane 100m2, and the inclination angle ⁇ o of the upper inclined plane 100m1 with respect to the lower surface 100u is equal to that of the lower inclined plane 100m2 with respect to the lower surface 100u. It is preferable that the inclination angle is smaller than ⁇ u.
  • the thickness of the semiconductor layer 100c is 50 nm
  • the thickness to of the upper inclined plane 100m1 is 15 nm
  • the thickness tu of the lower inclined plane 100m2 is 35 nm.
  • the inclination angle ⁇ o is 30 °
  • the inclination angle ⁇ u is 80 °.
  • Such a semiconductor layer 100c is formed as follows.
  • the first etching step the ratio of oxygen gas is made relatively high, and the first etching is performed, for example, with the partial pressure ratio of CF 4 and O 2 being 8: 2 (specifically, 800 sccm: 200 sccm).
  • an inclined plane 100m2 is formed on the side surface 100s of the semiconductor layer.
  • the second etching step the second etching is performed with the partial pressure ratio of CF 4 and O 2 being 5: 5 (specifically, 500 sccm: 500 sccm), thereby inclining the upper portion of the side surface 100s of the semiconductor layer 100c.
  • a plane 100m1 is formed.
  • the side surface 100s of the semiconductor layer 100c has different inclined planes 100m1 and 100m2 in the upper part and the lower part.
  • the shape of the lower part is mainly affected by the first etching, and the shape of the upper part is affected by the second etching.
  • the first etching the smaller the width of the photoresist layer and / or the steeper the inclined plane of the photoresist layer, the inclined plane of the lower portion. Becomes steep. For example, when the width of the photoresist layer becomes 5 ⁇ m or less, the inclined plane starts to become steep, and when the width becomes 3 ⁇ m or less, the inclination angle of the semiconductor layer becomes 70 ° or more.
  • the inclination angle of the semiconductor layer can be 60 ° or less even if the width of the photoresist layer is less than 3 ⁇ m.
  • various shapes can be formed on the side surface 100s of the semiconductor layer 100 by adjusting the partial pressure ratio and the processing time of the two etchings.
  • TFT 200 is suitably used for a liquid crystal display device.
  • the configuration of the liquid crystal display device 300 having the TFT 200 will be described with reference to FIG.
  • FIG. 7A shows a schematic cross-sectional view of the liquid crystal display device 300 of the present embodiment.
  • the liquid crystal display device 300 includes an active matrix substrate 320, a counter substrate 340, and a liquid crystal layer 360 positioned between the active matrix substrate 320 and the counter substrate 340.
  • the active matrix substrate 320 has the TFT 200 described above.
  • FIG. 7B shows a schematic cross-sectional view of the active matrix substrate 320.
  • FIG. 7C shows another cross-sectional view of the active matrix substrate 320.
  • the active matrix substrate 320 includes an insulating substrate 322, a buffer film 324, a TFT 200 provided on the buffer film 324, an interlayer insulating film 326 provided on the gate electrode 220 of the TFT 200, a source electrode, a drain electrode, and an interlayer.
  • the insulating substrate 322 is a transparent glass substrate.
  • the buffer film 324 is made of SiO 2 / SiNO, SiO 2 .
  • the interlayer insulating film 326 is formed from SiO 2 or SiN. Alternatively, the interlayer insulating film 326 may have a laminated structure such as SiO 2 / SiN or SiO 2 / SiN / SiO 2 .
  • the protective film 328 is formed from an acrylic resin material.
  • the pixel electrode 330 is formed of a transparent conductive material such as ITO or ZnO.
  • the semiconductor layer 100 has the round shape 100r, the dielectric breakdown of the TFT 200 can be suppressed and the fine structure can be easily realized.
  • the round shape can also be formed by performing a thermal oxidation process on the semiconductor layer and removing the oxide film by HF wet etching as necessary.
  • the thermal oxidation treatment include laser thermal oxidation, low-temperature thermal oxidation after ion doping, and steam oxidation.
  • a heat treatment at a temperature higher than the softening point of the glass substrate is performed. Therefore, it is preferable to perform the rounding process by removing each of the semiconductor layer and the photoresist layer as described above without performing the thermal oxidation process.
  • the semiconductor layer 100 of the TFT 200 shown in FIGS. 7B and 7C is electrically connected to the pixel electrode 330, and such a TFT 200 is provided in the display region. Is not limited to this.
  • the TFT 200 may be provided in a frame area surrounding the display area. Alternatively, the TFT 200 may be provided in both the display area and the frame area.
  • the semiconductor layer 100 is used as the active layer of the TFT 200, but the present invention is not limited to this. Impurities may be introduced into the semiconductor layer 100 to improve the carrier mobility, and the semiconductor layer 100 may be used as a so-called wiring.
  • the semiconductor layer 100 provided in a region different from the region used as the active layer of the TFT in the deposited semiconductor film S may be used as the wiring.
  • a part of the semiconductor layer 100 may function as an active layer of the TFT 200 and another part may function as a wiring.
  • the semiconductor layer according to the present invention is suitable for miniaturization, and a TFT including this semiconductor layer can suppress dielectric breakdown.
  • a liquid crystal display device including such a TFT is suitably used for a mobile phone, a personal digital assistant (PDA), a game device, and the like.

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PCT/JP2009/005824 2008-11-20 2009-11-02 半導体層およびその形成方法 WO2010058528A1 (ja)

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BRPI0921984A BRPI0921984A2 (pt) 2008-11-20 2009-11-02 camada semicondutora e método para fabricar a mesma
RU2011124916/28A RU2011124916A (ru) 2008-11-20 2009-11-02 Полупроводниковый слой и способ его формирования
CN2009801461110A CN102217075A (zh) 2008-11-20 2009-11-02 半导体层及其形成方法
US13/130,141 US8415673B2 (en) 2008-11-20 2009-11-02 Thin film transistor and semiconductor layer
JP2010539124A JPWO2010058528A1 (ja) 2008-11-20 2009-11-02 半導体層およびその形成方法
EP09827309A EP2357672A1 (en) 2008-11-20 2009-11-02 Semiconductor layer and method for forming same

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US9166006B1 (en) * 2013-12-08 2015-10-20 Iman Rezanezhad Gatabi Methods to improve the performance of compound semiconductor devices and field effect transistors
TWI577031B (zh) * 2014-11-04 2017-04-01 群創光電股份有限公司 顯示裝置
KR20180123028A (ko) 2016-03-11 2018-11-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장비, 상기 반도체 장치의 제작 방법, 및 상기 반도체 장치를 포함하는 표시 장치

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US8415673B2 (en) 2013-04-09

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