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TWI685920B - 半導體結構及形成積體電路結構的方法 - Google Patents

半導體結構及形成積體電路結構的方法 Download PDF

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TWI685920B
TWI685920B TW108105334A TW108105334A TWI685920B TW I685920 B TWI685920 B TW I685920B TW 108105334 A TW108105334 A TW 108105334A TW 108105334 A TW108105334 A TW 108105334A TW I685920 B TWI685920 B TW I685920B
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gate
dielectric
layer
trench
dielectric material
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TW108105334A
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TW202004989A (zh
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林大鈞
許博欽
潘國華
廖忠志
林志勇
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台灣積體電路製造股份有限公司
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Abstract

一種半導體結構包含從半導體基板凸出的鰭式主動區域以及設置在鰭式主動區域上的閘極堆疊。閘極堆疊包含閘極介電層及設置在閘極介電層上的閘極。閘極介電層包含第一介電材料。半導體結構更包含設置在鰭式主動區域上的第二介電材料的介電閘極。閘極介電層從閘極的側壁延伸至介電閘極的側壁。第二介電材料與第一介電材料在組成上不相同。

Description

半導體結構及形成積體電路結構的方法
本揭露是有關於一種閘極結構及一種閘極結構的製造方法。
積體電路形成於半導體基板上，且包含配置且共同連接至功能性電路的各種裝置，如電晶體、二極體及/或電阻器。特定而言，積體電路更包含場效電晶體，如金屬氧化物半導體場效電晶體(MOSFET)或互補金屬氧化物半導體場效電晶體，其中各個場效電晶體包含用於控制對應場效電晶體之通道區域的閘極。當半導體裝置(如MOSFET)經由各種技術節點按比例縮小時，採用高介電常數的介電材料及金屬以形成閘極堆疊。然而，在用於形成n型金屬氧化物半導體(nMOS)電晶體及p型金屬氧化物半導體(pMOS)電晶體之金屬閘極堆疊的方法中，於整合製程及材料時可能出現各種問題。例如，當金屬閘極經由閘極替代來形成時，由於閘極介電層亦在側壁上形成，因此存在不足夠的線端製程窗，進而保留較少使用金屬或金屬合金填充的開口。此 外，金屬閘極堆疊的輪廓取決於閘極切割特徵及介電閘極的佈局。如此一來，便影響閾值電壓及飽和電流，並導致裝置性能的變化。因此，期望具有以增強電路性能來解決上述問題的新裝置結構以及其製造方法。
一種半導體結構，包含鰭式主動區域、閘極堆疊、以及第二介電材料的介電閘極。鰭式主動區域從半導體基板凸出。閘極堆疊設置在鰭式主動區域上，其中閘極堆疊包含閘極介電層及設置在閘極介電層上的閘極，且閘極介電層包含第一介電材料。第二介電材料的介電閘極設置在鰭式主動區域上，其中閘極介電層從閘極的側壁延伸至介電閘極的側壁，且第二介電材料與第一介電材料在組成上不相同。
一種半導體結構包含鰭式主動區域、閘極堆疊、以及第一介電材料的介電閘極。鰭式主動區域從半導體基板凸出。閘極堆疊設置在鰭式主動區域上，其中閘極堆疊包含閘極介電層及設置在閘極介電層上的閘極。第一介電材料的介電閘極設置在鰭式主動區域上，其中閘極介電層包含與第一介電材料在組成上不相同的第二介電材料，且閘極介電層設置在閘極的第一側壁上，且不在閘極的第二側壁上。
一種形成積體電路結構的方法包含在半導體基板上形成複數個鰭式主動區域；在鰭式主動區域上形成複數個虛設閘極堆疊；在虛設閘極堆疊之間的間隙中形成層間介電(ILD)層；移除虛設閘極堆疊以在層間介電層中形成第一 溝槽；沉積一第一介電材料的一閘極介電層，並在該閘極介電層上沉積一導電材料層，以填充該第一溝槽並以此形成一高介電常數的金屬閘極堆疊；執行第一圖案化製程於導電材料層以形成第二溝槽；使用與第一介電材料在組成上不相同的第二介電材料填充第二溝槽；執行第二圖案化製程於導電材料層以形成第三溝槽；使用與第一介電材料及第二介電材料在組成上不相同的第三介電材料填充第三溝槽。
100‧‧‧方法
102‧‧‧方塊
104‧‧‧操作
106‧‧‧操作
108‧‧‧操作
110‧‧‧操作
112‧‧‧操作
114‧‧‧操作
116‧‧‧操作
118‧‧‧操作
120‧‧‧操作
122‧‧‧操作
124‧‧‧操作
200‧‧‧半導體結構
202‧‧‧半導體基板、基板、半導體層
204‧‧‧淺溝槽隔離(STI)特徵
206‧‧‧鰭式主動區域、主動區域、鰭片結構
208‧‧‧虛設閘極堆疊、閘極堆疊
210‧‧‧硬遮罩、硬遮罩層、閘極間隔件
212‧‧‧層間介電層
214‧‧‧閘極溝槽
216‧‧‧閘極堆疊
218‧‧‧閘極介電層
220‧‧‧閘極
222‧‧‧硬遮罩
224‧‧‧開口
226‧‧‧閘極切割開口、溝槽
230‧‧‧閘極切割特徵、閘極切割介電特徵
232‧‧‧頂層、硬遮罩
234‧‧‧溝槽
236‧‧‧開口
238‧‧‧介電材料
240‧‧‧介電閘極
246‧‧‧開口
248‧‧‧符號
AA’‧‧‧線段
BB’‧‧‧線段
當結合隨附圖式閱讀時，自以下詳細描述將很好地理解本揭露之態樣。應當強調，根據工業中的標準實務，各個特徵並非按比例繪製。事實上，出於論述清晰之目的，可任意增加或減小各個特徵之尺寸。
第1圖繪示根據本揭露之一些實施方式在各種方面製造具有多鰭片結構的半導體結構之方法的流程圖。
第2圖繪示根據一些實施方式在製造階段的半導體結構的剖面圖。
第3A繪示根據一些實施方式在後續製造階段的第2圖之半導體結構的俯視圖。
第3B圖繪示根據一些實施方式沿第3A圖的虛線AA’之半導體結構的剖面圖。
第4A圖、第5A圖、第6A圖、第7A圖、第8A圖、第9A圖、第10A圖及第11A圖繪示根據一些實施方式在各種製造階段的半導體結構的俯視圖。
第4B圖、第5B圖、第6B圖、第7B圖、第8B圖、第9B圖、第10B圖及第11B圖繪示根據一些實施方式沿虛線AA’在相應製造階段的半導體結構的剖面圖。
第4C圖、第5C圖、第6C圖、第7C圖、第8C圖、第9C圖、第10C圖及第11C圖繪示根據一些實施方式沿虛線BB’在相應製造階段的半導體結構的剖面圖。
第12A圖及第13A圖繪示根據其他實施方式在各種製造階段的半導體結構的俯視圖。
第12B圖及第13B圖繪示根據其他實施方式沿虛線AA’在相應製造階段的半導體結構的剖面圖。
第12C圖及第13C圖繪示根據其他實施方式沿虛線BB’在相應製造階段的半導體結構的剖面圖。
第14圖繪示根據一些實施方式的半導體結構的俯視圖。
第15圖繪示根據其他實施方式的半導體結構的俯視圖。
第16圖繪示根據一些實施方式的半導體結構的俯視圖。
第17圖繪示根據其他實施方式的半導體結構的俯視圖。
應當理解，以下揭露提供了眾多不同的實施方式或實例，以用於實現各種實施方式的不同特徵。下文描述元件及排列之特定實例以簡化本揭露。當然，此等僅為實例 且並不意欲為限制性。此外，本揭露可在各個實例中重複元件符號及/或字母。此重複係出於簡便性及清晰的目的且本身並不指示所論述之各種實施方式及/或配置之間的關係。
另外，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」等)來描述諸圖中所繪示之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所繪示之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。例如，如果一個附圖中的裝置翻轉，則被描述為在其他元件的「下方」或「下面」的元件將被定向在其他元件的「上方」。因此，示例性術語「下方」可以包含下方和上方的取向，取決於附圖的特定取向。設備可經其他方式定向(旋轉90度或處於其他定向)且由此可類似解讀本文所使用之空間相對性描述詞。
本揭露提供了形成於半導體基板上的半導體結構之各種實施方式。半導體結構包含具有金屬閘極堆疊的各種裝置，例如場效電晶體(FETs)，此等金屬閘極堆疊具有高介電常數之介電材料的閘極介電層及金屬或金屬合金的閘極。半導體結構更包含介電閘極及與金屬閘極堆疊整合的閘極切割特徵。半導體結構藉由所揭露的方法形成，且具有增強的製程窗及改良的裝置性能。
第1圖繪示根據本揭露之一些實施方式在製造具有鰭型電晶體及金屬閘極堆疊的半導體結構之方法100的流程圖。第2圖至第17圖繪示在各種製造階段的半導體結 構200的俯視圖或剖面圖。半導體結構200及其製造方法100將參考第1圖至第17圖於下文共同描述。
參閱第2圖，方法100開始於方塊102中的提供半導體基板202。半導體基板202包含矽。在一些其他實施方式中，基板202包含鍺、鍺化矽或其他合適的半導體材料。基板202可替代地由一些其他合適的元素半導體，例如金剛石或鍺；合適的化合物半導體，例如碳化矽、砷化銦或磷化銦；或合適的合金半導體，例如碳化矽鍺、磷化鎵砷或磷化鎵銦來製成。
半導體基板202還包含各種摻雜區域，利如n阱區及p阱區。在一個實施方式中，半導體基板202包含磊晶(或epi)半導體層。在另一實施方式中，半導體基板202包含由適當技術，例如一種被視為佈植氧分離(SIMOX)的技術，以形成之用於隔離的嵌入介電材料層。在一些實施方式中，基板202可為絕緣層上半導體，例如絕緣層上矽(SOI)。
繼續參閱第2圖，藉由在半導體基板202上形成淺溝槽隔離(STI)特徵204，以持續進行至方法100中的操作104。在一些實施方式中，以蝕刻形成淺溝槽隔離特徵204以形成溝槽、使用介電材料填充溝槽並拋光以移除多餘的介電材料並平坦化頂面。穿過軟遮罩或硬遮罩的開口在半導體基板202上執行一或多個蝕刻製程，這些開口藉由微影圖案化及蝕刻來形成。下文將根據一些實施方式進一步描述淺溝槽隔離特徵204的形成。
在本實例中，硬遮罩在基板202上沉積並藉由微影製程圖案化。硬遮罩層包含介電質，例如半導體氧化物、半導體氮化物、半導體氮氧化物及/或半導體碳化物，且在示例性實施方式中，硬遮罩層包含氧化矽膜及氮化矽膜。硬遮罩層可藉由熱生長、原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDP-CVD)、或其他合適的沉積製程來形成。
用於界定鰭片結構的光阻層(或光阻)可在硬遮罩層上形成。示例性光阻層包含光敏材料，當暴露至光(例如紫外(UV)光、深紫外(DUV)光或遠紫外(EUV)光)時，此光敏材料導致層經歷性質改變。此性質改變可藉由所提及的顯影製程以選擇性地移除光阻層已暴露部分或未暴露部分。這種用於形成圖案化光阻層的程序更被稱為微影圖案化。
在一實施方式中，藉由微影製程圖案化光阻層以保留在半導體結構200上方設置之部分的光阻材料。在圖案化光阻之後，在半導體結構200上執行蝕刻製程以打開硬遮罩層，由此將圖案從光阻層轉移至硬遮罩層。剩餘的光阻層可在圖案化硬遮罩層之後移除。示例性微影製程包含旋轉塗覆光阻層、軟烘焙光阻層、遮罩對齊、暴露、暴露後烘焙、顯影光阻層、沖洗及乾燥(例如硬烘焙)。或者，微影製程可由其他方法(例如無遮罩光微影、電子束寫入及離子束寫入)實現、補充或替代。用於圖案化硬遮罩層的蝕刻製程可包含濕式蝕刻、乾式蝕刻或其組合。蝕刻製程可包含多個蝕刻步 驟。例如，硬遮罩層中的氧化矽膜可藉由稀釋的氟化氫溶液蝕刻，且硬遮罩層中的氮化矽膜可藉由磷酸溶液蝕刻。
隨後，執行蝕刻製程以蝕刻基板202未由圖案化之硬遮罩層覆蓋的部分。圖案化之硬遮罩層在蝕刻製程期間作為蝕刻遮罩以圖案化基板202。蝕刻製程可包含任何合適的蝕刻技術，例如乾式蝕刻、濕式蝕刻及/或其他蝕刻方法(例如反應性離子蝕刻(RIE))。在一些實施方式中，蝕刻製程包含使用不同蝕刻化學試劑的多個蝕刻步驟，這些蝕刻步驟經設計以蝕刻基板來形成具有特定溝槽輪廓的溝槽，用於改良元件性能及圖案密度。在一些實例中，基板的半導體材料可使用氟的蝕刻劑藉由乾式蝕刻製程來蝕刻。特定而言，控制應用於基板的蝕刻製程，以蝕刻部分的基板202。這可藉由控制蝕刻時間或藉由控制其他蝕刻參數來實現。在蝕刻製程之後，主動區域206已在基板102上被界定。
在溝槽中填充一或多種介電材料以形成淺溝槽隔離特徵204。合適的填充介電材料包含半導體氧化物、半導體氮化物、半導體氮氧化物、氟化矽玻璃(FSG)、低介電常數的介電材料及/或其組合。在各個示例性實施方式中，介電材料使用高密度電漿化學氣相沉積製程、亞大氣壓化學氣相沉積(SACVD)製程、高深寬比製程(HARP)、可流動化學氣相沉積(FCVD)及/或旋塗製程來沉積。
沉積介電材料後可執行化學機械拋光/平坦化(CMP)製程以移除多餘的介電材料並平坦化半導體結構的頂面。化學機械拋光/平坦化製程可使用硬遮罩層作為拋光 終止層來防止對半導體層202拋光。在此情況下，化學機械拋光/平坦化製程完全移除硬遮罩。硬遮罩可替代地藉由蝕刻製程來移除。儘管在進一步的實施方式中，硬遮罩層的一些部分在化學機械拋光/平坦化製程之後被保留。
參閱第3A圖及第3B圖，藉由形成具有多個鰭式主動區域(或鰭特徵)的鰭片結構206，以持續進行至方法100中的操作106。第3A圖及第3B圖分別繪示半導體結構200的俯視圖及沿虛線AA’的剖面圖。操作106包含使淺溝槽隔離特徵204凹陷，使得鰭式主動區域206從淺溝槽隔離特徵204之上凸出。凹陷製程採用一或多個蝕刻步驟(例如乾式蝕刻、濕式蝕刻或其組合)來選擇性回蝕淺溝槽隔離特徵204。例如，當淺溝槽隔離特徵204為氧化矽時，可使用氫氟酸的濕式蝕刻製程來蝕刻。示例性鰭式主動區域206在第一方向(X方向)上彼此間隔開。鰭式主動區域206具有長條形狀並且沿著第二方向(Y方向)定向，第二方向與X方向為正交。在替代實施方式中，鰭式主動區域206使用一或多個半導體材料(例如矽及鍺矽)透過磊晶生長形成。在其他實施方式中，鰭式主動區域206藉由蝕刻以使淺溝槽隔離特徵204凹陷以及在主動區域上選擇性磊晶生長半導體材料的組合來形成。
各種摻雜製程可在當前階段或在操作106之前應用至半導體區域以形成各種摻雜阱區，例如n阱區及p阱區。各種摻雜阱區可在半導體基板中藉由相應的離子佈植來形成。
參見第4A圖、第4B圖及第4C圖，藉由在鰭式主動區域206上形成虛設閘極堆疊208，以持續進行至方法100中的操作108。第4A圖為俯視圖；第4B圖為沿虛線AA’的剖面圖；且第4C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。出於簡便性而跳過一些特徵。舉例來說，基板102未在第4A圖至第4C圖中繪示；且淺溝槽隔離特徵204未在第4A圖中繪示。在本實施方式中，如第4C圖所示，閘極堆疊208包含五個示例性閘極堆疊。虛設閘極堆疊208具有長條形狀並在X方向上定向。虛設閘極堆疊208中的每一個虛設閘極堆疊設置在一或多個鰭式主動區域206上方。
每一個虛設閘極堆疊208均可包含閘極介電層及在閘極介電層上方的閘極。閘極介電層包含介電材料，例如氧化矽，且閘極包含導電材料，例如多晶矽。形成虛設閘極堆疊208包含沉積閘極材料(在本實方式中包含形成氧化矽及多晶矽)、以及藉由微影製程及蝕刻圖案化閘極材料。硬遮罩層210可在閘極材料上形成，且在形成虛設閘極堆疊期間作為蝕刻遮罩。硬遮罩層210可包含任何合適的材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽、其他合適的材料及/或其組合。在一實施方式中，硬遮罩層210包含多個鰭，例如氧化矽及氮化矽。在一些實施方式中，用於形成閘極堆疊的圖案化製程包含藉由微影製程形成圖案化之光阻層、使用圖案化之光阻層作為蝕刻遮罩來蝕刻硬遮罩層、以及使用 圖案化之硬遮罩層作為蝕刻遮罩來蝕刻閘極材料以形成閘極堆疊208。
一或多個閘極間隔件(未繪示出)在虛設閘極堆疊208的側壁上形成。閘極間隔件可用於使後續形成的源極/汲極特徵偏移，並且可用於設計或修改源極/汲極結構的輪廓。閘極間隔件可包含任何合適的介電材料，例如半導體氧化物、半導體氮化物、半導體碳化物、半導體氮氧化物、其他合適的介電材料及/或其組合。閘極間隔件210可具有多個膜，例如兩個膜(氧化矽膜及氮化矽膜)或三個膜(氧化矽膜、氮化矽膜、以及氧化矽膜)。形成閘極間隔件包含沉積及各向異性蝕刻，例如乾式蝕刻。
虛設閘極堆疊208經配置在鰭式主動區域上並用於各種場效電晶體(FET)，因此亦被視為鰭片場效電晶體(FinFETs)。這些虛設閘極堆疊208將在以後的製造階段由金屬閘極替代。場效電晶體包含整合在一起的n型電晶體及p型電晶體。在一些實例中，這些場效電晶體經配置以形成邏輯閘極，例如NOR邏輯閘極、NAND邏輯閘極；記憶體元件，例如一或多個靜態隨機存取記憶體(SRAM)單元；其他元件，例如I/O元件；或其組合。
藉由形成各個源極及汲極(未繪示出)至相應的鰭片場效電晶體，以持續進行至方法100中的操作110。源極及汲極可包含輕微摻雜的汲極(LDD)特徵及重度摻雜的源極及汲極(S/D)。例如，每個場效電晶體包含在相應的鰭式主動區域上形成並由對應的虛設閘極堆疊208插入的源 極及汲極。通道在對應的閘極堆疊之下的部分中的鰭式主動區域中形成，並且橫跨在源極與汲極之間。
凸起的源極/汲極可藉由選擇性磊晶生長來形成，以獲得具有增強的載子遷移率及元件性能的應變效應。虛設閘極堆疊208及閘極間隔件將源極/汲極限制至源極/汲極區域。在一些實施方式中，源極/汲極藉由一或多個磊晶製程來形成，此由矽特徵、矽化鍺特徵、碳化矽特徵及/或其他合適的特徵以結晶狀態在鰭式主動區域206上生長。或者，應用蝕刻製程以在磊晶生長之前使源極/汲極區域凹陷。合適的磊晶製程包含化學氣相沉積技術(例如氣相磊晶(VPE)及/或超高真空化學氣相沉積(UHV-CVD))、分子束磊晶及/或其他合適的製程。磊晶製程可使用氣相及/或液相前驅物，這些前驅物與鰭式主動區域206的組成相互作用。
源極及汲極可在磊晶製程期間藉由引入摻雜物質來原位摻雜，這些摻雜物質包含p型摻雜劑，例如硼或二氟化硼；n型摻雜劑，例如磷或砷；及/或包含其組合的其他合適的摻雜劑。若源極及汲極未經原位摻雜，則執行佈植製程(亦即接面佈植製程)以將對應的摻雜劑引入源極及汲極中。在示例性實施方式中，在n型場效電晶體中的源極及汲極包含碳化矽或由磷摻雜的矽，而在p型場效電晶體中的源極及汲極包含鍺或由硼摻雜的矽化鍺。在一些其他實施方式中，凸起的源極及汲極包含一個以上的半導體材料層。例如，矽化鍺層在源極及汲極區域內的基板上磊晶生長，且矽層在矽化鍺層上磊晶生長。隨後可執行一或多個退火製程以 激活源極及汲極。合適的退火製程包含快速熱退火(RTA)、雷射退火製程、其他合適的退火技術或其組合。
參見第5A圖、第5B圖及第5C圖，藉由在鰭式主動區域206及虛設閘極堆疊208上形成層間介電層212，以持續進行至方法100中的操作112。第5A圖為俯視圖；第5B圖為沿虛線AA’的剖面圖；且第5C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。
層間介電層212圍繞虛設閘極堆疊208，進而允許移除虛設閘極堆疊208並在所得空腔(亦被視為閘極溝槽)中形成替代閘極。層間介電層212還可為電性互連結構的一部分，此部分電性互連半導體結構200的各個元件。在這些實施方式中，層間介電層212作為支撐並隔離傳導性軌跡的絕緣體。層間介電層212可包含任何合適的介電材料，例如半導體氧化物、半導體氮化物、半導體氮氧化物、其他合適的介電材料或其組合。在一些實施方式中，形成層間介電層212包含沉積及化學機械拋光/平坦化以提供經平坦化之頂面。可在此階段移除硬遮罩210，例如藉由化學機械拋光/平坦化或額外的蝕刻製程來移除。
參見第6A圖、第6B圖及第6C圖，藉由移除虛設閘極堆疊208，進而在層間介電層212中得到閘極溝槽214，以持續進行至方法100中的操作114。第6A圖為俯視圖；第6B圖為沿虛線AA’的剖面圖；且第6C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。在一些實施方式中，閘極堆疊208藉由蝕刻製程(例如濕式蝕刻) 以選擇性移除閘極堆疊208。若存在更多材料，蝕刻製程可包含多個蝕刻步驟以移除虛設閘極。
參見第7A圖、第7B圖及第7C圖，藉由在閘極溝槽214中形成閘極堆疊(或閘)216，以持續進行至方法100中的操作116。第7A圖為俯視圖；第7B圖為沿虛線AA’的剖面圖；且第7C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。在操作116中，閘極堆疊216為使用高介電常數介電質及金屬形成，因此亦被視為高介電常數的金屬閘極堆疊216。閘極堆疊216在閘極溝槽214中藉由適當程序(例如包含沉積及化學機械拋光/平坦化的程序)形成。閘極材料(例如高介電常數介電材料及金屬)在閘極溝槽214中沉積，並實施化學機械拋光/平坦化製程以拋光並移除在層間介電層212的頂面之上之多餘的閘極材料。
閘極堆疊216在鰭式主動區域206的通道區域之上的基板202上形成。每個閘極堆疊216均包含閘極介電層218及設置在閘極介電層218上的閘極220。在本實施方式中，閘極介電層218包含高介電常數的介電材料，且閘極220包含金屬或金屬合金。在一些實例中，閘極介電層及閘極均可包含數個子層。高介電常數的介電材料可包含金屬氧化物、金屬氮化物，例如氧化鑭、氧化鋁、氧化鋯、氧化鈦、五氧化二鉭、氧化釔、鈦酸鍶(STO)、鈦酸鋇(BTO)、氧化鋇鋯、氧化氟鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、氧化(鋇鍶)鈦(BST)、三氧化二 鋁、或其他合適的介電材料，例如氮化矽，氮氧化物(SiON)。
在一些實施方式中，閘極介電層218為U型的，且在每個閘極溝槽的底面及側壁上形成。閘極介電層218還可包含夾在高介電常數的介電材料層與鰭式主動區域206之間的界面層。界面層可包含氧化矽、氮化矽、氮氧化矽及/或其他合適的材料。界面層藉由合適的方法(例如原子層沉積、化學氣相沉積、臭氧氧化等等)來沉積。高介電常數的介電層藉由合適的技術(例如原子層沉積、化學氣相沉積、金屬有機化學氣相沉積(MOCVD)、物理氣相沉積、熱氧化、其組合及/或其他合適的技術)在界面層(若界面層存在)上沉積。
閘極220可包含鈦、銀、鋁、氮化鈦鋁、碳化鉭、氮化鉭碳、氮化鉭矽、錳、鋯、氮化鈦、氮化鉭、釕、鉬、鋁、氮化鎢、銅、鎢或任何合適的導電材料。在一些實施方式中，不同的金屬材料用於具有相應之功函數的n型場效電晶體及p型場效電晶體元件。閘極220可包含多種導電材料。在一些實施方式中，閘極220包含覆蓋層、第一阻擋層、功函數金屬層、第二阻擋層及填充金屬層。在進一步的實施方式中，覆蓋層包含藉由如原子層沉積之適當的沉積技術形成的氮化鈦、氮化鉭、或其他合適的材料。第一及第二阻擋層中的每一個阻擋層包含藉由如原子層沉積之適當的沉積技術形成的氮化鈦、氮化鉭或其他合適的材料。在一些實例中，阻擋層可能不存在或僅有阻擋層中的一者存在於閘 極中。功函數金屬層包含具有適當之功函數的金屬或金屬合金的導電層，使得對應之場效電晶體的元件性能增強。對於p型場效電晶體及n型場效電晶體而言，功函數(WF)金屬層為不同的，分別被稱為n型功函數金屬及p型功函數金屬。功函數金屬的選擇取決於待在主動區域上形成的場效電晶體。例如，半導體結構200包含用於n型場效電晶體的第一主動區域及用於p型場效電晶體的第二主動區域，且n型功函數金屬及p型功函數金屬分別在對應的閘極堆疊中形成。特定而言，n型功函數金屬為具有第一功函數的金屬，使得相關之n型場效電晶體的閾值電壓減小。n型功函數金屬接近矽導電帶能(Ec)或較低功函數，近而呈現較容易的電子逃離。例如，n型功函數金屬具有約4.2eV或更小的功函數。p型功函數金屬為具有第二功函數的金屬，使得相關之p型場效電晶體的閾值電壓減小。p型功函數金屬接近矽價帶能(Ev)或較高功函數，進而呈現對核的強電子結合能。例如，p型功函數金屬具有約5.2eV或更高的功函數。在一些實施方式中，n型功函數金屬包含鉭(Ta)。在其他實施方式中，n型功函數金屬包含鋁化鈦(TiAl)、氮化鈦鋁(TiAlN)、或其組合。在其他實施方式中，n型金屬包含鉭、鋁化鈦、氮化鈦鋁、氮化鎢(WN)或其組合。n型功函數金屬可包含各種金屬的膜，作為用於優化裝置性能及處理相容性的堆疊。在一些實施方式中，p型功函數金屬包含氮化鈦(TiN)或氮化鉭(TaN)。在其他實施方式中，p型金屬包含氮化鈦、氮化鉭、氮化鎢(WN)、鋁化鈦(TiAl)、或其組合。 p型功函數金屬可包含各種金屬的膜，作為用於優化裝置性能及處理相容性的堆疊。功函數金屬藉由如物理氣相沉積之合適的技術來沉積。在各種實施方式中，填充金屬層包含鋁、鎢或其他合適的金屬。填充金屬層藉由如物理氣相沉積或濺鍍之合適的技術來沉積。
隨後，閘極切割特徵及介電閘極在基板上形成，如下文所描述。
參見第8A圖、第8B圖及第8C圖，藉由對閘極堆疊216執行閘極切割製程，以持續進行至方法100中的操作118。第8A圖為俯視圖；第8B圖為沿虛線AA’的剖面圖；且第8C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。出於製造考量，例如改良閘極堆疊216的圖案化品質及特性，因此形成具有長條幾何形狀的閘極堆疊216，並隨後根據積體電路設計的佈局將閘極堆疊216切割為片段。操作118包含藉由包含微影圖案化及蝕刻的程序來圖案化閘極堆疊216。在本實施方式中，操作118包含在具有開口224的基板202上形成圖案化之硬遮罩222，而開口224界定閘極堆疊216待切割的區域；並隨後使用硬遮罩222作為蝕刻遮罩穿過硬遮罩222的開口224以對閘極堆疊216執行蝕刻製程。操作118在閘極堆疊216中形成閘極切割開口226。硬遮罩222可使用任何合適的材料，例如氧化矽、氮化矽、氮氧化矽、其他合適的介電材料、或其組合。硬遮罩222的形成是藉由沉積硬遮罩，並藉由微影形成圖案化之光阻層，以及在圖案化之光阻層的開口內蝕刻硬遮罩。 應用於閘極堆疊216的蝕刻製程可包含使用分別對應於閘極材料之蝕刻劑的多個蝕刻步驟，且可包含濕式蝕刻、乾式蝕刻或其組合。
參見第9A圖、第9B圖及第9C圖，藉由將介電材料填充至閘極切割開口226中，以在閘極切割開口226中形成閘極切割介電特徵230，以持續進行至方法100中的操作120。第9A圖為俯視圖；第9B圖為沿虛線AA’的剖面圖；且第9C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。在本實施方式中，形成閘極切割特徵230包含沉積，且還可包含在沉積之後的化學機械拋光/平坦化製程。沉積製程可使用合適的沉積技術來沉積任何合適的介電材料，此沉積技術例如化學氣相沉積、可流動化學氣相沉積(FCVD)、高密度電漿化學氣相沉積(HDPCVD)、其他合適的技術或其組合。在形成閘極切割特徵230之後，所沉積的介電材料可包含保留在閘極堆疊216及閘極切割特徵230上的頂層232。此頂層232可作為用於後續製程的硬遮罩。在替代實施方式中，在化學機械拋光/平坦化製程之後，所沉積的介電材料經平坦化為與閘極堆疊216共平面；且隨後硬遮罩232在半導體結構200的頂面上沉積。
參見第10A圖、第10B圖及第10C圖，藉由移除部分的閘極堆疊216以形成溝槽234，以持續進行至方法100中的操作122。第10A圖為俯視圖；第10B圖為沿虛線AA’的剖面圖；且第10C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。在操作122中，部分的閘 極堆疊216經移除並將由介電閘極替代。操作122包含藉由微影製程及蝕刻來圖案化硬遮罩232，以形成具有開口236的圖案化之硬遮罩，以及蝕刻以移除閘極堆疊216在開口236中的部分，進而產生溝槽234。在第10C圖所繪示的一些實施方式中，操作122僅選擇性地移除閘極220在開口236內的材料，並在操作122之後使閘極介電層218保留在溝槽234內。隨後，可例如藉由蝕刻移除硬遮罩232。
參見第11A圖、第11B圖及第11C圖，藉由使用介電材料238填充溝槽234以形成介電閘極240，以持續進行至方法100中的操作124。第11A圖為俯視圖；第11B圖為沿虛線AA’的剖面圖；且第11C圖為根據一些實施方式的半導體結構200沿虛線BB’的部分剖面圖。在操作124中，形成介電閘極240以替代部分的閘極堆疊216。介電閘極240為用於提供隔離的介電特徵。操作124包含沉積，且還可包含化學機械拋光/平坦化製程。沉積可包含任何合適的沉積技術，例如化學氣相沉積、可流動化學氣相沉積、高密度電漿化學氣相沉積或其組合。出於各種考量，例如蝕刻選擇性，介電閘極240與閘極切割特徵230在組成上不相同。出於類似考量，例如蝕刻選擇性，閘極切割特徵230及介電閘極240均與閘極介電層218在組成上不相同。
如上文所提及，閘極介電層218包含高介電常數的介電材料，或以氧化矽的界面層及在界面層上之高介電常數的介電材料來替代。在一些實施方式中，閘極切割特徵230及介電閘極240中的每一者可包含氧化矽、氮化矽、氮 氧化矽或其組合，但具有不相同的組成。例如，閘極切割特徵230為氧化矽，且介電閘極240為氮化矽。閘極切割特徵230及介電閘極240可具有多層結構。例如，閘極切割特徵230包含氧化矽層及在氧化矽層上方的氮化矽層，而介電閘極240包含氮化矽層及在氮化矽層上方的氧化矽層。
如此一來，形成的半導體結構200具有一或多個介電閘極240，且介電閘極240的側壁上具有閘極介電層218，此於第11C圖中繪示，並於第14圖中進一步繪示。第14圖為根據一些實施方式之半導體結構200的部分俯視圖。僅繪示出鰭式主動區域及閘極結構。閘極介電層218在閘極220的側壁上形成，且亦在閘極切割特徵230的側壁及介電閘極240的側壁上形成。此外，在閘極220與閘極切割特徵230之間的界面不具有閘極介電層218，這導致閘極220尺寸的增加及元件性能的改良。在本實施方式中，在第14圖之中心位置的閘極220由閘極切割特徵230插入，閘極切割特徵230更由介電閘極240插入。這些均對齊以形成完全由閘極介電層218圍繞的連續結構。
在其他實施方式中，如第12A圖、第12B圖及第12C圖中所繪示，於操作122中移除溝槽234內的閘極介電層218及閘極220二者。如第13A圖、第13B圖及第13C圖所繪示，在操作124中，藉由使用介電材料238填充溝槽234後，介電閘極240形成。如此一來，形成的介電閘極240具有與第11C圖的介電閘極不同的結構。在第13C圖中，閘 極介電層218不存在於介電閘極240的外側壁上，且介電閘極240從外側壁直接接觸層間介電層212。
此外，若在操作118中，移除溝槽226內的閘極介電層218及閘極220二者，則閘極切割特徵230在外側壁上亦不具有閘極介電層218。如此一來，形成的半導體結構200於第15圖中進一步繪示。第15圖為根據一些實施方式的半導體結構200的部分俯視圖。僅繪示出鰭式主動區域及閘極結構。閘極介電層218在閘極220的側壁上形成，但介電閘極240及閘極切割特徵230在相應的外側壁上不具有閘極介電層218。此外，在閘極220與閘極切割特徵230之間的界面不具有閘極介電層218，這導致閘極220之尺寸的增加及元件性能的改良。在本實施方式中，在第15圖之中心位置的閘極220由閘極切割特徵230插入，其中閘極切割特徵230進一步由介電閘極240插入。這些均對齊以形成連續結構，且閘極220由相應之外側壁上的閘極介電層218保護。由此，與閘極220相比，閘極切割特徵230及介電閘極240沿著Y方向橫跨較大尺寸。
半導體結構200及其製造方法100於上文根據各種實施方式共同描述。變化及替代方案存在於本揭露之範疇內。例如，形成閘極切割特徵230及介電閘極240可具有不同順序。例如，形成介電閘極240並隨後形成閘極切割特徵230。然而，二者皆在形成閘極堆疊216之後形成。在此情況下，操作122及124在操作118及120之前但在操作114及116之後實施。在另一實施方中，閘極切割特徵230及介 電閘極240藉由共同程序同時形成，例如使用一個圖案化來界定介電閘極240及閘極切割特徵230的開口以降低製造成本。二者將於下文中進一步描述。
在第16圖所繪示的一個實施方式中，閘極切割特徵230藉由第一微影製程以具有開口224(例如第8A圖所繪示之操作118中的硬遮罩開口224)的遮罩圖案來形成，且介電閘極240藉由第二微影製程以具有開口236(例如第10A圖所繪示之操作122中的硬遮罩開口236)的遮罩圖案來形成。
在第17圖所繪示的替代實施方式中，閘極切割特徵及介電閘極共同由具有開口246的單個遮罩圖案來界定，且由單個微影製程來界定。因此，閘極切割特徵及介電閘極在包含微影圖案化、蝕刻及沉積的單個程序中同時形成。由此，閘極切割特徵及介電閘極包含相同組成且在第17圖中由符號248共同代指。
本揭露提供了根據各種實施方式的半導體結構200及其製造方法100。此方法在形成高介電常數的金屬閘極堆疊216之後形成閘極切割特徵230及介電閘極240。各種優點可存在於各種實施方式中。藉由使用所揭露的方法，使得在閘極220與閘極切割特徵230(或介電閘極240)之間的界面不具有閘極介電層218，這導致閘極220尺寸的增加及元件性能的改良。介電閘極240的形成及閘極切割特徵230的形成皆為具有較好對齊及改良之元件性能的自對齊製程。
因此，本揭露提供了根據一些實施方式的半導體結構。半導體結構包含從半導體基板凸出的鰭式主動區域及設置在鰭式主動區域上的閘極堆疊。閘極堆疊包含閘極介電層及設置在閘極介電層上的閘極。閘極介電層包含第一介電材料。半導體結構更包含設置在鰭式主動區域上的第二介電材料的介電閘極。閘極介電層從閘極的側壁延伸至介電閘極的側壁。第二介電材料與第一介電材料在組成上不相同。
在本揭露一實施方式中，更包含插入閘極與介電閘極之間的第三介電材料的閘極切割特徵，其中第三介電材料與第一介電材料及第二介電材料中的至少一者在組成上不相同。
在本揭露一實施方式中，閘極介電層設置在閘極切割特徵的側壁上。
在本揭露一實施方式中，閘極與閘極切割特徵之間的界面不具有閘極介電層。
在本揭露一實施方式中，閘極切割特徵與介電閘極及閘極大致對齊，且閘極切割特徵在第一端接觸閘極，且在與第一端相對的第二端接觸介電閘極。
閘極介電層是從閘極的側壁穿過閘極切割特徵的側壁並延伸至介電閘極的側壁的連續特徵。
閘極包含金屬，且閘極介電層包含高介電常數的介電材料。
本揭露提供了根據其他實施方式的半導體結構。半導體結構包含從半導體基板凸出的鰭式主動區域；設 置在鰭式主動區域上的閘極堆疊，其中閘極堆疊包含閘極介電層及設置在閘極介電層上的閘極；以及設置在鰭式主動區域上之第一介電材料的介電閘極。閘極介電層包含與第一介電材料在組成上不相同的第二介電材料。閘極介電層設置在閘極的第一側壁上且不在閘極的第二側壁上。
在本揭露一實施方式中，介電閘極的所有側壁具有閘極介電層。
在本揭露一實施方式中，更包含插入閘極與介電閘極之間的第三介電材料的閘極切割特徵，其中第三介電材料與第一介電材料及第二介電材料中的至少一者在組成上不相同。
在本揭露一實施方式中，閘極直接接觸閘極切割特徵。
在本揭露一實施方式中，閘極介電層包含高介電常數的介電材料，且閘極包含金屬。
在本揭露一實施方式中，第一介電材料包含二氧化矽，且第三介電材料包含氮化矽。
在本揭露一實施方式中，更包含形成於半導體基板上並接觸介電閘極的淺溝槽隔離(STI)特徵。
本揭露還提供了一種根據一些實施方式之形成積體電路結構的方法。此方法包含在半導體基板上形成複數個鰭式主動區域；在鰭式主動區域上形成複數個虛設閘極堆疊；在虛設閘極堆疊之間的間隙中形成層間介電(ILD)層；移除虛設閘極堆疊以在層間介電層中形成第一溝槽；沉積第 一介電材料的閘極介電層，並在閘極介電層上沉積導電材料層，以填充第一溝槽並以此形成高介電常數的金屬閘極堆疊；執行第一圖案化製程於導電材料層以形成第二溝槽；使用與第一介電材料在組成上不相同的第二介電材料填充第二溝槽；執行第二圖案化製程於導電材料層以形成第三溝槽；以及使用與第一介電材料及第二介電材料在組成上不相同的第三介電材料填充第三溝槽。
在本揭露一實施方式中，執行第一圖案化製程於導電材料層是在填充第一溝槽以形成高介電常數的金屬閘極堆疊之後實施。
在本揭露一實施方式中，沉積第一介電材料層的閘極介電層包含沉積高介電常數的介電材料層；沉積導電材料層包含沉積金屬及金屬合金中的一者。
在本揭露一實施方式中，沉積導電材料層更包含沉積覆蓋層；在覆蓋層上方沉積功函數金屬層；在功函數金屬層上方沉積散裝含金屬層，其中執行第一圖案化製程於導電材料層包含圖案化覆蓋層、功函數金屬層及散裝含金屬層，使得第一介電層在第二溝槽內暴露。
在本揭露一實施方式中，更包含在執行第一圖案化製程於導電材料層以形成第二溝槽之前，執行第一化學機械拋光(CMP)製程於閘極介電層及導電材料層；在使用第二介電材料填充第二溝槽之後，執行第二化學機械拋光製程於第二介電材料；在使用第三介電材料填充第三溝槽之後，執行第三化學機械拋光製程於第三介電材料。
在本揭露一實施方式中，執行第一圖案化製程於導電材料層以形成第二溝槽更包含蝕刻在第二溝槽內暴露的閘極介電層；執行第二圖案化製程於導電材料層以形成第三溝槽更包含蝕刻在第三溝槽內暴露的閘極介電層。
上文概括若干實施方式的特徵。熟習此項技術者應瞭解，可輕易使用本揭露作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施方式的相同目的及/或實現相同優點。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，且可在不脫離本揭露之精神及範疇的情況下產生本文的各種變化、替代及更改。
200‧‧‧半導體結構
206‧‧‧鰭式主動區域
218‧‧‧鰭式主動區域、主動區域、鰭片結構
220‧‧‧閘極
230‧‧‧閘極切割特徵、閘極切割介電特徵
240‧‧‧介電閘極

Claims (10)

  1. 一種半導體結構，包含：一鰭式主動區域，從一半導體基板凸出，並沿一第一方向延伸；一閘極堆疊，設置在該鰭式主動區域上，並沿一第二方向延伸，其中該閘極堆疊包含一閘極介電層及設置在該閘極介電層上的一閘極，且該閘極介電層包含一第一介電材料，且該第一方向與該第二方向實質上互相垂直；以及一第二介電材料的一介電閘極，設置在該鰭式主動區域上，並沿該第二方向相鄰於該閘極，其中該閘極介電層從該閘極的一側壁延伸至該介電閘極的一側壁，且該閘極及該介電閘極共同由該閘極介電層圍繞，且該第二介電材料與該第一介電材料在組成上不相同。
  2. 如請求項1所述之半導體結構，更包含插入該閘極與該介電閘極之間的一第三介電材料的一閘極切割特徵，其中該第三介電材料與該第一介電材料及該第二介電材料中的至少一者在組成上不相同。
  3. 如請求項2所述之半導體結構，其中該閘極介電層設置在該閘極切割特徵的一側壁上。
  4. 如請求項3所述之半導體結構，其中該閘極切割特徵與該介電閘極及該閘極大致對齊，且該閘極切 割特徵在一第一端接觸該閘極，且在與該第一端相對的一第二端接觸該介電閘極。
  5. 一種半導體結構，包含：一鰭式主動區域，從一半導體基板凸出；一閘極堆疊，設置在該鰭式主動區域上，其中該閘極堆疊包含一閘極介電層及設置在該閘極介電層上的一閘極；以及一第一介電材料的一介電閘極，設置在該鰭式主動區域上，其中該閘極介電層包含與該第一介電材料在組成上不相同的一第二介電材料，且該閘極介電層設置在該閘極的一第一側壁上，且不在該閘極的一第二側壁上。
  6. 如請求項5所述之半導體結構，其中該介電閘極的所有側壁具有該閘極介電層。
  7. 一種形成積體電路結構的方法，包含：在一半導體基板上形成複數個鰭式主動區域；在該些鰭式主動區域上形成複數個虛設閘極堆疊；在該些虛設閘極堆疊之間的間隙中形成一層間介電(ILD)層；移除該些虛設閘極堆疊以在該層間介電層中形成一第一溝槽； 沉積一第一介電材料的一閘極介電層，並在該閘極介電層上沉積一導電材料層，以填充該第一溝槽並以此形成一高介電常數的金屬閘極堆疊；執行一第一圖案化製程於該導電材料層以形成一第二溝槽；使用與該第一介電材料在組成上不相同的一第二介電材料填充該第二溝槽；執行一第二圖案化製程於該導電材料層以形成一第三溝槽；以及使用與該第一介電材料及該第二介電材料在組成上不相同的一第三介電材料填充該第三溝槽。
  8. 如請求項7所述之形成積體電路結構的方法，其中執行該第一圖案化製程於該導電材料層是在填充該第一溝槽以形成該高介電常數的金屬閘極堆疊之後實施。
  9. 如請求項7所述之形成積體電路結構的方法，更包含：在執行該第一圖案化製程於該導電材料層以形成該第二溝槽之前，執行一第一化學機械拋光(CMP)製程於該閘極介電層及該導電材料層；在使用該第二介電材料填充該第二溝槽之後，執行一第二化學機械拋光製程於該第二介電材料；以及 在使用該第三介電材料填充該第三溝槽之後，執行一第三化學機械拋光製程於該第三介電材料。
  10. 如請求項7所述之方法，其中執行該第一圖案化製程於該導電材料層以形成該第二溝槽更包含蝕刻在該第二溝槽內暴露的該閘極介電層；以及執行該第二圖案化製程於該導電材料層以形成該第三溝槽更包含蝕刻在該第三溝槽內暴露的該閘極介電層。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200227323A1 (en) * 2019-01-13 2020-07-16 Globalfoundries Inc. Isolation structures of finfet semiconductor devices
US11233139B2 (en) * 2020-06-26 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Fin field-effect transistor and method of forming the same
KR20220145195A (ko) 2021-04-21 2022-10-28 삼성전자주식회사 반도체 장치 및 그 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160336426A1 (en) * 2015-05-15 2016-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with unleveled gate structure and method for forming the same
TW201715602A (zh) * 2015-08-07 2017-05-01 東京威力科創股份有限公司 不具有虛擬閘極之圖案化方法
US20180102362A1 (en) * 2016-10-10 2018-04-12 International Business Machines Corporation Finfets with controllable and adjustable channel doping

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
JP6007880B2 (ja) 2013-10-10 2016-10-12 株式会社ダイフク 天井搬送車
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9236437B2 (en) * 2014-02-20 2016-01-12 Globalfoundries Inc. Method for creating self-aligned transistor contacts
US9324710B2 (en) * 2014-02-24 2016-04-26 International Business Machines Corporation Very planar gate cut post replacement gate process
US9064932B1 (en) * 2014-05-02 2015-06-23 Globalfoundries Inc. Methods of forming gate structures by a gate-cut-last process and the resulting structures
US9373641B2 (en) * 2014-08-19 2016-06-21 International Business Machines Corporation Methods of forming field effect transistors using a gate cut process following final gate formation
KR102217246B1 (ko) * 2014-11-12 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9412759B2 (en) * 2014-12-11 2016-08-09 Globalfoundries Inc. CMOS gate contact resistance reduction
KR102312346B1 (ko) * 2015-02-23 2021-10-14 삼성전자주식회사 반도체 소자 형성 방법
KR102245136B1 (ko) * 2015-02-24 2021-04-28 삼성전자 주식회사 반도체 소자 형성 방법
KR102449901B1 (ko) * 2015-06-23 2022-09-30 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9853112B2 (en) * 2015-07-17 2017-12-26 Qualcomm Incorporated Device and method to connect gate regions separated using a gate cut
US9583600B1 (en) * 2015-10-08 2017-02-28 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US9793406B2 (en) * 2015-10-28 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US9601567B1 (en) * 2015-10-30 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple Fin FET structures having an insulating separation plug
US9659930B1 (en) * 2015-11-04 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US20170148682A1 (en) * 2015-11-19 2017-05-25 International Business Machines Corporation Finfet with post-rmg gate cut
KR102497251B1 (ko) * 2015-12-29 2023-02-08 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102514620B1 (ko) * 2016-04-28 2023-03-29 삼성전자주식회사 반도체 소자 및 이의 제조 방법
CN109417094B (zh) * 2016-07-01 2022-10-21 英特尔公司 自-对准栅极边缘三栅极和finFET器件
US9899397B1 (en) * 2016-08-19 2018-02-20 International Business Machines Corporation Integration of floating gate memory and logic device in replacement gate flow
US10083961B2 (en) * 2016-09-07 2018-09-25 International Business Machines Corporation Gate cut with integrated etch stop layer
US10008601B2 (en) * 2016-10-17 2018-06-26 International Business Machines Corporation Self-aligned gate cut with polysilicon liner oxidation
WO2018075072A1 (en) * 2016-10-21 2018-04-26 Intel Corporation Fin-based thin film resistor
KR102495093B1 (ko) * 2016-11-14 2023-02-01 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9929157B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Tall single-fin fin-type field effect transistor structures and methods
US10079289B2 (en) * 2016-12-22 2018-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate structure and methods thereof
US9929048B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Middle of the line (MOL) contacts with two-dimensional self-alignment
US10622352B2 (en) * 2017-01-25 2020-04-14 International Business Machines Corporation Fin cut to prevent replacement gate collapse on STI
US10177041B2 (en) * 2017-03-10 2019-01-08 Globalfoundries Inc. Fin-type field effect transistors (FINFETS) with replacement metal gates and methods
KR102314134B1 (ko) * 2017-03-10 2021-10-18 삼성전자 주식회사 집적회로 소자 및 그 제조 방법
US10083874B1 (en) * 2017-03-23 2018-09-25 Globalfoundries Inc. Gate cut method
US10217839B2 (en) * 2017-03-24 2019-02-26 Globalfoundries Inc. Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET
US10176995B1 (en) * 2017-08-09 2019-01-08 Globalfoundries Inc. Methods, apparatus and system for gate cut process using a stress material in a finFET device
KR102372892B1 (ko) * 2017-08-10 2022-03-10 삼성전자주식회사 집적회로 소자의 제조 방법
US20190067115A1 (en) * 2017-08-23 2019-02-28 Globalfoundries Inc. Gate cut method for replacement metal gate
US10403714B2 (en) * 2017-08-29 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fill fins for semiconductor devices
US10535654B2 (en) * 2017-08-30 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Cut metal gate with slanted sidewalls
US10490458B2 (en) * 2017-09-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of cutting metal gates and structures formed thereof
US10483369B2 (en) * 2017-10-30 2019-11-19 Globalfoundries Inc. Methods of forming replacement gate structures on transistor devices
US20190139830A1 (en) * 2017-11-03 2019-05-09 Globalfoundries Inc. Self-aligned gate isolation
US10522344B2 (en) * 2017-11-06 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits with doped gate dielectrics
US10403548B2 (en) * 2017-11-14 2019-09-03 Globalfoundries Inc. Forming single diffusion break and end isolation region after metal gate replacement, and related structure
US10157796B1 (en) * 2017-11-14 2018-12-18 Globalfoundries Inc. Forming of marking trenches in structure for multiple patterning lithography
US10388652B2 (en) * 2017-11-14 2019-08-20 Globalfoundries Inc. Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same
US10504990B2 (en) * 2017-11-21 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation features and methods of fabricating the same
US10510894B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure having different distances to adjacent FinFET devices
US10347540B1 (en) * 2017-12-14 2019-07-09 International Business Machines Corporation Gate cut using selective deposition to prevent oxide loss

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160336426A1 (en) * 2015-05-15 2016-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with unleveled gate structure and method for forming the same
TW201715602A (zh) * 2015-08-07 2017-05-01 東京威力科創股份有限公司 不具有虛擬閘極之圖案化方法
US20180102362A1 (en) * 2016-10-10 2018-04-12 International Business Machines Corporation Finfets with controllable and adjustable channel doping

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