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CN101996893A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101996893A
CN101996893A CN2010102492322A CN201010249232A CN101996893A CN 101996893 A CN101996893 A CN 101996893A CN 2010102492322 A CN2010102492322 A CN 2010102492322A CN 201010249232 A CN201010249232 A CN 201010249232A CN 101996893 A CN101996893 A CN 101996893A
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CN
China
Prior art keywords
semiconductor element
active surface
semiconductor
interconnection structure
sealant
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Granted
Application number
CN2010102492322A
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CN101996893B (zh
Inventor
R·A·帕盖拉
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Publication of CN101996893A publication Critical patent/CN101996893A/zh
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Abstract

本发明涉及半导体器件及其制造方法。在半导体器件中，安装第一半导体管芯并且它的有源表面面向临时载体。在第一半导体管芯和临时载体上沉积密封剂。除去临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面。在第一半导体管芯的有源表面上形成掩蔽层。在密封剂的第一侧上形成第一互连结构。所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构。除去掩蔽层以在第一半导体管芯的有源表面上形成空腔。在空腔中安装第二半导体管芯。第二半导体管芯以短信号路径电连接到第一半导体管芯的有源表面。

Description

半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在内建互连结构的各部分之间形成空腔的方法。下部半导体管芯被安装在空腔中以将短信号路径提供给上部半导体管芯。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积(footprint)，其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
可以利用导电直通硅通路(TSV)、直通孔通路(THV)、或镀铜导电柱实现包含堆叠于多级之上的半导体器件的扇出型晶片级芯片规模封装(FO-WLCSP)中的电互连。利用激光钻孔或深反应离子刻蚀(DRIE)在管芯周围的硅或有机材料中形成通路。例如使用电镀工艺通过铜沉积，利用导电材料来填充所述通路，以形成导电TSV和THV。所述TSV和THV进一步通过跨越每个半导体管芯形成的内建互连结构连接。
在例如在通信应用中使用的高速半导体器件中，堆叠半导体管芯需要以快速和有效的方式通信。在常规FO-WLCSP中，堆叠管芯之间的信号必须通过内建互连层、以及TSV和THV被路由(routed)，这引起长的信号路径。更长的信号路径降低FO-WLCSP的操作速度。另外，即使在不用于信号路由的区域中，内建互连层也跨越每个半导体管芯形成，这不必要地增加了制造材料和成本。
发明内容
在FO-WLCSP中存在对高速垂直互连结构的需要。因此，在一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供临时载体，安装第一半导体管芯并且它的有源表面面向所述临时载体，在第一半导体管芯和临时载体上沉积密封剂，除去临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面，在第一半导体管芯的有源表面上形成掩蔽层，以及在密封剂的第一侧上形成第一互连结构。所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构。所述方法进一步包括以下步骤：除去掩蔽层以在第一半导体管芯的有源表面上形成空腔，以及在空腔中安装第二半导体管芯。第二半导体管芯被电连接到第一半导体管芯的有源表面。
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供临时载体，安装第一半导体管芯并且它的有源表面面向所述临时载体，在第一半导体管芯和临时载体上沉积密封剂，除去临时载体以暴露密封剂的第一侧，在密封剂的第一侧上形成第一互连结构而不覆盖第一半导体管芯的有源表面，以及在第一互连结构的各部分之间的第一半导体管芯的有源表面上安装半导体部件。所述半导体部件被电连接到第一半导体管芯的有源表面。
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供第一半导体管芯，在第一半导体管芯上沉积密封剂，在密封剂上形成第一互连结构而不覆盖第一半导体管芯的有源表面，以及在第一互连结构的各部分之间的第一半导体管芯的有源表面上安装半导体部件。所述半导体部件被电连接到第一半导体管芯的有源表面。
在另一个实施例中，本发明是包括第一半导体管芯和沉积在第一半导体管芯上的密封剂的半导体器件。第一互连结构形成在密封剂上而不覆盖第一半导体管芯的有源表面。半导体部件被安装在第一互连结构的各部分之间的第一半导体管芯的有源表面上。所述半导体部件被电连接到第一半导体管芯的有源表面。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节；
图3a-3g示出在内建互连结构的各部分之间形成空腔用于上部和下部堆叠管芯之间的短信号路径的工艺；
图4示出具有在上部和下部堆叠半导体管芯之间的短信号路径的FO-WLCSP；
图5示出被暴露的上部半导体管芯的后表面；
图6示出通过上部半导体管芯形成的TSV；
图7示出在下部半导体管芯周围形成的密封剂；
图8示出形成在上部半导体管芯上的TIM和热沉；
图9示出通过形成在上部半导体管芯上的TIM和热沉形成的TSV；
图10示出形成在下部半导体管芯周围的EMI屏蔽层；
图11示出被安装在空腔中并且被附着到上部管芯的分立半导体部件；
图12示出在上部半导体管芯上的另外的半导体管芯和顶侧内建互连结构；
图13示出被安装在空腔中并且被附着到上部半导体管芯的散热器(heat spreader)；
图14a-14i示出在内建互连结构中形成空腔用于上部和下部堆叠半导体管芯之间的短信号路径的另一个工艺；以及
图15示出具有在上部和下部堆叠半导体管芯之间的短信号路径的FO-WLCSP。
具体实施方式
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(1and grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leaded package，QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(AL)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag))的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填料(underfill)或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级包装(packing)互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-3g示出在FO-WLCSP中在内建互连结构的各部分之间形成空腔用于上部和下部堆叠半导体管芯之间的短信号路径的工艺。在图3a中，晶片形式的衬底或载体120包括临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料或体半导体材料。载体120也可以是带(tape)。在一个实施例中，载体120的直径是20.3厘米(cm)。可以在载体120上形成可选界面层122作为临时结合膜或腐蚀停层。
半导体管芯或部件124利用面朝下向着载体120的有源表面128上的接触焊盘126被安装到界面层122。有源表面128包括模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面128内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。
在图3b中，利用浆料印刷(paste printing)、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器(applicator)将密封剂或模塑料130沉积在半导体管芯124上。密封剂130可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂130不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图3c中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模(wet stripping)来除去载体120和可选界面层122。掩蔽层132被形成在接触焊盘126之间的有源表面128上。
在图3d中，底侧内建互连结构134形成在半导体管芯124和密封剂130上。内建互连结构134包括绝缘或钝化层136，所述绝缘或钝化层136包括二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层136。
底侧内建互连结构134进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀(electroless plating))形成在绝缘层136中的导电层138。导电层138可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层138的一部分被电连接到半导体管芯124的接触焊盘126。导电层138的其它部分可以根据半导体器件的设计和功能是电共有的(electricallycommon)或被电隔离。
掩蔽层132阻挡在半导体管芯124的有源表面128上形成内建互连结构134。在图3e中，掩蔽层132被除去，留下了空腔140，这从半导体管芯124的底侧暴露有源表面128。
在图3f中，半导体管芯或部件142利用面向上的接触焊盘144在内建互连结构134的各部分之间的空腔140内被安装到有源表面128上的接触焊盘。凸块146提供接触焊盘144和有源表面128之间的电连接。半导体管芯142包括包含模拟或数字电路的有源表面，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯142也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。
利用蒸发、电解电镀、无电电镀、球滴(ball drop)、或丝网印刷工艺将导电凸块材料沉积到内建互连结构134上并且电连接到导电层138。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层138。在一个实施例中，通过将所述凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块148。在一些应用中，凸块148二次回流以改善到导电层138的电接触。所述凸块也可以被压缩结合到导电层138。凸块148表示一种可以形成在导电层138上的互连结构。所述互连结构也可以使用结合线(bond wire)、柱形凸块(stud bump)、微凸块、或其它电互连。
在图3g中，底层填料材料150(例如环氧树脂)被沉积到半导体管芯124和142之间。利用锯条或激光切割装置152将半导体管芯124单体化(singulate)成单个半导体器件。
图4示出单体化之后的FO-WLCSP 154。半导体管芯142被安装在利用掩蔽层132形成在底侧内建互连结构134的各部分之间的空腔140中。半导体管芯124和142利用凸块146电互连。通过将半导体管芯142放置在空腔140中，管芯之间的间隔被减小，导致短且有效的信号路径以改善电性能并且提高FO-WLCSP 154的操作速度。半导体管芯142(包括凸块146)的高度小于凸块148的高度。利用以上新颖的制造工艺和结构，FO-WLCSP 154的总高度被减小。
在图5中，通过刻蚀工艺除去密封剂130的一部分以暴露半导体管芯124的后表面156。
在图6中，通过刻蚀工艺除去密封剂130的一部分以暴露半导体管芯124的后表面156。利用激光钻孔或刻蚀工艺，例如DRIE，通过半导体管芯124形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、W、多晶硅、或其它合适的导电材料来填充所述通路，以形成导电TSV 158。TSV 158可以在将管芯安装到图3a中的界面层122之前形成在半导体管芯124中。TSV 158可以根据管芯的设计电互连。
图7示出利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器沉积在半导体管芯142之上以及周围的密封剂或模塑料160。密封剂160可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂160不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图8中，密封剂130的一部分被除去以暴露半导体管芯124的后表面156。在与有源表面128相对的半导体管芯124的后表面156上沉积热界面材料(TIM)162。TIM 162可以是氧化铝、氧化锌、氮化硼、或粉状银。热沉164被安装在TIM 162和密封剂130上。热沉164可以是Al、Cu、或具有高热导率的另外的材料，以为半导体管芯124提供热耗散。TIM 162帮助散布和耗散由半导体管芯124产生的热。
在图9中，通过刻蚀工艺除去密封剂130的一部分以暴露半导体管芯124的后表面156。利用激光钻孔或刻蚀工艺，例如DRIE，通过半导体管芯124形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通路，以形成导电TSV 170。TSV 170可以在将管芯安装到图3a中的界面层122之前形成在半导体管芯124中。TSV 170可以根据管芯的设计电互连。
在与有源表面128相对的半导体管芯124的后表面156上沉积TIM 172。TIM 172可以是氧化铝、氧化锌、氮化硼、或粉状银。热沉174被安装在TIM 172和密封剂130上。热沉174可以是Al、Cu、或具有高热导率的另外的材料，以为半导体管芯124提供热耗散。TIM172帮助散布和耗散由半导体管芯124产生的热。
图10示出形成在半导体管芯142上的屏蔽层176。屏蔽层176可以是Cu、Al、铁氧体或羰基铁(carbonyl iron)、不锈钢、镍银、低碳钢、硅铁钢、箔、环氧树脂、导电树脂、以及能够阻挡或吸收电磁干扰(EMI)、射频干扰(RFI)、和其它器件之间的干扰的其它金属和复合物。屏蔽层176也可以是非金属材料(例如碳黑)或铝片(aluminum flake)，以减小EMI和RFI的影响。屏蔽层176通过导电层178到凸块148而接地。
图11示出被安装到空腔140中的有源表面128上的接触焊盘的无源部件180。无源部件180可以是电阻器、电容器、电感器、或分立的有源器件。
在图12中，利用激光钻孔或刻蚀工艺，例如DRIE，通过密封剂130形成多个通路。使用PVD、CVD、电解电镀、无电电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通路，以形成导电THV
182。可替换地，在沉积密封剂130之前在半导体管芯124的周围形成导电柱182。通过下述步骤来形成导电柱182：沉积光致抗蚀剂层，在光致抗蚀剂中刻蚀多个通路，利用导电材料填充所述通路，以及除去所述光致抗蚀剂层，留下导电柱。
顶侧内建互连结构184形成在密封剂130上。内建互连结构184包括绝缘或钝化层186，所述绝缘或钝化层186包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层186。
顶侧内建互连结构184进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀)形成在绝缘层186中的导电层188。导电层188可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层188的一部分被电连接到导电通路182。导电层188的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。导电通路182是底侧内建互连结构134和顶侧内建互连结构184之间的z方向互连。
利用凸块192将半导体管芯或部件190安装到内建互连结构184。半导体管芯190包括包含模拟或数字电路的有源表面193，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面193内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯190也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。底层填料材料194，例如环氧树脂，被沉积在半导体管芯190之下。
图13示出利用凸块198安装到半导体管芯124的有源表面128的空腔140中的散热器196。散热器196散布和耗散由半导体管芯124产生的热。
图14a-14i示出在内建互连结构的各部分之间形成空腔用于FO-WLCSP中上部和下部堆叠半导体管芯之间的短信号路径的另一个工艺。在图14a中，晶片形式的衬底或载体200包括临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料或体半导体材料。载体200也可以是带。在一个实施例中，载体200的直径是20.3cm。可以在载体200上形成可选界面层202作为临时结合膜或腐蚀停层。多个可选可湿性焊盘(wettable pad)可以形成在载体200上。多个坝墙(dam wall)204被沉积在界面层202上以在半导体管芯208的有源表面将要位于的指定区域周围形成包围(enclosure)。
在图14b中，凸块206被形成在界面层202上。利用面向下朝向载体200的有源表面212上的接触焊盘210在凸块206上安装半导体管芯或部件208。可替换地，可以在将半导体管芯208安装到载体200之前在接触焊盘210上形成凸块206。有源表面212包括模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面212内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯208也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。
图14c示出被安装到界面层202上的凸块206的半导体管芯208的接触焊盘210。凸块206的高度大约与坝墙204的高度相同。坝墙204在界面层202和有源表面212之间被指定用于有源表面212的区域周围形成密封的包围。
在图14d中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器将密封剂或模塑料214沉积在半导体管芯208上。密封剂214可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂214不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。由坝墙204形成的包围提供密封以防止密封剂214蔓延到接触焊盘210之间的有源表面212的内部部分。因此，坝墙204在半导体管芯208的有源表面212下形成空腔216。
在图14e中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体200和可选界面层202。掩蔽层218被形成在接触焊盘210之间的有源表面212上的空腔216中。
在图14f中，底侧内建互连结构220形成在半导体管芯208和密封剂214上。内建互连结构220包括绝缘或钝化层222，所述绝缘或钝化层222包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层222。
底侧内建互连结构220进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀)形成在绝缘层222中的导电层224。导电层224可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层224的一部分通过凸块206被电连接到半导体管芯208的接触焊盘210。导电层224的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
掩蔽层218阻挡在半导体管芯208的有源表面212上形成内建互连结构220。在图14g中，掩蔽层218被除去，留下空腔226，这从半导体管芯208的底侧暴露出有源表面212。
在图14h中，半导体管芯或部件230利用面向上的接触焊盘232在内建互连结构220的各部分之间的空腔226内被安装到有源表面212上的接触焊盘。凸块234提供接触焊盘232和有源表面212之间的电连接。坝墙204和掩蔽层218的组合提供更深的空腔226以容纳具有更大厚度的半导体管芯230。半导体管芯230包括包含模拟或数字电路的有源表面，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯230也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。
利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到内建互连结构220上并且电连接到导电层224。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层224。在一个实施例中，通过将所述凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块236。在一些应用中，凸块236二次回流以改善到导电层224的电接触。所述凸块也可以被压缩结合到导电层224。凸块236表示一种可以形成在导电层224上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
在图14i中，底层填料材料238，例如环氧树脂，被沉积在半导体管芯208和230之间。利用锯条或激光切割装置240将半导体管芯208和230单体化成单个半导体器件。
图15示出单体化之后的FO-WLCSP 242。半导体管芯230被安装在利用坝墙204和掩蔽层218形成在半导体管芯208的底侧内建互连结构220的各部分之间的空腔226中。半导体管芯208和230利用凸块234电互连。通过将半导体管芯230放置在空腔226中，管芯之间的间隔被减小，导致短且有效的信号路径以改善电性能并且增加FO-WLCSP 242的操作速度。半导体管芯230(包括凸块234)的高度小于凸块236的高度。利用以上新颖的制造工艺和结构，FO-WLCSP242的总高度被减小。
在图5-13中所示的多个实施例可适用于图15。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供临时载体；
安装第一半导体管芯，并且它的有源表面面向所述临时载体；
在第一半导体管芯和临时载体上沉积密封剂；
除去临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面；
在第一半导体管芯的有源表面上形成掩蔽层；
在密封剂的第一侧上形成第一互连结构，所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构；
除去掩蔽层以在第一半导体管芯的有源表面上形成空腔；以及
在空腔中安装第二半导体管芯，第二半导体管芯被电连接到第一半导体管芯的有源表面。
2.如权利要求1所述的方法，进一步包括通过第一半导体管芯形成导电直通硅通路。
3.如权利要求1所述的方法，进一步包括在第二半导体管芯上形成屏蔽层。
4.如权利要求1所述的方法，进一步包括：
在与第一半导体管芯的有源表面相对的第一半导体管芯的后表面上形成第二互连结构；以及
将第三半导体管芯安装到第二互连结构。
5.一种制造半导体器件的方法，包括：
提供临时载体；
安装第一半导体管芯，并且它的有源表面面向所述临时载体；
在第一半导体管芯和临时载体上沉积密封剂；
除去临时载体以暴露密封剂的第一侧；
在密封剂的第一侧上形成第一互连结构而不覆盖第一半导体管芯的有源表面；以及
在第一互连结构的各部分之间的第一半导体管芯的有源表面上安装半导体部件，所述半导体部件被电连接到第一半导体管芯的有源表面。
6.如权利要求5所述的方法，进一步包括：
在第一半导体管芯的有源表面上形成掩蔽层；
在密封剂的第一侧上形成第一互连结构，所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构；以及
除去掩蔽层以在第一半导体管芯的有源表面上形成空腔。
7.如权利要求5所述的方法，进一步包括：
在所述临时载体上形成坝墙；
将第一半导体管芯安装到所述临时载体以便所述有源表面存在于所述坝墙内；
在第一半导体管芯和临时载体上沉积密封剂，所述坝墙防止所述密封剂蔓延到第一半导体管芯的有源区域；
除去所述临时载体；
在第一半导体管芯的有源表面上形成掩蔽层；
在密封剂的第一侧上形成第一互连结构，所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构；以及
除去掩蔽层以在第一半导体管芯的有源表面上形成空腔。
8.如权利要求5所述的方法，其中所述半导体部件是半导体管芯或分立半导体器件。
9.如权利要求5所述的方法，进一步包括通过第一半导体管芯形成导电直通硅通路。
10.如权利要求5所述的方法，进一步包括将散热器安装到第一半导体管芯的有源表面。
11.如权利要求5所述的方法，进一步包括在所述半导体部件的周围沉积第二密封剂。
12.如权利要求5所述的方法，进一步包括在所述半导体部件上形成屏蔽层。
13.如权利要求5所述的方法，进一步包括将热沉安装到与第一半导体管芯的有源表面相对的第一半导体管芯的后表面。
14.如权利要求5所述的方法，进一步包括：
在与第一半导体管芯的有源表面相对的第一半导体管芯的后表面上形成第二互连结构；以及
将第二半导体管芯安装到第二互连结构。
15.一种制造半导体器件的方法，包括：
提供第一半导体管芯；
在第一半导体管芯上沉积密封剂；
在密封剂上形成第一互连结构而不覆盖第一半导体管芯的有源表面；以及
在第一互连结构的各部分之间的第一半导体管芯的有源表面上安装半导体部件，所述半导体部件被电连接到第一半导体管芯的有源表面。
16.如权利要求15所述的方法，进一步包括：
在第一半导体管芯的有源表面上形成掩蔽层；
在密封剂和第一半导体管芯上形成第一互连结构，所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构；以及
除去掩蔽层以在第一半导体管芯的有源表面上形成空腔。
17.如权利要求15所述的方法，进一步包括：
在第一半导体管芯的有源表面周围形成坝墙；
在第一半导体管芯上沉积密封剂，所述坝墙防止所述密封剂蔓延到第一半导体管芯的有源区域；
在第一半导体管芯的有源表面上形成掩蔽层；
在密封剂上形成第一互连结构，所述掩蔽层阻挡在第一半导体管芯的有源表面上形成第一互连结构；以及
除去掩蔽层以在第一半导体管芯的有源表面上形成空腔。
18.如权利要求15所述的方法，其中所述半导体部件是半导体管芯或分立半导体器件。
19.如权利要求15所述的方法，进一步包括通过第一半导体管芯形成导电直通硅通路。
20.如权利要求15所述的方法，进一步包括：
在与第一半导体管芯的有源表面相对的第一半导体管芯的后表面上形成第二互连结构；以及
将第二半导体管芯安装到第二互连结构。
21.一种半导体器件，包括：
第一半导体管芯；
沉积在第一半导体管芯上的密封剂；
形成在密封剂上而不覆盖第一半导体管芯的有源表面的第一互连结构；以及
安装在第一互连结构的各部分之间的第一半导体管芯的有源表面上的半导体部件，所述半导体部件被电连接到第一半导体管芯的有源表面。
22.如权利要求21所述的半导体器件，其中所述半导体部件是半导体管芯或分立半导体器件。
23.如权利要求21所述的半导体器件，进一步包括通过第一半导体管芯形成的导电直通硅通路。
24.如权利要求21所述的半导体器件，进一步包括形成在所述半导体部件上的屏蔽层。
25.如权利要求21所述的半导体器件，进一步包括：
形成在与第一半导体管芯的有源表面相对的第一半导体管芯的后表面上的第二互连结构；以及
安装到第二互连结构的第二半导体管芯。
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