SU1727213A1 - Device for control over access to common communication channel - Google Patents

Abstract

The invention relates to control devices for accessing a common communication channel and can be used in information collection and processing systems. The goal — improving operational efficiency — is achieved by introducing into the subscriber units a detector of information performed on the first and second elements OR and the shift register, as well as the analyzer filling the memory block implemented on the first, second and third triggers and the first, second and third elements AND The access control by the subscriber units 5 to the communication channel through the block of elements OR is carried out by the pulse distributor. 1 il.

Description

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The invention relates to the transmission of discrete information and can be used in the organization of communication systems and computing systems with a common communication channel, as well as in telemetry, telecontrol and tele-alarm systems.

The aim of the invention is to increase the speed of information transfer.

The drawing shows a structural electrical circuit of the device.

 The control device for access to a common communication channel contains subscriber units 1, a generator of 2 pulses, a block of 3 OR elements, a block of 4 AND elements and a distributor of 5 pulses, each subscriber unit 1 containing a source of 6 information, the first 7, the second 8 and the third 9 the elements AND, the first 10, the second 11 and the third 12 triggers, the counter 13, the multiplexer 14, the first 15 and the second 16 elements OR, the shift register 17 and the memory block 18.

The control device for access to a common communication channel operates as follows.

The generator 2 pulses produces clock pulses, which through the first input of the block 4 elements And arrive at the input of the distributor 5 pulses and start it. From the first clock pulse, a first pulse appears at the first output of the pulse distributor 5, and from the second clock pulse a second pulse appears at the second output of the distributor 5 pulses, etc. to N, where N is the number of subscriber units 1. Pulses alternately appear at the outputs of the distributor 5 pulses and, arriving at the first input of each subscriber channel 1, interrogate thereby the states of the sources 6 of the information.

Suppose that the output of the source 6 of the information of the first subscriber unit 1

with

there is discrete information, then it, arriving at the first input of the first trigger 10, translates it into a single state. The first bit at the beginning of the transfer of any information sequence has the level of logical units. Simultaneously, the information pulses arrive at the first input of the shift register 17 and, through the first input of the first element IL AND 15 to the second input of the shift register 17, providing the level of the sequential information input with the shift to the right level. The shift register 17 is loaded with data by means of clock pulses arriving at its clock input from the output of the generator 2 pulses. The second element LL & 16 performs a logical addition of information pulses that appear at the outputs of the shift register 17. This ensures the constancy of the signal level of the logical unit during the time of arrival of information pulses, the output of the second element OR 16, which is simultaneously applied to the third input of the second element AND 8, and through the second input of the first element OR 15 to the second input of the register

17 shift. Based on the above, conditions are created for the passage of the clock pulses generated by the pulse generator 2 through the second input of the second element 8 to the clock input of the memory block 18, as well as for the signal of the level of the logical unit at the output of the first element 15 which does not the second input of the register 17 shift, provides the mode of sequential input of information with a shift to the right. The clock pulses from the output of the second element I 8 to the clock input of the memory block 18 record the information pulses coming from the output of the source 6 of information. In case of complete filling of the block

18, from its overflow output, a signal is transmitted to the input of the information source b, suspending the transmission of information pulses.

The recording of information sequences in memory block 18 may be performed repeatedly. The arrival of a certain number of zero bits after the arrival of the last single pulse is a sign that the source 6 has completed transmitting the discrete sequence information. After the arrival of a specified number of zero bits on all outputs of shift register 17, there will be logic zero levels, which, after adding them in the second element OR 16, also provide a logic level

zero at its output. This signal, acting on the third input of the second element And 8, prohibits the passage of clock pulses to the clock input of the memory block 18, and also passes from the second input of the first element OR 15, at the first input of which there is a logic zero level due to the lack of information at the output source 6 information. Logical zero level with

the output of the first element OR 15 passes to the second input of the shift register 17, thereby transferring it to the storage mode.

Upon receipt of a signal from the output of the distributor 5 pulses to the first input

The first subscriber unit 1, this pulse appears at the output of the first element And 7 and switches the second trigger 11 to one state. The level of logical zero coming from its second output

on one of the inputs of the block 4 elements And, prohibits the passage of clock trigger impulse-.sov to the input of the distributor 5 pulses. The level of logical units, which appeared at the reset input of the counter 13,

the active level of which is the logical zero level allows the counting of clock pulses arriving at its clock input from the output of the generator 2 pulses. The counter 17, under their action, enumerates its states, thereby making a change in the code arriving at the address inputs of the multiplexer 14. A sequential switching occurs.

input data multiplexer 14 to its output. At the data inputs of multiplexer 14, the code of this subscriber unit 1 is set. This code arrives at one of the inputs, block 3 OR elements, and without delay, is transmitted to the communication channel. After iterating through the counter 13 of all its states, overflow occurs at its output overflow pulse, which simultaneously enters the first input of the second trigger 11,

switching it to the zero state, and the second input of the third trigger 12, transferring it to the single state. From the second output of the third trigger 12, the logical zero level is fed to one of the inputs of the block 4 of the elements I, thus not allowing the passage of clock pulses to the input of the distributor 5 pulses for the time of reading information from the memory block 18. The level of the logical unit from the first output of the third trigger 12 enters the first input of the third element I 9, ensuring the passage of clock pulses arriving at its second input to the second input of the memory block 18. The digital information is read out from the memory block 18 and, arriving at one of the inputs of the block 3 of the OR elements, passes to the communication channel.

In memory block 18, the deciphering of the write address and the read address is performed by two independent nodes that have autonomous address inputs, so it is possible, along with reading data from it, to record discrete information from the output of information source 6.

After reading the last bit recorded in memory block 18, memory block 18 emits a reset pulse, which goes simultaneously to the second input of the first trigger 10 and to the first input of the third trigger 12, transferring them to the zero state and preparing to transfer the information arriving from the output of source 6 information. After the occurrence of the level of the logical unit at the second output of the third trigger 12, the passage of clock pulses through the first input of the 4-element block 4 to the input of the distributor 5 pulses begins, which again begins to poll the sources 6 of information.

Claims (1)

Invention Formula A common channel access control device containing subscriber units, a pulse generator, an OR block and a series-connected AND block and a pulse distributor, whose outputs are connected to the first inputs of the respective subscriber blocks, each of which contains an information source and the first And block, the input of which is the input of the subscriber unit, characterized in that, in order to increase efficiency, the first, second and third triggers, the second and the third are entered into each subscriber unit And, counter, multiplexer, first and second OR elements, shift register and memory block whose overflow output is connected to the control input of the information source, whose output is connected to the combined first input of the memory block, shift register, first element 5 OR and the first trigger, the output of which is connected to the second input of the first And, and to the first input of the second And; the output of which is connected to the clock input of the memory block, the first output of which 0 is connected to the second input of the first trigger and to the first input of the third trigger, the second input of which is combined with the first input of the second trigger and connected to the counter overflow output, reset input 5 which is connected to the first output of the second trigger, the second input of which is connected to the output of the first element I, the first output of the third trigger connected to the first input of the third element I, the output of which is connected to the second input of the memory block, the output of which is the first output of the subscriber a block whose second output is the output of a multiplexer whose inputs are connected to the outputs 5 counter, the clock input of which is combined with the clock input of the shift register, the second inputs of the second and third elements AND, and is the clock input of the subscriber unit, the third and fourth 0 outputs of which are the second outputs of the second and third triggers, the output of the first element AND is connected to the second input of the shift register, the outputs of which are connected to the inputs of the second OR element, the output of which is connected to the second input the first element OR to the third input the second element And, moreover, the output of the generator of pulses is connected to the clock inputs of the subscriber units and the first input 0 of the AND block, to the other inputs of which the second and third outputs of the subscriber units are connected, the first and second outputs of which are connected to the inputs of the block of the OR elements. g s q