SU1081637A1 - Information input device - Google Patents

Abstract

A DEVICE FOR INPUT OF INFORMATION containing a multiplexer, memory blocks, a counter, the outputs of which are connected to the inputs of the first group of the multiplexer, the inputs of the second group of which are connected to the outputs of the blocks, the inputs of the group of which are the inputs of a device group that is in order to increase the reliability of the device, a shift register, a trigger, a NOT element, a clock generator, the first, second and third elements AND, a decoder, the inputs of which are connected to the outputs of the counter whose input is connected, are entered into it The code of the second element I, the first input of the second and third elements I are connected to the first output of the pulse generator, the output of the third element I is connected to the input of the decoder j whose outputs are connected to the inputs of memory blocks, the output of the multiplexer is connected to the first inputs of the shift register and trigger, the second input which is the input of the device, the first output of the trigger is connected to the second inputs of the first I and the third elements And, the third input of the first element And is connected to the output of the pulse generator, the second output ggera .The inputs coupled to a second second AND gate, the outputs of the register are svdiga device outputs the most significant bit output of shift register elements via: cop is coupled to the first input of the first AND gate EO, whose output is connected to a second input of a shift register. 00 |

Description

The invention relates to automation and computing and can be used to enter information in collective computing systems. A multi-channel device for inputting information is known, which contains in each channel the first and second trigger and the element I lj. The disadvantage of the device is the limitation of the number of channels by the size of the information word entered into the computer. The closest to the invention to the technical essence is a device for inputting information, containing blocks of buffer memory in each channel, a multiplexer, a counter, the outputs of blocks of buffer memory being connected to one input of a multiplexer, and outputs of a counter to other inputs of a multiplexer 2 A disadvantage of the known device is low reliability due to the complexity of the multiplexer node switching the number of multi-bit circuits. The aim of the invention is to increase the reliability of the device. The goal is achieved by the fact that, in a device for inputting information containing a multiplexer, memory blocks, a counter, the outputs of which are connected to the inputs of the first group of the multiplexer, the inputs of the second group of which are connected to the outputs of the memory blocks, the inputs of the group of which are inputs device groups, shift register, trigger, “element NOT, clock pulse generator, first, second and third elements AND, decoder, the inputs of the group of which are connected to the outputs of the counter, whose input is connected to the output of the second element And the first input of the second and third elements I is connected to the first output of the pulse generator, the output of the third element I is connected to the input of the decoder, the outputs of which are connected to the inputs of the units of the unit, the output of the multiplexer is connected to the first inputs of the shift register and the trigger, the second input is the input of the device, the first output of the trigger is connected to the second inputs of the first and third elements And, the third input of the first element And is connected to the second output of the generator-i pulse generator, the second output of the trigger is connected to the second input of orogo AND gate, the outputs of the shift register are output devices output the most significant bit of the shift register through the element is coupled to the first input of the first AND gate whose output is connected to the second input of the shift register. The drawing shows a block diagram of the device. The device contains memory blocks 1, counter 2, multiplexer 3, decoder 4, shift register 5, trigger 6, element 7, pulse generator 8, first element 9, second element 10 and third element 11. Memory blocks 1 are intended for storing information from the moment of its recording to the moment of transfer to the computer, counter 2 for cyclic polling of channels, multiplexer 3 for transmitting information from blocks 1 of the buffer memory to the input of shift register 5, decoder 4 for issuing shift pulses to that block 1 buffer memory, information before through a multiplexer 3. The shift register 5 is designed for serial-parallel conversion information, a trigger circuit 6 for switching from the channel scanning mode information in the transmission mode, NOT element 7 - for prohibition of shift pulses at the time of completion of the series-parallel conversion information. The clock pulse generator 8 is designed to form two series of pulses shifted one relative to the other by half a turn. The first AND 9 element is designed to generate information shift pulses through the shift register 5, the second AND 10 element to generate counting pulses in the channel scanning mode, the third And 11 element to generate serial output pulses from the buffer memory. The device works as follows. In the channel polling mode, counter 2 alternately connects to the output of the multiplexer 3 outputs of blocks 1 of memory. Simultaneously the counter acts

decoder A, which selects the shift input of that memory block whose information is fed to the output of multiplexer 3,

When a logical 1 is detected in one of the channels, which means entering information into memory block 1, trigger 6 puts the circuit into information transfer mode, prohibiting the supply of counting pulses to the counter through AND 10 and allowing shear pulses to the corresponding memory 1 through the element Both 11 and the decoder 4 and impulse-j shifted by a half-cycle through the element AND 9 by the shift register 5. The transmission of information from memory block 1 to shift register 5 via multiplexer 3 occurs on the order of the day.

The number of shear pulses corresponds to the size of the information word transmitted to the computer. Sequence (1st pulse completely clears the corresponding block 1 of buffer memory and writes logical 1, indicating readiness to transfer information to the computer, to the high-order register of the shift register 5. At the same time, a signal preventing the further arrival of shift pulses on the register 5 shift through the element And 9.

When receiving information, the computer inserts a signal that switches the trigger 6 in the mode of polling channels.

The proposed device makes it possible to simplify the multiplexing of channels by serial transmission (1-bit information through a multiplexer and subsequent serial-parallel conversion of information, and in organizing a multi-user mode, to reduce the amount of equipment and improve system reliability.

Claims (1)

A device for inputting information, comprising a multiplexer, memory blocks, a counter whose outputs are connected to the inputs of the first group of the multiplexer, the inputs of the second group of which are connected to the outputs of the memory blocks, the group inputs of which are inputs of the device group, which is the fact that, in order to increase the reliability of the device, a shift register, a trigger, an element NOT, a clock pulse generator, the first, second and third elements AND, a decoder, the inputs of which are connected to the outputs of the counter, the input of which is connected to the output of the second element And, the first input of the second and third elements And are connected to the first output of the pulse generator, the output of the third element And is connected to the input of the decoder j the outputs of which are connected to the inputs of the memory blocks, the output of the multiplexer is connected to the first inputs of the shift register and trigger, the second input of which is the input of the device, the first output of the trigger is connected to the second inputs of the first and third elements And, the third input of the first element And is connected to the second output of the pulse generator, the second output of the trigger is connected nen with the second input of the second element And, the outputs of the svdig register are the outputs of the device, the high-order output of the shift register through the element is NOT connected to the first input of the first element And, the output of which is connected to the second input of the shift register.