SU492042A1 - Device for matching a stream of compressed priority messages with a communication channel - Google Patents

Description

yen in the form of three reversible counters 10, II, 12, designed to generate the address of the recording of counts III, II and I priorities, respectively; valve group 13, 14 and 15, output circuit OR 16, priority decoder 17, circuit AND 18-22, circuit NOT 23 and 24, group circuit AND 25, group OR circuit 26 and transmitter 27.

The cell width of drive 2, valve group 8, and input register 9 is determined by the width of the transmitted data. The input register, in addition to the bits for the information part of the reference, contains two bits of the priority attribute (in the case of dividing data into three priorities). The storage volume is selected from the conditions of permissible probabilities of data loss of the three priorities and permissible average data delays of the three priorities before transmission over the communication channel, determined in accordance with the normal loads of the three priority sub-flows. The size of the reversible counters 10, 11, and 12, valve groups 13, 14, and 15, the circuit OR 16, and the decoder 4 is determined by the storage capacity. The number of circuits is AND 25 and OR 26 is equal to the storage capacity. The number of inputs for circuits 26 increases from the circuit to the circuit by one from right to left, starting with two at the second to the right of the drive cell.

The cell size of the accumulator of the proposed device is determined by the size of the transmitted samples. In addition to the information part, the overhead of the counts includes overhead bits for linking the readout to the sensor address and time of occurrence (cycle number), which provides unambiguous decommutation of readings on the receiving side. The input register 9 bit is larger than the sample width by the number of priority sign bits.

The device works as follows.

The next significant count is written from the data compression device to the input register 9. A sign of the priority of the count comes from the bits of the input register assigned to it to the decoder 17, where it is converted to the priority potential that appears in one of the three decoder output and goes to one from the groups of valves 13, 14 or 15 and to one of the three schemes AND 18, 19 or 20. This potential connects through the open group of valves 13, 14 or 15 and the scheme OR 16 to the decoder 4 outputs of only one reversing counter 10, 11 or 12 The contents of the account snip 12 is a cell number, which should zapisats next count, if I prioretety; the contents of the reversible counter 11 is the number of the cell into which the next count should be recorded if it is P priority; The contents of the counter 10 are the number of the cell to which the next count should be recorded if it is of priority III.

The proposed device is constructed in such a way that the substantial readings of the three priorities coming from the compression device fill drive 2 from right to left, lining up in a natural priority queue and in the sequence of their arrival within the given priority. The samples are arranged in priority groups, each new incoming count is recorded at the end

groups of samples of his priority, and the samples decrease sequentially from right to left of the group to the group. Inside the group, counts are arranged from right to left in the sequence of their arrival.

In order for the counting input to the matching device to take up a place corresponding to its priority, at the end of the sample group of the same priority, it is necessary to shift all the groups of lower priorities to the left by one cell in order to release the corresponding cell for the incoming sample. The incoming count is recorded in the input register 9, its priority is decrypted in the decoder 17, the reversible counter corresponding to the priority of the count is connected to the address decoder 4 and the decoder 4 generates at one of its address

tires, the potential of recording resolution in the corresponding memory cell, into which the incoming reading is to be written. After that, all the information in the packer to the left of the selected cell and in the

the selected cell is shifted left by one cell by the left shift pulse (i.e.f.) and only then by the write pulse (i.e.) the new count is written from the input register to the selected cell of accumulator 2. Circuit groups AND 25 and OR 26 provide shift to the left by the left shift of the necessary part of the storage information. Circuits 25 and 26 are not needed for the leftmost cell. From the output bus decoder hell

Resa 4, the recording resolution potential is fed to the selected cell and only allows it to record the readout from the data bus. The same potential is applied to all located to the left of the selected cell and under the cell itself of the circuit 26, and through them to the circuits 25 controlled by them. Therefore, the left shift pulse passes through the open circuits 25 only to the cell selected for recording and all cells located from her to the left, and shifts the information stored by them one cell to the left. All circuits 25 located to the right of the cell selected for recording remain closed and the left shift pulse is not passed. Record count from input register 9 to

drive 2 is made after shifting the corresponding group of samples through a group of valves 8 by a write pulse passing through the circuit 21 in the case of recording resolution. This impulse goes to the circuit And 18

19 and 20.

The reversible counters 10, 11 and 12 have the initial state (there is no count in the accumulator yet) 111 ... 1. If the priority device reads the I priority, then the valve group 15 and the AND 20 circuit are open and the contents of the counters 10 , 11 and 12 are decremented by one, and the count is recorded at the end of the priority group I. If a priority II count arrives at the device, then the valve group 14 and the circuit 19 are opened and, with a write pulse, the contents of counters 10 and 11 are reduced by one, and the count is recorded at the end of the priority group II counts. If a priority III count arrives at the device, then the valve group 13 and the circuit 18 are opened and the record impulse counter 10 decreases by one, and the count is recorded at the end of the priority group III and, therefore, at the end of the entire count queue.

For transmitting the samples to the transmitter 27, and then to the communication channel, a read pulse (I. read) is sent to the matching device, which, passing through the AND circuit 22, if the read resolution is enabled, shifts all information of drive 2 by one cell and on the right, the accumulator count is pushed into the transmitter. The order of location of samples in the drive described above ensures that there is always a count in the drive that needs to be transmitted first, then there is a count that needs to be transmitted second, etc. This same read pulse is fed to the inputs "plus reversible counters 10, 11 and 12 and increases their contents by one.

Thus, the reversible counters work in the following mode, they always contain the addresses of the cells in which the relevant readings of the corresponding priorities will be recorded in the matching device. The samples in the accumulator are always located in the sequence in which they must arrive at the communication channel, based on their importance (priority) and the sequence of arrival in the negotiator.

When, when reading information from any of the reversible counters, it reaches the state 111 ... 1, i.e., there is no priority data to which this reverse counter corresponds, the " plus counter is closed. This eliminates the possibility of data transfer to the accumulator in case a next impulse arrives in the counter at the input plus and the counter transitions from the state 111 ... 1 to the state 000 ... 0.

Prior to starting reading, priority code III is entered into priority bits by a priority code III write pulse (I. zap. To III rd), so that during reading, reversible counter 10, which corresponds to priority 11, is connected to address decoder 4. When the counter connected to the address decoder has a state of And ... 1,

the resolving potential is generated by the decoder on the right-most bus connected to the right-most cell of the drive. The same potential passage through the circuit

NOT 24 and the act is inverted on the circuit And 22, closes it, i.e. it prohibits reading. The read inhibit must be done through the decoder 4 by the reversible counter 10, since the priority data III always remains the last in the accumulator, and the contents of the counter 10 indicate the address of the end of the sample queue in the accumulator. In order to do this, priority code III is entered into the bits of the priority sign.

In the proposed device, a situation may arise when a new countdown arrives, a reversible counter corresponding to the priority of the countdown is connected to the address decoder 4, and the contents of the reversible counter

is 000 ... 0. This indicates that the drive is completely filled with data of the same priority and priorities higher. In this case, the address decoder generates a potential at the left-most output bus, which, having passed through the NOT 23 circuit, closes the AND 21 circuit. The write pulse to the device does not pass and the countdown will be lost, but all of the previously read samples of the same and higher priority at

the drive is saved.

Transmitter 27 serves to convert samples to a form convenient for transmission, and transmits them to the communication channel. The proposed device is built so

that it cannot simultaneously record and read information. These cycles should be separated by the telemetry control unit. All impulses (I. zap., I. lev.sdv., I. zap. To

III pr., And counts.), Controlling the operation of the device, should be developed by the telemetry complex control device. Moreover, the write and read cycles must be separated, and the left shift and write pulses must always arrive after the next significant reference has been written to the input register 9 sequentially at certain time intervals.

Claims (2)

1. A device for matching a stream of priority messages with a communication channel containing an input node, one group of outputs of which is connected to informational inputs of a storage device, to the address inputs of which the outputs of the address generator are connected via a decoder, and the outputs of the storage device are connected to the inputs of the transmitter, in addition, write pulses through the input node filed to the inputs “the priority sign of the address maker, and to the input“ minus this mapper - through the write blocking node, to the input of “negation of which the corresponding decoder output is connected, characterized in that, for the purpose of sort7 samples according to priorities, taking into account the categories of messages, a read blocking node and a zone selection node are entered into it, while the decoder outputs are connected to the "drive left shift input, to the read input and to the input" plus address generator An output "match of the read lockout node" is connected, the output "negation of which is connected to the corresponding inputs of the accumulator and the node for selecting the zone, and the readout pulses are applied to the control input of the read lock node, and eight PA control input node of the zone pick-pulses shift left. 2. Device for and. 1, that is, with the fact that the address driver is made in in the form of three reversible counters, the outputs of each of which are connected to the inputs of the output circuit OR through the corresponding group of valves, and the inputs “minus these counters are connected through the corresponding Circuits And with the inputs of the priority decoder, and inputs "plus" are interconnected and are input "plus the address resolver. L. I. counts. I I. zap.kZhpr. And .. n.3anp.c4vm.