SU1714612A1 - Data exchange device - Google Patents

Description

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the moment of recording information from the corresponding computer channels in all information registers of the device. The essence of the invention is that each computer can write information to its information register once per N device operation cycles. The recording of information from each computer into the information registers 2 of the device occurs simultaneously and

The invention relates to computing and can be used in digital computing systems and networks, data exchange systems between computers and the user.

A multi-channel communication device of a computing system is known, which contains ringed channels and a clock pulse generator, as well as an address register in each channel, three buffer registers, a control unit, a comparison circuit, two transmitting and two receiving registers, four groups of AND elements, and a generating unit directions and register constants. .

The disadvantage of this device is high hardware costs.

A device for information exchange is known, comprising two registers and an information exchanger, which contain M channels consisting of an information register and three multiplexers.

The disadvantage of such a device is the complexity of the process of organizing the exchange of information and, as a result, high hardware costs, low speed, the impossibility of simultaneous multilateral exchange of information in communication channels, inefficient use of equipment in the ring structure of a computing system.

The closest in technical, essence and achieved positive effect to the present invention is an information exchange device containing M channels, the first information input and output of the 1st channel (1 iTIvl) being the input and output devices for connecting the information output and the input of the 1st computer, the second information input of the 1st channel is connected to the second information input of the M-th channel, each channel consisting of a block of elements of the INRNI and the information register input connected to output of the block of elements AND-OR,

is identified by a counter 1 every N clock cycles per device operation cycle. Recorded information is continuously circulating in the information registers of the channel. In case of equality of the recipient's address recorded in the information register, the computer number reads information from the computer, in the channel of which the comparison takes place. 3 il.

the first information input of which is connected to the second information input of the channel, and the first control input is the input of the channel for connecting the first clock input of the device and on each channel the register outputs are connected to the second information output of the channel, the information input of the And block and the first inputs of the first and second comparison circuits, the second inputs of which are connected to the first information input of the channel and the second information input of the block of AND-OR elements, the second control input connected to the output n The first element And the output and control input of the block of elements And is connected to the first information output of the channel and the output of the second element And, the first inputs of the first and second elements And are the input of the channel for connecting the second clock input of the device, and the second inputs are connected to the corresponding outputs of the first and second comparison circuits.

The disadvantage of such a device is the high hardware costs due to the excessively large information register of each channel and the resulting connections.

Large hardware costs due to the fact that the issuance of information from the computer to the channel of the M-channel device occurs once per M device cycles when the source code of the information matches the number of the computer. In other cases, the source information code continuously circulates in all information registers without being read by the receiver.

The aim of the invention is to reduce the amount of equipment of the device.

The essence of the invention is that each computer can write information to its register once per N device operation cycles. The recorded information is continuously circulated in the information registers of the channels and with the equality of the recipient's address recorded in the register.

the computer number reads information from the computer in the channel of which the comparison has occurred. The recording of information from each computer into the channel information register occurs simultaneously and is identified by a counter every N clock cycles, i.e. for one cycle of the device.

The introduction of the counter and its connections allows identifying the moment of recording information into all information registers of the device from the corresponding computer channels. The introduction of switches and their connections allows to output information from computer channels to information registers in recording mode from a computer and from the channel register of a previous computer to a channel register of a subsequent computer in information census mode.

FIG. 1 shows a functional diagram of the proposed device; Fig. 2 shows the layout of the information in the channel register; Fig. 3 is a timing diagram of signals at the clock inputs of the device and the output of the counter.

The device contains a counter of 1 and N channels, consisting of information register 2, comparison unit 3, first 4 and second 5 switches, AND 6 block, second 7 and first 8 information outputs, first 9 and second 10 information inputs, as well as the first 11 and 12 second clock inputs.

Counter 1 counts the number of clock pulses and translates the device from the information recording mode from the computer to the device information registers in the mode of information exchange with the computer and back every N cycles - one device operation cycle. Information register 2 is a memory element of a device that performs the functions of receiving and storing information. Comparison unit 3 compares the recipient's address and computer number and, on the basis of this, controls the output of information from the information register to the computer channel.

The first 4 and second 5 switches transmit information from the computer to the information registers 2 from the first information input 9 of the device or the second information output 7 of the channel of the previous computer. The block of elements And carries out the issuance of information from the information register 2 in the computer. The second information output is used to issue information from the information register 2 to the second information input 10 of the subsequent computer channel. The first information output 8 and the input 9 of the device are designed to transmit information

from the device to the computer channel and accordingly for receiving information from the computer channel to the device.

The second information input 10 of the device is designed to receive information from the second information output 7 of the channel of the previous computer. The first 11 and second 12 clock inputs of the device are used to transmit pulses that synchronize the operation of the device from the computer. In this case, one clock pulse coming from the sync input of the channel on the second clock INPUT 12 of the device accompanies one information word,

15 coming from the computer (figure 2).:.

The device works as follows.

In the initial state, the current information is stored in the memory elements of the device — the information registers pax 2: the recipient's address and text (Fig. 2, the initial setup inputs are not shown).

The first clock pulse received from the channel sync input through

5 to the second clock input 12 of the device at the second control input of the block And 6 elements, allows reading information from the information register 2 at the first input of the elements And 6 into those computers whose number received by the device from the first information input 9 coincides with the code addressee stored in information registers 2.

When reading information from the information register 2, it is set to the zero state (the reset circuit of register 2 is not shown).

The falling edge of the first clock pulse from input 12 is counted by counter 1

0 (i.e., a one is added to the contents of counter 1), and if an overflow has occurred, a single signal appears at the output of counter 1. The overflow condition of counter 1 indicates that in

5, the device began the next cycle of operation, and a single potential at the output of the counter

Initializes the recording mode, i.e. transfer of information from computer channels through the first information inputs 9, via switches 4 and 5 to information registers 2. Received from the first clock input

II devices to the second control input of the switches. The 4 and 5 clock pulse produces a census of information located in the information registers 2 from the second information output 7 of the channel of the previous computer via the second information input 10 of the subsequent computer via switches 5 and 4 to the information registers 2.

The next clock pulse coming from the channel sync input via the second clock input 12 to the second control inputs of the And 6 blocks of cells allows reading information from information registers 2 if the computer number is compared with the address code stored in the information register 2 of the computer . At the same time, a single signal arrives at the first control input of the I 6 unit and information from the register 2 is transmitted to the computer channel via the second information output of the register 2, the information input of the And 6 element block, through the And 6 element block at the first information output 8 of the device. If the comparison does not take place, then the information from the information register 2 is transmitted via the second information output 7 of the channel to the second information input 10 of the next computer. The falling edge of the pulse input from the second clock input 12 to the contents of counter 1 is added to one, and if the counter is in the overflow state, it is set to zero.

A zero signal from the output of counter 1 prohibits the transfer of information from computer channels to information registers 2 for N clock cycles of the device, i.e. switches the device to the information reading mode (the reset circuit of counter 1 is not shown). Subsequent (N-1) -speak pulses coming from the first clock input 11 of the device are fed to the second control inputs of the switches 4 and 5 and rewrite the information in the information registers 2 according to the principle from the previous to the next.

If the required exchange of information between computers in one cycle of work cannot be done, then new information is entered from the computer channels to information registers 2 and another cycle is carried out.

Claims (1)

The invention is a device for the exchange of information, containing N channels, the first information input and output of which are the corresponding input and output of the device and connected to the information input and output of the corresponding computer, and the second information output of the 1st channel (, N-1) is connected to the second information input of the (1 + 1) -th channel, the second information output of the N-ro channel is connected to the second information input of the first channel, the first clock inputs of the channels connected to the first clock input of the device, each channel contains two switches and a unit with |, the first information inputs of which are connected to the first information input of the channel, the information register, the first and second information inputs of which are connected respectively to the outputs of the first and second switches, the second information and control inputs which connected to the second information input and the first clock input of the channel, and an AND block whose output is the first information output of the channel, the first and second outputs of the information register being connected respectively to the second information input of the comparison block and the information input of the AND block and forming the second information the output of the channel, which is tla and so that, in order to reduce the volume of the equipment of the device, a counter is entered into it, the input of which is the second clock input of the devices a and is connected to the clock inputs of the channels, the second clock inputs of which are connected to the counter output, and in each channel the first and second control inputs of the AND block are connected respectively to the output of the comparison block and sync channel input.