SU1443193A1 - Cyclic synchronization system - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the capacity of the communication channel during the transmission of slowly varying signals, not causing pauses. The frame synchronization system contains, in the transmitting part of Mr. 1, control pulses, a divider 2 frequencies, E-mails of the TRC signal or 3 and a transducer 4 of the parallel code into a series, and in the reception part of the memory block 5, the PLA is EXCLUSIVE OR 6 and Element I 7. In this frame synchronization system, the phasing of the receiving part is performed in the process of transmitting the information signal without using additional symbols in the transmission cycle. The goal is achieved by introducing the divisor 2 and the ELITE EXCLUSIVE OR 3 and 6. 2 Ш1.

Description

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The invention relates to communication technology, specifically to frame alignment devices, and can be used to synchronize over a cycle of devices for transmitting and receiving telemetry information transmitted in digital form.

The aim of the invention is to increase the capacity of the communication channel during the transmission of slowly varying signals without interruption.

FIG. 1 shows a frame synchronization system; Fig, 2 - timing charts of the system,

The frame synchronization system contains a generator of 1 control pulses, a divider of 2 frequencies per (ha + - n), K elements of the SSC 3, (where K is the number of bits to be inverted), 4 parallel code to serial converter, memory block 5 , 2K of the elements ISKHYUYACHEYE IZH 6 and the element I 7 "

The cyclic syncronization system works in the following way.

From the clock output of the generator 1 of the transmitting part, the clock pulses of the code advance are fed to the clock input of the converter 4 (Fig. 2a). From the output of the cyclic pulses of the generator 1 to the input of the rewriting pulses, the code of the transducer 4 is supplied with cyclic pulses of the rewriting of the code (Fig 26), with the help of which the code coming to its information BYPASSES is rewritten into the transducer 4. At the same time, 1 duplicate code rewrite pulses are fed to the input of divider 2, which can be made in the form of a binary counter with a reset to 0 when certain code states are reached. Fig. 2 shows a timing diagram of a pulse train at the output of a frequency divider, built on the basis of a binary counter with a reset with a frequency division factor of 3, At the moment of occurrence of 1 into input distributors 2 in bits J, .. K, which include the elements EXCLUSIVE PARTICIPATOR OR 3, an inversion is performed, as a result of which the code sequence (fig.2d) takes the form (fig.2d) „

The code sequence (FIG. 2d) is fed to the information input of a clocked memory block 5.

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the receiving part, where m + n cycles of the information signal are memorized, i.e. the whole cycle of sync information. With the help of the elements EXCLUSIVE OR 6, the values of the bits on the conjugate of the sync are compared under the sync information cycles. With equal values of bits at the compared points of the sync cycle, at the outputs of the elements of the Trial or 6 are set O, If at a comparison of 11K the sequence appears with the sequence Xj., X) and Xj ,,, X in accordance with the law of alternation, installed at the transmission, then the outputs of the TERMINAL SURFACE elements 6 arise 1, and the element 7 7 signals a signal (FIG. 2e) about which the receiving part is phased and the place of the inversions is determined, which are then inverted to restore their original values eny,

As a result of this construction of the frame synchronization system, the phasing of the receiving part is performed during the transmission of the information signal without using additional symbols in the transmission cycle.

Claims (1)

Invention Formula The frame synchronization system, which contains a parallel code converter in the last part in the transmitting part, to the clock input and rewriting input of the code of which the corresponding outputs of the control pulse generator are connected, and in the receiving part - the memory unit and the AND element, which differs from In order to increase the bandwidth of a communication channel when transmitting slow-moving signals, not having pauses, a frequency divider of (m + n) (where type is integer numbers and m and n) and K-elements of the FRONT HOLE or (where K - The number of bits subjected to inversion), the information inputs of which are the information inputs of the transmitting part of the frame synchronization system, the output of the frequency divider is connected to the control inputs (m + n) and the outputs of the elements of the ULR1.1 | EE OR are connected to the corresponding inputs parallel code converter to pos-31443193 The research, the other entrances of which the receiving part is entered 2K elements of the go are the information inputs EXCEPT 11EE IDE, to the inputs of which the corresponding g outputs of the memory unit are connected, and the outputs are connected to the inputs of the AND element, the output of which is the output of the receiving part of the frame synchronization system. the transmitting part of the frame alignment system, while the input of the frequency divider is (m + n; the output of the pulses is rewritten from the code of the generator of the control pulses, and o) I it I I I 1 I I I I I I I I I I I 1 I I I I I I I I I I I I I I 1 I M I I I I I rfl J tI l |. c) I1 I Z) X | ... X | j.Xj. ..K; Ai ..X.Xj ... Xj} (H-: X ... X.Xj. ..Xj X ... X | j.Xj ... Xj XN- .X.Xj ... Xj-X ... .X.Xj. Xj X, ... -Xj X ... X.Xj .. -Xj X ... Xj.X; ..Xj X ... X.Xj. ..Xj Xd, .., X.Xj ... Xj one .. tTf 1T, -uuir / i indyurhythm futHoaa. |. Tj zsht transmission synxoin ornlchii