SU843301A1 - Device for shaping frame synchronization signal - Google Patents

Description

, (54) DEVICE FORMATION OF A HUMAN SYNCHRONIZATION SIGNAL

The invention relates to a television technology and can be used in receiving devices for frame (cyclic) synchronization of image transmission systems, telemetry, using the transmission decrypted on the receiving side of a sync pattern (code marker). It is known a frame synchronization signal generating device comprising a sync pattern decoder, the information input of which is intended for supplying a sync pattern code combination, a cycle length counter, the counting input of which is intended for supplying symbol frequency pulses, and the output of which is connected to the first input of the first And element, the second input of which is connected with the output of the sync group decoder, the delay unit. And the second element And, the output of which is connected to the reset input: sa loop length counter Dl The main disadvantage and Vestn device is the low noise immunity. The purpose of the invention is to increase the noise immunity of the device for forming a frame synchronization signal. The goal is achieved by the fact that a sync group decoder, the information input of which is intended for supplying a synchronization pattern, a cycle length counter, the counting input of which is intended for pulsing a frequency, and the output of which is connected to the first input the first element And, the second input of which is connected to the output of the decoder of the Sikh group, the delay unit and the second element And, the output of which is connected to the reset input of the length counter cycle introduced a shift register, a first

the input of which is connected to the output of the first element I, and the second input to the output of the cycle length counter, the set-up unit, the output of which is connected to the third input of the shift register, the control decoder, the inputs of which are connected to the outputs of the shift register, the first output connected to the first the input of the third element is And, and the second output with the first input of the fourth element And, while the second inputs of the third and fourth elements And connected to the output of the loop length counter, the first element OR, the first input of which is connected to the output The first element is And, the second input is with the output of the third element And, the third input is with the output of the second element And, and the output with a delay unit whose output is connected to the first input of the trigger, the second element OR, the first input of which is connected to the output of the fourth element And, the second input - with the output of the setup unit in the initial state, and the output - with the second trigger input, the output of which is connected to the first input of the second element I, the second input of the second element I is connected to the output of the sync decoder, the clock input predna is intended for pulsing the symbol frequency.

The drawing shows a device, a scheme for forming a frame synchronization signal.

The device contains a decoder 1 sync group with information input 2 and input 3 pulses of the symbol frequency, counter 4 cycle length, element AND 5, trigger 6, element OR 7, block 8 delay, element OR 9, element AND 10, block P set to the initial state element, elements 12 and 13, the decoder 14 control and shift register 15, the output device

b;

The framing signal shaping device operates as follows.

When the device is turned on, the setup unit 11 in the initial state generates a pulse, which zeroes the shift register 15 and flows through the second element OR 7 to the second input of the trigger 6, sets it to the state that opens the second element AND 5. Then the pulse response is depressed. ,

of a sync group torus 1 to a sync group type code combination, arriving at its input from information input 2 and gated with symbol frequency pulses from input 3, passes through the second element 5, transmits to the first (reset) input of counter 4 of the loop length and sets it to zero the position, in addition, through the third input of the first element PfflH 9 and the delay block 8, returns the trigger 6 to the state by closing the second AND 5, which will be closed for a time equal to the length of the frame synchronization cycle. The counter 4 of the cycle length, counting the number of pulses of the symbol frequency, arriving at its counting input from input 3 and equal to the frame length, generates a pulse at the end of the cycle, which is fed to the input of the first element 12 and the first inputs of the third and fourth elements 13 and 10, on the shift input of the register 15 shift. Since in register 15 there are zeros in all bits, the output of control decoder 14 connected to the input of the fourth element AND 10 will have a signal opening the fourth element 10 and passing the end of the loop through the second element 7 of the trigger 7, which opens the second element and 5.

If the first response of the decoder 1 was true, i.e. If the shaft is in a temporary position in the cycle to the frame sync signal, then the cycle must be repeated at the same position of the cycle, and then the first element I 12 will match the response of the decoder 1 and the cycle pulse from the output of the counter 4 cycle length. The coincidence signal from the output of the first element AND 12 through the first element OR 9, the delay block 8 arrives at the trigger 6 and returns it to the state closing the second element 5, and also enters the first (informational) input of the shift register 15, as a result, a unit is recorded in the first discharge register 15.

Claims (1)

If the first response of the sync group decoder turned out to be false, then the counter impulse pulse 4 through the cycle passed through the fourth fourth element AND 10 (in register 15 are still only zeros), the second element OR 7 sets the trigger 6 and Since the signal of the first element of IL 9 does not come to the signal, then element I 5 remains open until the new response of the decoder 1 of the synchronous circuit passes through it, which sets the new phase of the counter 4 of the cycle length and returns the trigger .6 through the first element of SHS and block 8 per The holders in the position closing the second element AND 5. When the responses of the decoder 1 of the synchro-group arrive regularly at the same position of the cycle (synchronism is found), then from the output of the first element And 12 regularly impulses come that support the trigger 6, the state closing the second element AND 5, and in addition, these pulses, arriving at the first (informational) input of the shift register 15, fill the register 15, moving along the register, using pulses from the output of the counter 4 of the cycle length which are regularly fed to the second (shift) input reg Example 15. When units appear in all bits of register 15 (or units as many as specified by the decisive synchronization rule), the output of control decoder 14 connected to the third And 1 element shows a signal that opens the third And 13 element, which trigger 6 constantly keeps the second element AND 5 closed, preventing it from changing the phase 4 of the cycle length. Thus, the device is in sync, its frame 1 output regularly receives frame synchronization pulses, and the shift register 15 monitors the synphase of the responses of the decoder 1 sync group and output counter pulses of 4 dpins of the cycle. If they do not match (the synchronism layer), the shift register 15 will begin to empty out, since the shift pulses from counter 4 of the cycle length pass, and the pulses do not coincide with the output of the first element I 12. At that moment, when the unit less in the shift register 15 than is determined by the decisive rule, the control decoder 14 closes the third element And 13 and the device switches to the intermediate mode. If the arrival of signals from the first element And 12 is resumed, the device will return to steady synchronization mode, if. The register 15 shift is emptied completely then the device will go into search mode. The use of newly introduced elements — the shift register, the control decoder, the third and fourth elements AND, the first and second elements OR, and the installation unit to the initial state, as well as the proposed connection of elements in the device give the proposed device a higher noise immunity than the known one. This is due, firstly, after passing the response from the output of the SIN5FOGROUP decoder to the phasing of a 1L1) 1 cycle counter, the second electrical element AND closes for the next cycle with the same pulse that goes to the reset input of the cycle length counter, through the third input of the first element IJTM and the delay unit sets the trigger to the position closed by the second element I. As a result, in the process of searching for synchronism, the faerization of the loop length counter will not be lost. Secondly, the presence of a scheme for tracking the state of synchronism in the form of a shift register and a control decoder makes it possible to avoid synchronization failures during short-term interruptions of marker sync groups and with the arrival of false sync groups. . The invention of the frame synchronization signal shaping device, comprising a sync group decoder, the information input of which is intended for supplying a synchronous code pattern, a cycle length counter, the counting input of which is intended for. pulse symbol frequency, the output of which is connected to the first move of the first element And the second. the course of which is connected to the output of the synchronization group deflector, the delay unit and the second element I, the output of which is connected to the reset input of the counter of the loop gap, by which, in order to increase the noise immunity, the first shift input