SU1124278A1 - Information output device - Google Patents

Abstract

1. DEVICE FOR EXTING INFORMATION, containing the first group of registers, memory block, interface blocks, first group of counters, inputs of the first group of memory block and inputs of registers of the first group are information inputs of the Device Group, the first outputs of the interface blocks are outputs Devices, characterized in that, in order to improve the performance of the device, the second group of registers, the control unit, the first, second, third and quarter multiplexers, the first and second counters, the first and second decipher are entered into it tori, the outputs of the latter are connected respectively to the fifth inputs of the interface blocks, the second outputs of which are connected to the inputs of the first group of the third multiplexer, the outputs of which are connected to the inputs of the second group of the control unit, the inputs of the third group of which are connected to the inputs of the fourth group of the third multiplexer, the inputs of the second group the second multiplexer, the outputs of the first counter, the inputs of the second decoder group and the inputs of the third group of the first multiplexer, the outputs of which are connected to the inputs of the second The memory blocks, the outputs of which are connected to the inputs of the first group of the fourth multiplexer, the output of which is connected to the third inputs of the interface blocks, the first inputs of which are connected to the fourth output of the first decoder and the first input of the second counter, the outputs of the KOTCJroi are connected to the inputs of the second group of the fourth multiplexer and the inputs of the first decoder, the first output of which is connected to the fourth inputs of the interface blocks, the seventh inputs of which are connected to the sixth output of the control unit, the first of which is connected Not with the second output About the first decoder, the third output of which is connected to the sixth inputs: yes the interface blocks and the second input of the control unit, the third output of which is connected to the input of the second decoder, the last output of which is connected to the third input of the control unit, the fourth the output of which is connected to the second inputs of the t ch1 interfacing blocks, the eighth inputs of which are connected respectively to the first x outputs of the second registers of the group, the second outputs of which are connected respectively to the outputs of the first counters of the groups The outputs of which are connected to the inputs of the first group of the second multiplexer, the outputs of which are connected to the inputs of the second group of the first multsexor, the inputs of the first group of which are connected to the inputs of the first group of the control unit and are the address inputs of the device group, the second input of the second counter with the fifth output of the unit management

Description

: the third output of which is connected to the input of the first multiplexer and the first input of the first counter, the second input of which is connected to the first output of the control unit, the seventh output of which is connected to the input of the memory unit, the inputs of the second group of the third multiplexer are connected respectively to the outputs of the first group of registers, the outputs of the group which are connected respectively to the inputs of the registers of the group; the outputs of the group of which are connected to the inputs of the third group of the third multiplexer; the outputs of the first group of the control unit are connected respectively with the first inputs of the registers of the first group, the second inputs of which are connected respectively to the outputs of the third group of the control unit, the outputs of the fourth group of which are connected respectively to the first inputs of the registers of the second group, the second inputs of which are connected respectively to the inputs of the fifth group of the control unit, outputs of the sixth the groups of which are connected respectively to the second inputs of the counters of the group, the third inputs of which are connected respectively to the inputs of the seventh group of the control unit, the inputs of the second group, the second output, the fourth and fifth inputs of which are, respectively, group breakout outputs, response output, recording input and input of device settings.

2. A device according to claim 1, characterized in that the control unit comprises first and second decoders, a multiphase generator, a frequency divider, a first, a SECOND, a third flip-flops, a peevy, a second, a third and a fourth elements OR,

The first, second, third, fourth, fifth, sixth, seventh, eighth and ninth elements are AND, the first, second, third, fourth, fifth and sixth demalplexers, the outputs and inputs of the group of which are respectively the second, third, fourth ,, the sixth and seventh groups and the inputs of the third group of the block, the first output of the multi-phase generator is connected to the input of the frequency drainer, the second input of the decoder, | the input of the second trigger and is the first output of the block; the second output of the multi-phase generator is connected to the third input of the second element And and the second

the input of the fifth element And whose output is connected to the input of the third demultiplexer, the third output of the multiphase generator is connected to the second inputs of the seventh and eighth elements And whose outputs are connected respectively to the inputs of the fifth and sixth demultiplexers; the fourth output of the multiphase generator is connected to the second inputs of the fourth and the sixth And elements and is the fourth output of the device, the inputs of the i group of the first and second decoders are the inputs of the first group of the block, the first input of the first element And is with the second input of the block, the first input of the first decoder, the input of the second decoder and the R input of the first trigger are the fourth input of the block, the R input of the third trigger is the third input of the block, the first input of the ninth And element and the second input of the third And element are the first input of the block, the second input of the ninth element And, the fourth input of the sixth element And, the first and second inputs of the second element OR, are the inputs of the second group of the block, the second inputs of the third and fourth elements of the SH are the fifth input of the block, the outputs of the first decryptra Pa are connected to the inputs of the group of the first element ORI are the outputs of the first group of the block, the output of the first element OR is connected to the 5 input of the first trigger, the direct output of which is the second output of the block, the inverse output of the first trigger AND the output which is connected to the 5-input of the second trigger, the output of which is connected to the input of the first element OR and is the seventh output of the block, the output of the first element I is the six output of the block, the output of the frequency divider is connected to the second input of the first el And the 5th input of the third trigger is the fifth output of the block, the third output of the third trigger is connected to the first input of the third element And is the third output of the block, the second output of the decoder is connected to the second input of the BTopqro element I, the fourth the input of which is connected to the inverse output of the third trigger, the output of the third element And | connected to the first inputs of the fourth, fifth, sixth, seventh and eighth elements And, the third input of the last one is connected to the inverse output of the second element OR, the direct output of which is connected to the third input of the seventh element And, the second input of the second element OR is connected to the third input of the sixth element AND and the third input of the ninth element AND, the output of which is connected to the input of the first demultiplexer, the first input of the second element OR is connected to the third inputs of the fifth and fourth elements AND, the output of the last is connected to the first input the house of the third OR element, the output of which is connected to the input of the second de-multiplexer; the output of the sixth element AND is connected to the first input of the fourth OR element, the output of which is connected to the input of the fourth demultiplex.

The invention relates to computing and can be used to organize the output of arrays of information, presented in the form of serial codes from a digital computer through a communication line to external subscribers.

A device is known for transmitting information from a digital computer to a communication line containing a trigger, a group of elements And, a direction selection register, an information register, a switch, a decoder and a pulse generator Cl)

The drawbacks of the device are low autonomy, the need for constant loading and control of the device by the digital computer. In addition, such a construction of the device necessitates the conversion of arrays of information to be output in a special form, i.e. in parallel codes Consisting of certain bits, the words to be output. This reduces the performance of the computing complex.

The closest in technical essence to the present invention is a device for outputting information, comprising a buffer memory, a group of shift registers, a shaper of clock pulses, interface blocks, a control memory and AND elements, the inputs of the control and buffer memory are connected to the digital computer buses and are the inputs of the device, the buffer code is connected to the inputs and shift registers, the outputs of which are connected via inputs to the inputs of the gateways. The outputs of the interface nodes are the outputs of the device 12 3.

The drawbacks of the device are the low autonomy of the device due to the need to input a large amount of information into the control memory when setting up, as well as low bandwidth, caused by the presence of only one communication channel, which reduces the performance of simultaneous servicing of several subscribers.

The purpose of the invention is to improve the performance of the device.

The goal is achieved

In that the information input device containing the first group of registers, the memory block, the interface blocks, the first group of counters, the inputs of the first group of the memory block and the inputs of the registers of the first group are information inputs of the device group, the first outputs of the interface blocks are device outputs, the second group is additionally entered

registers, control unit, first, second, third and fourth multiplexers, first and second counters, first and second decoders, the outputs of the latter are connected respectively

with the fifth inputs of the interface blocks, the second outputs of which are connected to the inputs of the first group of the third multiplexer, the outputs of which are connected to the inputs of the second group of the block

control, the inputs of the third group of which are connected to the inputs of the fourth group of the third multiplexer, the input and the second group of the second multiplexer, the outputs of the first counter, vhog

The second desh band and the inputs of the third group of the first cultivator, the outputs of which are connected to the inputs of the second group of the memory block, the outputs of which are connected to the inputs of the first group of the fourth multiplexer, the output of which is connected to the third inputs of the interface blocks, the first inputs of which are connected to the fourth the output of the first decoder and the first input of the second counter, the outputs of which are connected from the input of the second group of the fourth multiplexer and the inputs of the first decoder, the first code of which is connected to the fourth by the inputs of the interface blocks, the seventh inputs of which. connected to the sixth output of the control unit, the first input of which is connected to the second output of the first decoder, the third output of which is connected to the sixth inputs of the interface blocks and the second input of the control unit. The third output of which is connected by the input of the second decoder, after which the output is connected to the third input of the control unit, the fourth output of which is connected to the second inputs of the interface units, the eighth inputs of which are connected respectively to the first outputs of registers of the second group, the second outputs of which are connected respectively, with the inputs of the counters of the first group, the outputs of which are connected to the inputs of the first group of the second multiplexer, the outputs of which are connected to the inputs of the second group of the first multiplexer, the inputs p which group is connected to the inputs of the first group of the control unit and are the address inputs of the device group, the second input of the second counter is connected to the fifth output of the control unit, the third output of which is connected to the input of the first multiplexer and the first input of the first counter, the second input of which is connected to the first the output of the control unit, the seventh output of which is connected to the input of the memory unit, the inputs of the second group of the third multiplexer are connected respectively to the outputs of the registers of the first group, the outputs of which are are connected respectively to the inputs of the second group of registers, which troupe outputs connected to inputs of the third group of the third multiplexer, the outputs of the first group of the control unit are respectively connected to the first inputs.  78-4 registers of the first group, the second inputs of which are connected respectively to the outputs of the third group of the control unit, the outputs of the fourth group of which are connected respectively to the first inputs of the registers of the second group, the second inputs of which are connected respectively to the inputs of the fifth group of the control unit, the steps of the sixth group of which are connected respectively, with the second inputs of the Group's counters, the third inputs of which are connected respectively to the inputs of the seventh group of the control unit, the inputs of the second group, the second output, the fourth and The fifth inputs of which are respectively a group interrupt output, a response output, a recording input and an input of device settings.  The control unit contains the first and second decoders, a multiphase generator, a frequency divider, first, second, / third triggers, first, second, third and fourth elements OR, first, second, third, fourth, fifth, sixth, seventh, eighth and Nine elements AND, first, second, third, fourth, fifth and sixth demultiplexers, the outputs and inputs of the group which are respectively the outputs of the second, third, fourth, fifth, sixth and seventh groups and inputs of the third group of the unit, the first output of the multiphase generator soy;: nen with the entrance of affairs frequency bodies, the second input of the decoder, the R-input of the second trigger and is the first output of the block, the second output of the multiphase generator is connected to the third input of the second element And the second input of the fifth element And whose output is connected to the input of the third demultiplexer, the third output of the multiphase generator connected to the second inputs of the seventh and eighth elements And, the outputs of which are connected respectively to the inputs of the fifth and.  the sixth demultiplexer, the fourth output of the multiphase generator is connected with CO by the second inputs of the fourth and sixth And elements, and is the fourth output of the device, the inputs of the first and second decoder groups are the inputs of the first group of the block, the first input of the first element of And is the second input of the block, the first input, the first decoder, the input of the second decoder and the R input of the first trigger are the fourth input of the block, the R input of the third T1 igger is the third input of the block, the first input of the ninth And element and the second input of the third And are the first input of the block, the second input of the ninth And element, the fourth input of the sixth. And, the first and second inputs of the second element OR are the inputs of the second group of the block, the second inputs of the third and fourth elements of OR are the fifth input of the block, the outputs of the first decoder are connected to the inputs of the group of the first OR element and The first element SH is connected to the 5-input of the first trigger, the direct output of which is the second output of the block, the inverse output of the first trigger is connected to the first input of the second element I, the output of which is connected to the 5-input the second trigger, output to The second is connected to the input of the first element OR and is the seventh output of the block, the output of the first element I is the sixth output of the block, the output of the frequency divider is connected to the second input of the first element AND, the 5 input of the third trigger and is the fifth output of the block the direct output of the third trigger is connected to the first input of the third element I and is the third output of the block, the output of the second decoder is connected to the second input of the second element I, the fourth input of which is connected to the inverse output of the third trigger, the output of the third ele And is connected to the first inputs of the fourth, fifth, fifth, sixth, seventh and eighth elements AND, the third input of the last is connected to the inverse output of the second element OR, the direct output of which is connected to the third input of the seventh element And, the second input of the second element OR is connected with the third input of the sixth element And and the third input of the ninth element And whose output is connected to the input of the first demultiplexer, the first input of the second element OR is connected to the third inputs of the fifth and fourth elements And, the output of the last connected to the first The third input of the OR element, whose output is connected to the input of the second demultiplexer, the output of the sixth element AND is connected to the first output of the fourth OR element, the output of which is connected to the input of the fourth demultiplexer.  The device (FIG. 1) contains block 1 of memory, first 2, second 3, third 4, fourth 5 multiplexers, outputs 6 ,. . . 6.  third multiplexer, group of first registers 7,. . . , 7, with exits 8j,. . .  , 8th first bits, group of second registers 9,. . .  , 9, with exits 10,. . . , 10 first bits, group of counters 11 ,. . . , 11, the first counter 12 channels with outputs 13, the second counter 14, the first decoder 15 with the outputs 15 ,. .  . , 15, the second decoder 16 with outputs 16 ,. . . , 16, blocks 17 ,. . . .  , 17 mates with exits 18 ,. . . , 18 data and 19- ,,. . . , 19 "serial code, control unit 20 with output signals 20 | ,. . . , 20g control, signals 21 ,. . . , 21 downloads the first registers 7, signals 22 ,. . . , 22 interrupts, signals 23,.    23, zeroing of the first registers 7,, signals (load the second registers 9 |, signals o6i of the second registers 9, signals 26 ,. . . , 26 downloads counters 11 groups, signals 27 ,. . . , 27 adding single counters 11group and signal 28 Response (WDM).  In addition, in FIG. 1 shows information inputs 29, address inputs 30, recording signal input 31, and device setup signal input 32.  .  Block 17 (FIG. 2) the interface contains a data trigger 33, a counting trigger 34, a multiplexer 35, elements 36, 37A, and a bipolar code modulator 38.  Block 20 (FIG. H) control contains the first decoder 39, a multi-phase generator 40, a frequency divider 41, first, second and third triggers 42, 43 and 44, first, second, third elements 45 - 48 OR, first, second, third, fourth, w , sixth, seventh, and eighth.  the ninth elements 49-57 And, the second decoder 58; the first, second, third, fourth, fifth, and sixth demultiplexes 59-64.  FIG. 4 shows the signal 15.  The end of the word. , . signal 152 - reset cycle, signal 15.  pauses, signal 154 End of cycle, signal 20, frequency divider 41, signal 20, output code synchronization, and bipolar output serial codes 19,. . . ,nineteen,.  FIG. 5 shows signals 6,.  . .  at the outputs of the multiplexer 4, the signal 15 reset cycle, the signals 16 ,. . . , 16 sampling channels, signals 20 ,, 22;,. . . 27  , at the outputs of the control unit 20, the signals at the inputs 29 and. 30, the recording signal 31.  Memory block 1 is designed to receive information from the digital computer via inputs 29 and its storage, multiplexers 2, 3 are used to connect various sources of addresses to the address inputs of memory block 1.  The data multiplexer 5 is designed to select from the word of information (serial code bit) read out in memory block 1, output through the interface block 17 in the next cycle.  Registers 7- are used to receive, from the digital computer, inputs 29 of the setup codes defining the operating modes of the respective communication channels.  The registers are designed to store setup codes and control the appropriate communication channels during operation (output information). Counters 11 are used to form addresses (numbers) of output serial codes.  The counter 12 and the decoder 16 provide a choice of the communication channel currently being serviced during their setup and loading of the conjugation blocks 17.  Counter 14 and decoder 15 ensure the formation of a predetermined duration (number of pulses) of successive codes and a pause — the time interval between two codes.  The multiplexer 4 is designed to select and transmit to the control unit 20 control signals that determine the mode of operation of the served channel.  Blocks 17, the mates are designed to receive and store the pulse transmitted in the sequential code (discharge) of the sequential code, generate the check bit of the sequential code, and convert the information into bipolar form.  The control unit 20 controls the formation of control signals and synchronizing signals (bots of elements and nodes of the device).  The principle of operation of the device consists in sequential reading from the memory block 1 of the words output via the corresponding channels, loading the corresponding word bits into the 17-conjugation blocks with the subsequent simultaneous formation of bipolar signals on the communication lines.  In this case, the load of the conjugation blocks is performed during the period of the zero (passive) level of the output code signal synchronization 20, and the formation of bipolar code bits on the communication lines during the period of the single (active) level of the signal 20.  Channel reconfiguration - changing the address of the output words, changing the modes of operation - makes -.  c at the moment of pause between two words.  The multiphase generator 40 of the control unit forms a cyclic pulse train (see  FIG. 5) 20, . . , 20, which synchronizes the operation of the device nodes and elements of the control unit 20.  The pulse 20 is fed to the input of the frequency divider 41, made, for example, on the basis of a counter, which generates clock pulses 20d at the output, the frequency of which corresponds to the required transmission frequency of the bits of the serial code, for example, 50 KHz at a duty cycle of 2.  The pulses 20 are fed to the counting input of the counter 14 cycles, in addition, by dropping the pulses 20, the trigger 44 is set to one state.  The counter 14 and the decoder 15 set the cyclogram (see  FIG. 4) transmission codes on the communication line.  For example, with 32-bit codes and a pause duration equal to four clock cycles, the transfer of codes per line is carried out with codes O ,. . . , 31 in the clock counter, and with code 31, the check bit is transmitted, and with codes 32 ,. . . , 35 a pause is formed. At the first output of the decoder 15, a signal 15 is generated with code 31 in counter 14, which determines the moment of transmission on the link of control bits, on the second, the signal 152 of PP code 32 in counter 14, which determines the moment of reconfiguration of channels, at the third output signal 15 with codes 32 ,. . . , 35, defining the pause duration, on the fourth - signal 15 with code 36, which ends the single word transmission cycle and zeroes the counter 14 is loaded. Loading of the conjugation blocks 17 with information to be output through the corresponding channels, as well as reconfiguration of the channels is performed trigger state 44, whereby the load is carried out in the absence of a signal 15, a pause, and reconfiguration in the presence of a signal 15 ,.  Each channel of the device in memory block 1 is allocated an array of memory cells from which information can be output.  The array number corresponds to the channel number and is determined by code, for example, in the higher address bits.  The number of the word in the array is determined by the lower-order address bits.  The channel loading cycle consists of reading information from memory block 1, entering it into triggers 33, 34, block 17, mating and changing the contents of counter 12.  After removing the signal 20.  zeroing, the first channel is loaded.  In this case, the decoder 16 generates a load enable signal 16 of the first channel, which enters block 17.  A read is made from memory cell 1 with the address made up by the code of the counters 12 of the channel and 11 words of the first channel, which is fed to the address inputs of the memory through multiplexer 2.  Control of the transfer to the output of the multiplexer 2 codes from the second and third groups of inputs is carried out by a single signal level of 20g.  Through multiplexer 5, one of the bits, the number of which is determined by a counter code of 14 cycles, is fed to the inputs of the flip-flops 33, 34 and entered. they signal 20.  The front of the next signal 20 changes the channel number code in the counter 12, loads the next channel, and so on. d.  After loading the last channel by dropping the signal 16, the trigger 44 of the control unit 20 is zeroed, blocking the operation of the decoder 16 and resetting the counter 12.  The trigger 33 performs the reception and storage of a serial code bit in the Transmit Pulse, the trigger 34 modulo 2 bits of the code. And the latter, for example, the 32nd time, is not taken into account when summing up, is not connected to the communication line and .  The presence of a unit in this bit of a word read from memory 1 indicates that this word is the last word of the array to be output on this channel.  On line 19.  instead, the value of the mod 2 sum is output from trigger output 34.  The moment of issuing the last bit is determined by the signal 15, blocking through the circuit; 37 And the input to the trigger 34 and the control multiplexer 35, through which sequential bits arrive at the information input of the modulator 38.  code.  The moment of formation of bipolar signals at the outputs of the modulator is determined by the unit level of the signal 20 at the synchronization input of the modulator 38.  The output of information on the channel (modulator operation) may be blocked by a signal 10, for example, by a low level.  The loading of the triggers 33, 34 in the interval of the pause is blocked by the signal 15.  The preparation of the block 17 for maintenance of the operation (resetting the previous value of the sum mod 2) is carried out by the signal 15 simultaneously with the counter being reset to 14 cycles.  After turning on the power from the digital computer, the installation signal 32 is supplied to the unit 20 in the period of the next loading cycle, and the demultiplexers 60 and 62 generate the signals 23. , . . , 23 and 25 ,. . . , 25 register reset 7.  and 9. , this blocks the operation of the modulators 38 and the transmission of information on the communication line.  The digital computer inputs the data arrays through the inputs 29 into the 1 st unit, while the address from the outputs 30 through the first group (1) of the multiplexer 2 inputs goes to the address inputs of the memory 1.  At the same time, the decoder 5g, which determines the actuation of the address inputs to 30 to the address array of the memory unit 1, sets in one state the trigger 43, which generates the recording signal 20 in the memory unit 1.  Writing to memory block 1 is blocked during the period of loading channels by a signal from the output of trigger 44, which prohibits triggering element 43 through element 50 and trigger 43.  The trigger trigger 43 is synchronized by the signal 202 of the generator 40 111 through the element 50 I.  At the same time, the signal 20- is set to one state, through element 45 OR trigger 42, which generates a signal 28 Response to the digital computer, while restarting trigger 43, which is set to zero state at the end of recording by block 20, is blocked.  The trigger 42 is zeroed out at the end of the exchange with the digital computer, removing the signal 31 of the recording.  After preparing in block 1, the arrays of information for outputting the digital computer load the tuning codes into registers 7; channel settings.  In this case, the codes received from the inputs 29 are inputted into the registers 7 by the signals 21-, which are formed by the decoder 39 of the control unit 20.  The signals 21 are synchronized by a signal 20, which is fed to one of the control inputs of the decoder 39.  The exchange procedure with a digital computer is the same as when writing to memory 1.  When writing to the register 7, the settings of its first bit are set to one, and the unit signal level is 8.  at its output in the period of the next signal 13, causes a channel reconfiguration.  The first bit of registers 9.  the control is set to one when writing to these registers, the single state of the signals of the outputs of the registers 9.  permits operation of the corresponding blocks 17, - mates.  The second bit of registers is 7, and 9.  determine the page number in the memory array of the corresponding channel, from the first cell of which the output of information begins.  Each channel's memory cell consists of two pages.  The output of information can start from the first cell of any page, while in the process of outputting information from the cells of one page, the memory cells of the second page can be loaded with information from the digital computer.  Thus, an array of data is prepared for the output and information is transmitted to the channel output simultaneously.  Third register bits 7.  and 9.  The modes of operation of the corresponding channels are determined, for example, with a single code in these bits, information is once output from memory block 1 via the communication line 19 8 of the corresponding channel, and with zero cyclic (continuous) output.  Fourth register bits 1.  and 9-determine the need to form, for example, with a single code, an interrupt signal for the DVR program that is generated when the last word of the array is output.  The multiplexer 4 selects one of the control registers 9 during the tuning process and transfers its bits to the control unit 20.  If during the validity period of signal 15 (reset cycle) the first bit of register 7 is in a single state, signals 24 are generated, register loading 9 | management, 26.  counter load 11- and 23-reset register 7, -.  In this case, the setting code from the register 7.  is overwritten into register 9-, the page number code from the first digit of register 9 to the most significant bit of counter 11. -, the remaining bits of the counter 11 are zeroed out, and the register is zeroed, t. e.  it is being prepared to receive the following setup code.  In the zero state of the first register bit 7 in the tuning cycle, the unit is added to the content of the corresponding Counter llj by the signal 27.  and the address of the word that is output via the channel in the next cycle is prepared.  However, if, in addition, the trigger 33 of the block 17 of the conjugation is in a single state, t. e.  The last word output by the channel is the final word of the specified array, performed or resetting the register 9. .  control signal 25- with single output mode, or reloading the counter. 11 signal 26, 5 continuous output mode.  Interrupt signals are generated in the reset cycle with unit codes in the corresponding quarter bits of registers 9, and in the triggers 33 of the junction blocks 17j of the corresponding channels.  Signals 20.  the synchronization of the modulators 38 are formed by the AND circuit 49 and represent the clock pulses 20g of the frequency divider 41, the arrival of which is blocked in the interval of the pause by the pause signal 15j.  The interrupt signals are generated by the circuit 57 And and arrive at the corresponding bus digital computers through the demultiplexer 59, which selects the bus depending on the number of the channel served.

The remaining control signals are formed by the circuits 46,.,., 48 OR and 5-1, 53,. ,, 57 And are distributed to the control inputs of the device elements by demultiplexers 60, ..., 64

Thus, the device allows simultaneous transmission of several arrays of information to different subscribers. At the same time, unlike the prototype, which is a basic device, which uses several control memory cells ff 23, iit, 2S, 27, fOr for each output word.

and requires several write operations to them of the tuning (controlling i) code from TSB1, in the proposed device the process of tuning

the channel is reduced to a single write operation in the corresponding output settings register of the entire information array. In addition, the device provides the opportunity for the DVR simultaneously with the information output process over communication channels, which is carried out asynchronously and does not require the intervention of the DVR, to produce next-to-one arrays

information in the device’s memory

the process of calculating them, not waiting for the end of the transfer of the previous arrays "

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Claims (2)

1. A DEVICE FOR INFORMATION OUTPUT, comprising a first group of registers, a memory unit, interface units, a first group of counters, inputs of a first group of memory unit and inputs of registers of a first group are information inputs of a device group, the first outputs of interface units are device outputs, characterized in that , in order to improve the performance of the device, it introduced a second group of registers, a control unit, the first, second, third and fourth multiplexers, the first and second counters, the first and second decoders, the outputs of the latter are connected respectively to the fifth inputs of the interface units, the second outputs of which are connected to the inputs of the first group of the third multiplexer, the outputs of which are connected to the inputs of the second group of the control unit, the inputs of the third group of which are connected to the inputs of the fourth group of the third multiplexer, the inputs of the second group of the second multiplexer, the outputs the first counter, the inputs of the group of the second go decoder and the inputs of the third group of the first multiplexer, the outputs of which are connected to the inputs of the second group of block RAM memory, which outputs are connected to the inputs of the first group of the fourth _multiplexer? the output of which is connected to the third inputs of the interface units, the first inputs of which are connected to the fourth output of the first decoder and the first input of the second counter, the outputs of which are connected to the inputs of the second group of the fourth multiplexer and the inputs of the first decoder, the first output of which is connected to the fourth ^ inputs of the interface units, seventh the inputs of which are connected to the sixth output of the control unit, the first input of which is connected to the second output of the first decoder, the third output of which • is connected to the sixth inputs of the blocks the interface and the second input of the control unit, the third output of which is connected to the input of the second decoder, the last output of which is connected to the third input of the control unit, the fourth output of which is connected to the second inputs of the interface units, the eighth inputs of which are connected respectively to the first outputs of the second registers of the group, the second outputs which are connected respectively with the outputs of the first counters of the group, the outputs of which are connected with the inputs of the first group of the second multiplexer, the outputs of which are connected with the inputs of the second group of the first multiplexer, the inputs of the first group of which are connected to the inputs of the first group of the control unit and are the address inputs of the device group, the second input of the second counter is connected to the fifth output of the control unit, the third output of which is connected to the input of the first multiplexer and the first input of the first counter, the second input of which connected to the first output of the control unit, the seventh output of which is connected to the input of the memory unit, the inputs of the second group of the third multiplexer are connected respectively with the outputs of the register in the first group, the outputs of the group of which are connected respectively to the inputs of the registers of the group, the outputs of the group of which are connected to the inputs of the third group of the third multiplexer, the outputs of the first group of the control unit are connected respectively to the first inputs of the registers of the first group, the second inputs of which are connected respectively to the outputs of the third i group of the block control, the outputs of the fourth group of which are connected respectively to the first inputs of the registers of the second group, the second inputs of which are connected respectively to the inputs of the fifth groups of the control unit, the outputs of the sixth group of which are connected respectively to the second inputs of the counters of the group, the third inputs of which are connected respectively to the inputs of the seventh group of the control unit, the inputs of the second group, the second output, the fourth and fifth inputs of which are respectively the interrupt outputs of the group, the response output, the input recording and input device settings. 2. The device according to claim 1, characterized in that the control unit comprises a first and second decoders, a multiphase generator, a frequency divider, first, second, third triggers, first, second, third and fourth elements OR, first, second, third, fourth , fifth, sixth, seventh, eighth and ninth elements And, the first, second, third, fourth, fifth and sixth demultiplexers, the outputs and inputs of the group of which are respectively the outputs of the second, third, fourth, fifth, sixth and seventh groups and the inputs of the third group unit, first phase output of the second generator is connected to the input of the frequency divider, the second input of the decoder, the ₽ input of the second trigger and is the first output of the block, the second output of the multiphase generator is connected to the third input of the second element And the second input of the fifth element And, the output of which is connected to the input of the third demultiplexer, the third the output of the multiphase generator is connected to the second inputs of the seventh and eighth elements And, the outputs of which are connected respectively to the inputs of the fifth and sixth demultiplexers, the fourth output of the multiphase generator the ora is connected to the second inputs of the fourth and sixth elements And is the fourth output of the device, the inputs of the group of the first and second decoders are the inputs of the first group of the block, the first input of the first element And is the second input of the block, the first input of the first decoder, the input of the second decoder and R- the input of the first trigger is the fourth input of the block, the R-input of the third trigger is the third input of the block, the first input of the ninth element And the second input of the third element And are the first input of the block, the second input of the ninth And, the fourth input of the sixth AND element, the first and second inputs of the second OR element, are the inputs of the second block group, the second inputs of the third and fourth OR elements are the fifth block input, the outputs of the first decoder are connected to the inputs of the group of the first OR element and are the outputs the first group of the block, the output of the first OR element is connected to the 5-input of the first trigger, the direct output of which is the second output of the block, the inverse output of the first trigger is connected to the first input of the second AND element, the output of which is connected to 5 the second trigger, the output of which is connected to the input of the first OR element and is the seventh output of the block, the output of the first AND element is the sixth output of the block, the output of the frequency divider is connected to the second input of the first AND element, the S-input of the third trigger and is the fifth output of the block. direct output of the third flip-flop connected to the first input of the third aND gate _t and a third output unit, an output of the second decoder coupled to the second input of the second aND gate, whose fourth input is connected to the inverted output of the third t iggera, the output of third AND \ connected to the first input of the fourth-j th, fifth, sixth, seventh and eighth AND gates, the third input posled1124278 it is connected to an inverted output of the second OR gate. whose direct output is connected to the third input of the seventh AND element, the second input of the second OR element is connected to the third input of the sixth AND element and the third input of the ninth AND element, the output of which is connected to the input of the first demultiplexer, the first input of the second OR element is connected to the third inputs of the fifth and of the fourth AND element, the output of the last is connected to the first input of the third OR element, the output of which is connected to the input of the second demultiplexer, the output of the sixth AND element is connected to the first input of the fourth OR element, output One of which is connected to the input of the fourth demultiplexer.